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drm/i915/glk: Add MIPIIO Enable/disable sequence
v2: Addressed Jani's Review comments(renamed bit field macros) v3: Jani's Review comment for aligning code to platforms and added wrapper functions. v4: Corrected enable/disable seuqence as per BSPEC v5: Corrected waiting twice for same bit (Review comments: Jani) v6: Rebased to Han's patches(dsi restructuring code) Signed-off-by: Deepak M <m.deepak@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1488352893-29916-2-git-send-email-madhav.chauhan@intel.com
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f4c3a88e5f
commit
4644848369
1 changed files with 195 additions and 11 deletions
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@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
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return true;
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}
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static void glk_dsi_device_ready(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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enum port port;
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u32 tmp, val;
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/* Set the MIPI mode
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* If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
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* Power ON MIPI IO first and then write into IO reset and LP wake bits
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*/
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for_each_dsi_port(port, intel_dsi->ports) {
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tmp = I915_READ(MIPI_CTRL(port));
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I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
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}
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/* Put the IO into reset */
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tmp = I915_READ(MIPI_CTRL(PORT_A));
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tmp &= ~GLK_MIPIIO_RESET_RELEASED;
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I915_WRITE(MIPI_CTRL(PORT_A), tmp);
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/* Program LP Wake */
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for_each_dsi_port(port, intel_dsi->ports) {
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tmp = I915_READ(MIPI_CTRL(port));
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tmp |= GLK_LP_WAKE;
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I915_WRITE(MIPI_CTRL(port), tmp);
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}
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/* Wait for Pwr ACK */
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_wait_for_register(dev_priv,
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MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
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GLK_MIPIIO_PORT_POWERED, 20))
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DRM_ERROR("MIPIO port is powergated\n");
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}
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/* Wait for MIPI PHY status bit to set */
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_wait_for_register(dev_priv,
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MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
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GLK_PHY_STATUS_PORT_READY, 20))
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DRM_ERROR("PHY is not ON\n");
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}
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/* Get IO out of reset */
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tmp = I915_READ(MIPI_CTRL(PORT_A));
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I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
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/* Get IO out of Low power state*/
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for_each_dsi_port(port, intel_dsi->ports) {
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if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
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val = I915_READ(MIPI_DEVICE_READY(port));
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val &= ~ULPS_STATE_MASK;
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val |= DEVICE_READY;
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I915_WRITE(MIPI_DEVICE_READY(port), val);
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usleep_range(10, 15);
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}
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/* Enter ULPS */
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val = I915_READ(MIPI_DEVICE_READY(port));
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val &= ~ULPS_STATE_MASK;
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val |= (ULPS_STATE_ENTER | DEVICE_READY);
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I915_WRITE(MIPI_DEVICE_READY(port), val);
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/* Wait for ULPS Not active */
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if (intel_wait_for_register(dev_priv,
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MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
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GLK_ULPS_NOT_ACTIVE, 20))
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/* Exit ULPS */
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val = I915_READ(MIPI_DEVICE_READY(port));
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val &= ~ULPS_STATE_MASK;
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val |= (ULPS_STATE_EXIT | DEVICE_READY);
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I915_WRITE(MIPI_DEVICE_READY(port), val);
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/* Enter Normal Mode */
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val = I915_READ(MIPI_DEVICE_READY(port));
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val &= ~ULPS_STATE_MASK;
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val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
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I915_WRITE(MIPI_DEVICE_READY(port), val);
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tmp = I915_READ(MIPI_CTRL(port));
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tmp &= ~GLK_LP_WAKE;
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I915_WRITE(MIPI_CTRL(port), tmp);
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}
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/* Wait for Stop state */
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_wait_for_register(dev_priv,
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MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
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GLK_DATA_LANE_STOP_STATE, 20))
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DRM_ERROR("Date lane not in STOP state\n");
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}
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/* Wait for AFE LATCH */
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_wait_for_register(dev_priv,
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BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
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AFE_LATCHOUT, 20))
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DRM_ERROR("D-PHY not entering LP-11 state\n");
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}
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}
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static void bxt_dsi_device_ready(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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@ -429,11 +532,79 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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vlv_dsi_device_ready(encoder);
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else if (IS_GEN9_LP(dev_priv))
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else if (IS_BROXTON(dev_priv))
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bxt_dsi_device_ready(encoder);
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else if (IS_GEMINILAKE(dev_priv))
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glk_dsi_device_ready(encoder);
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}
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static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
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static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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enum port port;
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u32 val;
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/* Enter ULPS */
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for_each_dsi_port(port, intel_dsi->ports) {
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val = I915_READ(MIPI_DEVICE_READY(port));
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val &= ~ULPS_STATE_MASK;
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val |= (ULPS_STATE_ENTER | DEVICE_READY);
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I915_WRITE(MIPI_DEVICE_READY(port), val);
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}
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/* Wait for MIPI PHY status bit to unset */
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_wait_for_register(dev_priv,
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MIPI_CTRL(port),
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GLK_PHY_STATUS_PORT_READY, 0, 20))
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DRM_ERROR("PHY is not turning OFF\n");
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}
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/* Wait for Pwr ACK bit to unset */
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_wait_for_register(dev_priv,
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MIPI_CTRL(port),
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GLK_MIPIIO_PORT_POWERED, 0, 20))
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DRM_ERROR("MIPI IO Port is not powergated\n");
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}
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}
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static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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enum port port;
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u32 tmp;
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/* Put the IO into reset */
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tmp = I915_READ(MIPI_CTRL(PORT_A));
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tmp &= ~GLK_MIPIIO_RESET_RELEASED;
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I915_WRITE(MIPI_CTRL(PORT_A), tmp);
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/* Wait for MIPI PHY status bit to unset */
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_wait_for_register(dev_priv,
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MIPI_CTRL(port),
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GLK_PHY_STATUS_PORT_READY, 0, 20))
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DRM_ERROR("PHY is not turning OFF\n");
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}
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/* Clear MIPI mode */
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for_each_dsi_port(port, intel_dsi->ports) {
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tmp = I915_READ(MIPI_CTRL(port));
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tmp &= ~GLK_MIPIIO_ENABLE;
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I915_WRITE(MIPI_CTRL(port), tmp);
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}
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}
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static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
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{
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glk_dsi_enter_low_power_mode(encoder);
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glk_dsi_disable_mipi_io(encoder);
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}
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static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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@ -670,6 +841,17 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
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}
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}
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static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
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IS_BROXTON(dev_priv))
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vlv_dsi_clear_device_ready(encoder);
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else if (IS_GEMINILAKE(dev_priv))
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glk_dsi_clear_device_ready(encoder);
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}
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static void intel_dsi_post_disable(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state)
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@ -1314,18 +1496,20 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)
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enum port port;
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u32 val;
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for_each_dsi_port(port, intel_dsi->ports) {
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/* Panel commands can be sent when clock is in LP11 */
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I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
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if (!IS_GEMINILAKE(dev_priv)) {
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for_each_dsi_port(port, intel_dsi->ports) {
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/* Panel commands can be sent when clock is in LP11 */
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I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
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intel_dsi_reset_clocks(encoder, port);
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I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
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intel_dsi_reset_clocks(encoder, port);
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I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
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val = I915_READ(MIPI_DSI_FUNC_PRG(port));
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val &= ~VID_MODE_FORMAT_MASK;
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I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
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val = I915_READ(MIPI_DSI_FUNC_PRG(port));
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val &= ~VID_MODE_FORMAT_MASK;
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I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
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I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
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I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
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}
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}
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}
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