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clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328"
This reverts commit82f4b67f01
. According to a subsequent revert in the vendor kernel, the original change was based on unclear documentation and was in fact incorrect. Emprically, my board's HS200 eMMC at 200MHZ apparently gets lucky with a phase where this had no impact, but limiting max-frequency to 150MHz to match the nominal capability of the I/O pins made it virtually unusable, constantly throwing errors and retuning. With this revert, it starts behaving perfectly at 150MHz too. Fixes:82f4b67f01
("clk: rockchip: fix wrong mmc sample phase shift for rk3328") Signed-off-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://lore.kernel.org/r/c80eb52e34c03f817586b6b7912fbd4e31be9079.1589475794.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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commit
465931e708
1 changed files with 4 additions and 4 deletions
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@ -808,22 +808,22 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
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MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
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RK3328_SDMMC_CON0, 1),
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MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
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RK3328_SDMMC_CON1, 0),
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RK3328_SDMMC_CON1, 1),
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MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
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RK3328_SDIO_CON0, 1),
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MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
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RK3328_SDIO_CON1, 0),
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RK3328_SDIO_CON1, 1),
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MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
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RK3328_EMMC_CON0, 1),
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MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
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RK3328_EMMC_CON1, 0),
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RK3328_EMMC_CON1, 1),
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MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",
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RK3328_SDMMC_EXT_CON0, 1),
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MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",
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RK3328_SDMMC_EXT_CON1, 0),
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RK3328_SDMMC_EXT_CON1, 1),
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};
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static const char *const rk3328_critical_clocks[] __initconst = {
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