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Renesas DTS updates for v6.9

Browse source 
- Add GPIO keys and watchdog support for the RZ/G3S SMARC development
     board,
   - Add GNSS support for Renesas ULCB development boards equipped with
     the Shimafuji Kingfisher extension,
   - Add support for the standalone White Hawk CPU board,
   - Add support for the R-Car V4H ES2.0 (R8A779G2) SoC and the White
     Hawk Single development board,
   - Add initial support for the R-Car V4M (R8A779H0) SoC and the Gray
     Hawk Single development board,
   - Add camera support for the RZ/G2UL SoC,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.9

  - Add GPIO keys and watchdog support for the RZ/G3S SMARC development
    board,
  - Add GNSS support for Renesas ULCB development boards equipped with
    the Shimafuji Kingfisher extension,
  - Add support for the standalone White Hawk CPU board,
  - Add support for the R-Car V4H ES2.0 (R8A779G2) SoC and the White
    Hawk Single development board,
  - Add initial support for the R-Car V4M (R8A779H0) SoC and the Gray
    Hawk Single development board,
  - Add camera support for the RZ/G2UL SoC,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (29 commits)
  arm64: dts: renesas: gray-hawk-single: Enable watchdog timer
  arm64: dts: renesas: r8a779h0: Add RWDT node
  arm64: dts: renesas: Improve TMU interrupt descriptions
  ARM: dts: renesas: Improve TMU interrupt descriptions
  arm64: dts: renesas: r9a07g043u: Add CSI and CRU nodes
  arm64: dts: renesas: Add Gray Hawk Single board support
  arm64: dts: renesas: Add Renesas R8A779H0 SoC support
  arm64: dts: renesas: rzg3s-smarc-som: Enable the watchdog interface
  arm64: dts: renesas: r9a08g045: Add watchdog node
  arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2
  dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions
  dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support
  dt-bindings: power: Add r8a779h0 SYSC power domain definitions
  dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support
  arm64: dts: renesas: r8a779g2: Add White Hawk Single support
  arm64: dts: renesas: Add Renesas R8A779G2 SoC support
  arm64: dts: renesas: white-hawk: Factor out common parts
  arm64: dts: renesas: white-hawk-cpu: Factor out common parts
  arm64: dts: renesas: white-hawk: Add SoC name to top-level comment
  arm64: dts: renesas: white-hawk: Drop SoC parts from sub boards
  ...

Link: https://lore.kernel.org/r/cover.1707487834.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-02-29 16:06:49 +01:00
commit 466b99ac51
41 changed files with 1233 additions and 540 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
View file

@ -50,6 +50,7 @@ properties:
- renesas,r8a779a0-cpg-mssr # R-Car V3U
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
- renesas,r8a779g0-cpg-mssr # R-Car V4H
- renesas,r8a779h0-cpg-mssr # R-Car V4M
reg:
maxItems: 1

1
Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
View file

@ -45,6 +45,7 @@ properties:
- renesas,r8a779a0-sysc # R-Car V3U
- renesas,r8a779f0-sysc # R-Car S4-8
- renesas,r8a779g0-sysc # R-Car V4H
- renesas,r8a779h0-sysc # R-Car V4M
reg:
maxItems: 1

12
arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts
View file

@ -209,6 +209,18 @@ &cmt1 {
status = "okay";
};
&extal1_clk {
clock-frequency = <26000000>;
};
&extal2_clk {
clock-frequency = <48000000>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
scifa0_pins: scifa0 {
groups = "scifa0_data";

23
arch/arm/boot/dts/renesas/r8a73a4.dtsi
View file

@ -450,17 +450,20 @@ clocks {
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
extal1_clk: extal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
extal2_clk: extal2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
fsiack_clk: fsiack {
compatible = "fixed-clock";
@ -621,6 +624,13 @@ main_div2_clk: main_div2 {
clock-div = <2>;
clock-mult = <1>;
};
cp_clk: cp {
compatible = "fixed-factor-clock";
clocks = <&main_div2_clk>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};
pll0_div2_clk: pll0_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
@ -686,9 +696,8 @@ R8A73A4_CLK_CMT1
mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
<&main_div2_clk>,
<&cpg_clocks R8A73A4_CLK_HP>,
clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
<&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
<&cpg_clocks R8A73A4_CLK_HP>;
#clock-cells = <1>;
clock-indices = <
@ -702,7 +711,7 @@ R8A73A4_CLK_IIC3
mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
#clock-cells = <1>;
clock-indices = <
R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8

2
arch/arm/boot/dts/renesas/r8a7740.dtsi
View file

@ -459,6 +459,7 @@ tmu0: timer@fff80000 {
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
clock-names = "fck";
power-domains = <&pd_a4r>;
@ -474,6 +475,7 @@ tmu1: timer@fff90000 {
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
clock-names = "fck";
power-domains = <&pd_a4r>;

9
arch/arm/boot/dts/renesas/r8a7778.dtsi
View file

@ -199,7 +199,9 @@ tmu0: timer@ffd80000 {
reg = <0xffd80000 0x30>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
@ -214,7 +216,9 @@ tmu1: timer@ffd81000 {
reg = <0xffd81000 0x30>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
@ -230,6 +234,7 @@ tmu2: timer@ffd82000 {
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
clock-names = "fck";
power-domains = <&cpg_clocks>;

9
arch/arm/boot/dts/renesas/r8a7779.dtsi
View file

@ -402,7 +402,9 @@ tmu0: timer@ffd80000 {
reg = <0xffd80000 0x30>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck";
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
@ -417,7 +419,9 @@ tmu1: timer@ffd81000 {
reg = <0xffd81000 0x30>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
clock-names = "fck";
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
@ -433,6 +437,7 @@ tmu2: timer@ffd82000 {
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
clock-names = "fck";
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

5
arch/arm64/boot/dts/renesas/Makefile
View file

@ -82,10 +82,15 @@ dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb
dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f4-s4sk.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-cpu.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtbo
r8a779g0-white-hawk-ard-audio-da7212-dtbs := r8a779g0-white-hawk.dtb r8a779g0-white-hawk-ard-audio-da7212.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single.dtb
dtb-$(CONFIG_ARCH_R8A779H0) += r8a779h0-gray-hawk-single.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb
r8a779m1-salvator-xs-panel-aa104xd12-dtbs := r8a779m1-salvator-xs.dtb salvator-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs-panel-aa104xd12.dtb

11
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View file

@ -529,6 +529,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
@ -541,7 +542,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
@ -554,7 +557,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
@ -568,6 +573,7 @@ tmu3: timer@e6fe0000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
@ -581,6 +587,7 @@ tmu4: timer@ffc00000 {
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;

11
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View file

@ -413,6 +413,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
@ -425,7 +426,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
@ -438,7 +441,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
@ -452,6 +457,7 @@ tmu3: timer@e6fe0000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
@ -465,6 +471,7 @@ tmu4: timer@ffc00000 {
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;

11
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View file

@ -384,6 +384,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
@ -396,7 +397,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
@ -409,7 +412,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
@ -423,6 +428,7 @@ tmu3: timer@e6fe0000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
@ -436,6 +442,7 @@ tmu4: timer@ffc00000 {
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

11
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View file

@ -593,6 +593,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
@ -605,7 +606,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
@ -618,7 +621,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
@ -632,6 +637,7 @@ tmu3: timer@e6fe0000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
@ -645,6 +651,7 @@ tmu4: timer@ffc00000 {
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

11
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View file

@ -614,6 +614,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@ -626,7 +627,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@ -639,7 +642,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@ -653,6 +658,7 @@ tmu3: timer@e6fe0000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@ -666,6 +672,7 @@ tmu4: timer@ffc00000 {
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

11
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View file

@ -578,6 +578,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@ -590,7 +591,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@ -603,7 +606,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@ -617,6 +622,7 @@ tmu3: timer@e6fe0000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@ -630,6 +636,7 @@ tmu4: timer@ffc00000 {
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

11
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View file

@ -578,6 +578,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
@ -590,7 +591,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
@ -603,7 +606,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
@ -617,6 +622,7 @@ tmu3: timer@e6fe0000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
@ -630,6 +636,7 @@ tmu4: timer@ffc00000 {
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

11
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View file

@ -449,6 +449,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@ -461,7 +462,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@ -474,7 +477,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@ -488,6 +493,7 @@ tmu3: timer@e6fe0000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@ -501,6 +507,7 @@ tmu4: timer@ffc00000 {
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;

11
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View file

@ -328,6 +328,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
@ -340,7 +341,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
@ -353,7 +356,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
@ -367,6 +372,7 @@ tmu3: timer@e6fe0000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
@ -380,6 +386,7 @@ tmu4: timer@ffc00000 {
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;

17
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View file

@ -357,6 +357,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
@ -369,7 +370,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
@ -382,7 +385,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
@ -395,7 +400,9 @@ tmu3: timer@e6fe0000 {
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
@ -408,7 +415,9 @@ tmu4: timer@ffc00000 {
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;

11
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View file

@ -415,6 +415,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
@ -427,7 +428,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
@ -440,7 +443,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
@ -454,6 +459,7 @@ tmu3: timer@e6fe0000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
@ -467,6 +473,7 @@ tmu4: timer@ffc00000 {
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

11
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View file

@ -336,6 +336,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
@ -348,7 +349,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
@ -361,7 +364,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
@ -375,6 +380,7 @@ tmu3: timer@e6fe0000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
@ -388,6 +394,7 @@ tmu4: timer@ffc00000 {
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;

17
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View file

@ -370,6 +370,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 713>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -382,7 +383,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 714>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -395,7 +398,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 715>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -408,7 +413,9 @@ tmu3: timer@e6fe0000 {
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 716>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -421,7 +428,9 @@ tmu4: timer@ffc00000 {
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 717>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

17
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
View file

@ -501,6 +501,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 713>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
@ -513,7 +514,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 714>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
@ -526,7 +529,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 715>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
@ -539,7 +544,9 @@ tmu3: timer@e6fe0000 {
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 716>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
@ -552,7 +559,9 @@ tmu4: timer@ffc00000 {
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 717>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;

13
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dts Normal file
View file

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the standalone R-Car V4H White Hawk CPU board
*
* Copyright (C) 2023 Glider bv
*/
/dts-v1/;
#include "r8a779g0-white-hawk-cpu.dtsi"
/ {
model = "Renesas White Hawk CPU board based on r8a779g0";
};

368
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
View file

@ -1,378 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the White Hawk CPU board
* Device Tree Source for the R-Car V4H White Hawk CPU board
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include "r8a779g0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "white-hawk-cpu-common.dtsi"
/ {
model = "Renesas White Hawk CPU board";
compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
aliases {
ethernet0 = &avb0;
serial0 = &hscif0;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:921600n8";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW47";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW48";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW49";
wakeup-source;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
led-1 {
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
};
led-2 {
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
};
led-3 {
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x1 0x00000000>;
};
mini-dp-con {
compatible = "dp-connector";
label = "CN5";
type = "mini";
port {
mini_dp_con_in: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sn65dsi86_refclk: clk-x6 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
};
};
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio7>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
};
};
&dsi0 {
status = "okay";
ports {
port@1 {
dsi0_out: endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&du {
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
io_expander_a: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
bridge@2c {
compatible = "ti,sn65dsi86";
reg = <0x2c>;
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
vccio-supply = <&reg_1p8v>;
vpll-supply = <&reg_1p8v>;
vcca-supply = <&reg_1p2v>;
vcc-supply = <&reg_1p2v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
remote-endpoint = <&mini_dp_con_in>;
};
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
"avb0_txcrefclk";
function = "avb0";
};
pins_mdio {
groups = "avb0_mdio";
drive-strength = <21>;
};
pins_mii {
groups = "avb0_rgmii";
drive-strength = <21>;
};
};
hscif0_pins: hscif0 {
groups = "hscif0_data";
function = "hscif0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
keys_pins: keys {
pins = "GP_5_0", "GP_5_1", "GP_5_2";
bias-pull-up;
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x0 0x1200000>;
read-only;
};
user@1200000 {
reg = <0x1200000 0x2e00000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};

58
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
View file

@ -1,69 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the White Hawk CPU and BreakOut boards
* Device Tree Source for the R-Car V4H White Hawk CPU and BreakOut boards
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779g0-white-hawk-cpu.dtsi"
#include "r8a779g0-white-hawk-csi-dsi.dtsi"
#include "r8a779g0-white-hawk-ethernet.dtsi"
#include "white-hawk-common.dtsi"
/ {
model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
can_transceiver0: can-phy0 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
max-bitrate = <5000000>;
};
};
&can_clk {
clock-frequency = <40000000>;
};
&canfd {
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
phys = <&can_transceiver0>;
};
channel1 {
status = "okay";
};
};
&i2c0 {
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "breakout-board";
reg = <0x51>;
pagesize = <8>;
};
};
&pfc {
can_clk_pins: can-clk {
groups = "can_clk";
function = "can_clk";
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
canfd1_pins: canfd1 {
groups = "canfd1_data";
function = "canfd1";
};
};

101
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View file

@ -161,11 +161,6 @@ L3_CA76_1: cache-controller-1 {
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -185,13 +180,24 @@ pmu_a76 {
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
/* External SCIF clock - to be overridden by boards that provide it */
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
/* External SCIF clocks - to be overridden by boards that provide them */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
scif_clk2: scif2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@ -479,6 +485,7 @@ tmu0: timer@e61e0000 {
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 713>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
@ -491,7 +498,9 @@ tmu1: timer@e6fc0000 {
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 714>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
@ -504,7 +513,9 @@ tmu2: timer@e6fd0000 {
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 715>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
@ -517,7 +528,9 @@ tmu3: timer@e6fe0000 {
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 716>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
@ -530,7 +543,9 @@ tmu4: timer@ffc00000 {
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 717>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
@ -681,7 +696,7 @@ hscif2: serial@e6560000 {
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 516>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
<&scif_clk>;
<&scif_clk2>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x35>, <&dmac0 0x34>,
<&dmac1 0x35>, <&dmac1 0x34>;
@ -1057,7 +1072,7 @@ scif4: serial@e6c40000 {
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 705>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
<&scif_clk>;
<&scif_clk2>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>,
<&dmac1 0x59>, <&dmac1 0x58>;
@ -1777,6 +1792,37 @@ ssi0: ssi-0 {
};
};
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a779g0",
"renesas,rcar-gen4-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 706>,
<&cpg CPG_CORE R8A779G0_CLK_SD0H>;
clock-names = "core", "clkh";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 706>;
max-frequency = <200000000>;
iommus = <&ipmmu_ds0 32>;
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a779g0-rpc-if",
"renesas,rcar-gen4-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 629>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 629>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ipmmu_rt0: iommu@ee480000 {
compatible = "renesas,ipmmu-r8a779g0",
"renesas,rcar-gen4-ipmmu-vmsa";
@ -1886,37 +1932,6 @@ ipmmu_mm: iommu@eefc0000 {
#iommu-cells = <1>;
};
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a779g0",
"renesas,rcar-gen4-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 706>,
<&cpg CPG_CORE R8A779G0_CLK_SD0H>;
clock-names = "core", "clkh";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 706>;
max-frequency = <200000000>;
iommus = <&ipmmu_ds0 32>;
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a779g0-rpc-if",
"renesas,rcar-gen4-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 629>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 629>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;

26
arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts Normal file
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@ -0,0 +1,26 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H ES2.0 White Hawk Single board
*
* Copyright (C) 2023 Glider bv
*/
/dts-v1/;
#include "r8a779g2.dtsi"
#include "white-hawk-cpu-common.dtsi"
#include "white-hawk-common.dtsi"
/ {
model = "Renesas White Hawk Single board based on r8a779g2";
compatible = "renesas,white-hawk-single", "renesas,r8a779g2",
"renesas,r8a779g0";
};
&hscif0 {
uart-has-rtscts;
};
&hscif0_pins {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};

12
arch/arm64/boot/dts/renesas/r8a779g2.dtsi Normal file
View file

@ -0,0 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H (R8A779G2) SoC
*
* Copyright (C) 2023 Glider bv
*/
#include "r8a779g0.dtsi"
/ {
compatible = "renesas,r8a779g2", "renesas,r8a779g0";
};

57
arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts Normal file
View file

@ -0,0 +1,57 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4M Gray Hawk Single board
*
* Copyright (C) 2023 Renesas Electronics Corp.
* Copyright (C) 2024 Glider bv
*/
/dts-v1/;
#include "r8a779h0.dtsi"
/ {
model = "Renesas Gray Hawk Single board based on r8a779h0";
compatible = "renesas,gray-hawk-single", "renesas,r8a779h0";
aliases {
serial0 = &hscif0;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:921600n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x1 0x80000000>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
uart-has-rtscts;
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};

132
arch/arm64/boot/dts/renesas/r8a779h0.dtsi Normal file
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@ -0,0 +1,132 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4M (R8A779H0) SoC
*
* Copyright (C) 2023 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/renesas,r8a779h0-sysc.h>
/ {
compatible = "renesas,r8a779h0";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
a76_0: cpu@0 {
compatible = "arm,cortex-a76";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
};
};
extal_clk: extal-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
extalr_clk: extalr-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
pmu-a76 {
compatible = "arm,cortex-a76-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a779h0-wdt",
"renesas,rcar-gen4-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 907>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779h0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a779h0-rst";
reg = <0 0xe6160000 0 0x4000>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a779h0-sysc";
reg = <0 0xe6180000 0 0x4000>;
#power-domain-cells = <1>;
};
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a779h0",
"renesas,rcar-gen4-hscif", "renesas,hscif";
reg = <0 0xe6540000 0 0x60>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>,
<&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 514>;
status = "disabled";
};
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};

69
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
View file

@ -61,6 +61,75 @@ &pinctrl {
&soc {
interrupt-parent = <&gic>;
cru: video@10830000 {
compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru";
reg = <0 0x10830000 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
<&cpg CPG_MOD R9A07G043_CRU_PCLK>,
<&cpg CPG_MOD R9A07G043_CRU_ACLK>;
clock-names = "video", "apb", "axi";
interrupts = <SOC_PERIPHERAL_IRQ(167) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(168) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(169) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
resets = <&cpg R9A07G043_CRU_PRESETN>,
<&cpg R9A07G043_CRU_ARESETN>;
reset-names = "presetn", "aresetn";
power-domains = <&cpg>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
crucsi2: endpoint@0 {
reg = <0>;
remote-endpoint = <&csi2cru>;
};
};
};
};
csi2: csi2@10830400 {
compatible = "renesas,r9a07g043-csi2", "renesas,rzg2l-csi2";
reg = <0 0x10830400 0 0xfc00>;
interrupts = <SOC_PERIPHERAL_IRQ(166) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>,
<&cpg CPG_MOD R9A07G043_CRU_VCLK>,
<&cpg CPG_MOD R9A07G043_CRU_PCLK>;
clock-names = "system", "video", "apb";
resets = <&cpg R9A07G043_CRU_PRESETN>,
<&cpg R9A07G043_CRU_CMN_RSTB>;
reset-names = "presetn", "cmn-rstb";
power-domains = <&cpg>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi2cru: endpoint@0 {
reg = <0>;
remote-endpoint = <&crucsi2>;
};
};
};
};
irqc: interrupt-controller@110a0000 {
compatible = "renesas,r9a07g043u-irqc",
"renesas,rzg2l-irqc";

14
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
View file

@ -264,6 +264,20 @@ gic: interrupt-controller@12400000 {
<0x0 0x12440000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
wdt0: watchdog@12800800 {
compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
reg = <0 0x12800800 0 0x400>;
clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
<&cpg CPG_MOD R9A08G045_WDT0_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A08G045_WDT0_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
};
timer {

5
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
View file

@ -336,3 +336,8 @@ mux {
};
};
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};

53
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
View file

@ -6,6 +6,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
@ -14,6 +15,37 @@ aliases {
mmc1 = &sdhi1;
};
keys {
compatible = "gpio-keys";
key-1 {
interrupts = <RZG2L_GPIO(18, 0) IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&pinctrl>;
linux,code = <KEY_1>;
label = "USER_SW1";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
interrupts = <RZG2L_GPIO(0, 1) IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&pinctrl>;
linux,code = <KEY_2>;
label = "USER_SW2";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
interrupts = <RZG2L_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&pinctrl>;
linux,code = <KEY_3>;
label = "USER_SW3";
wakeup-source;
debounce-interval = <20>;
};
};
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
@ -35,6 +67,27 @@ vccq_sdhi1: regulator-vccq-sdhi1 {
};
&pinctrl {
key-1-gpio-hog {
gpio-hog;
gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>;
input;
line-name = "key-1-gpio-irq";
};
key-2-gpio-hog {
gpio-hog;
gpios = <RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
input;
line-name = "key-2-gpio-irq";
};
key-3-gpio-hog {
gpio-hog;
gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_LOW>;
input;
line-name = "key-3-gpio-irq";
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
<RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */

42
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
View file

@ -32,13 +32,6 @@ hdmi1_con: endpoint {
};
};
accel_3v3: regulator-acc-3v3 {
compatible = "regulator-fixed";
regulator-name = "accel-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
hdmi_1v8: regulator-hdmi-1v8 {
compatible = "regulator-fixed";
regulator-name = "hdmi-1v8";
@ -46,20 +39,6 @@ hdmi_1v8: regulator-hdmi-1v8 {
regulator-max-microvolt = <1800000>;
};
hdmi_3v3: regulator-hdmi-3v3 {
compatible = "regulator-fixed";
regulator-name = "hdmi-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
snd_3p3v: regulator-snd_3p3v {
compatible = "regulator-fixed";
regulator-name = "snd-3.3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
snd_vcc5v: regulator-snd_vcc5v {
compatible = "regulator-fixed";
regulator-name = "snd-vcc5v";
@ -160,7 +139,7 @@ hdmi@3d {
avdd-supply = <&hdmi_1v8>;
dvdd-supply = <&hdmi_1v8>;
pvdd-supply = <&hdmi_1v8>;
dvdd-3v-supply = <&hdmi_3v3>;
dvdd-3v-supply = <&reg_3p3v>;
bgvdd-supply = <&hdmi_1v8>;
adi,input-depth = <8>;
@ -198,8 +177,8 @@ accelerometer@1d {
compatible = "st,lsm9ds0-imu";
reg = <0x1d>;
vdd-supply = <&accel_3v3>;
vddio-supply = <&accel_3v3>;
vdd-supply = <&reg_3p3v>;
vddio-supply = <&reg_3p3v>;
};
pcm3168a: audio-codec@44 {
@ -209,8 +188,8 @@ pcm3168a: audio-codec@44 {
clocks = <&clksndsel>;
clock-names = "scki";
VDD1-supply = <&snd_3p3v>;
VDD2-supply = <&snd_3p3v>;
VDD1-supply = <&reg_3p3v>;
VDD2-supply = <&reg_3p3v>;
VCCAD1-supply = <&snd_vcc5v>;
VCCAD2-supply = <&snd_vcc5v>;
VCCDA1-supply = <&snd_vcc5v>;
@ -221,8 +200,8 @@ gyroscope@6b {
compatible = "st,lsm9ds0-gyro";
reg = <0x6b>;
vdd-supply = <&accel_3v3>;
vddio-supply = <&accel_3v3>;
vdd-supply = <&reg_3p3v>;
vddio-supply = <&reg_3p3v>;
};
};
};
@ -417,6 +396,13 @@ &scif1 {
pinctrl-names = "default";
status = "okay";
gnss {
compatible = "u-blox,neo-m8";
reset-gpios = <&gpio_exp_75 6 GPIO_ACTIVE_LOW>;
vcc-supply = <&reg_3p3v>;
current-speed = <9600>;
};
};
&sdhi3 {

65
arch/arm64/boot/dts/renesas/white-hawk-common.dtsi Normal file
View file

@ -0,0 +1,65 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the common parts shared by the White Hawk BreakOut
* and White Hawk Single boards
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include "white-hawk-csi-dsi.dtsi"
#include "white-hawk-ethernet.dtsi"
/ {
can_transceiver0: can-phy0 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
max-bitrate = <5000000>;
};
};
&can_clk {
clock-frequency = <40000000>;
};
&canfd {
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
phys = <&can_transceiver0>;
};
channel1 {
status = "okay";
};
};
&i2c0 {
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "breakout-board";
reg = <0x51>;
pagesize = <8>;
};
};
&pfc {
can_clk_pins: can-clk {
groups = "can_clk";
function = "can_clk";
};
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
canfd1_pins: canfd1 {
groups = "canfd1_data";
function = "canfd1";
};
};

375
arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi Normal file
View file

@ -0,0 +1,375 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the common parts shared by the White Hawk CPU and
* White Hawk Single boards
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
ethernet0 = &avb0;
serial0 = &hscif0;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:921600n8";
};
sn65dsi86_refclk: clk-x6 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW47";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW48";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW49";
wakeup-source;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
led-1 {
gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
};
led-2 {
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
};
led-3 {
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x1 0x00000000>;
};
mini-dp-con {
compatible = "dp-connector";
label = "CN5";
type = "mini";
port {
mini_dp_con_in: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio7>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
};
};
&dsi0 {
status = "okay";
ports {
port@1 {
dsi0_out: endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&du {
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
io_expander_a: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
bridge@2c {
compatible = "ti,sn65dsi86";
reg = <0x2c>;
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
vccio-supply = <&reg_1p8v>;
vpll-supply = <&reg_1p8v>;
vcca-supply = <&reg_1p2v>;
vcc-supply = <&reg_1p2v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
remote-endpoint = <&mini_dp_con_in>;
};
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
"avb0_txcrefclk";
function = "avb0";
};
pins_mdio {
groups = "avb0_mdio";
drive-strength = <21>;
};
pins_mii {
groups = "avb0_rgmii";
drive-strength = <21>;
};
};
hscif0_pins: hscif0 {
groups = "hscif0_data";
function = "hscif0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
keys_pins: keys {
pins = "GP_5_0", "GP_5_1", "GP_5_2";
bias-pull-up;
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x0 0x1200000>;
read-only;
};
user@1200000 {
reg = <0x1200000 0x2e00000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};

2
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi → arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board
* Device Tree Source for the White Hawk CSI/DSI sub-board
*
* Copyright (C) 2022 Glider bv
*/

2
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi → arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1)
* Device Tree Source for the White Hawk RAVB/Ethernet(1000Base-T1)
* sub-board
*
* Copyright (C) 2022 Glider bv

96
include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h Normal file
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@ -0,0 +1,96 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2023 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a779h0 CPG Core Clocks */
#define R8A779H0_CLK_ZX 0
#define R8A779H0_CLK_ZD 1
#define R8A779H0_CLK_ZS 2
#define R8A779H0_CLK_ZT 3
#define R8A779H0_CLK_ZTR 4
#define R8A779H0_CLK_S0D2 5
#define R8A779H0_CLK_S0D3 6
#define R8A779H0_CLK_S0D4 7
#define R8A779H0_CLK_S0D1_VIO 8
#define R8A779H0_CLK_S0D2_VIO 9
#define R8A779H0_CLK_S0D4_VIO 10
#define R8A779H0_CLK_S0D8_VIO 11
#define R8A779H0_CLK_VIOBUSD1 12
#define R8A779H0_CLK_VIOBUSD2 13
#define R8A779H0_CLK_S0D1_VC 14
#define R8A779H0_CLK_S0D2_VC 15
#define R8A779H0_CLK_S0D4_VC 16
#define R8A779H0_CLK_VCBUSD1 17
#define R8A779H0_CLK_VCBUSD2 18
#define R8A779H0_CLK_S0D2_MM 19
#define R8A779H0_CLK_S0D4_MM 20
#define R8A779H0_CLK_S0D2_U3DG 21
#define R8A779H0_CLK_S0D4_U3DG 22
#define R8A779H0_CLK_S0D2_RT 23
#define R8A779H0_CLK_S0D3_RT 24
#define R8A779H0_CLK_S0D4_RT 25
#define R8A779H0_CLK_S0D6_RT 26
#define R8A779H0_CLK_S0D2_PER 27
#define R8A779H0_CLK_S0D3_PER 28
#define R8A779H0_CLK_S0D4_PER 29
#define R8A779H0_CLK_S0D6_PER 30
#define R8A779H0_CLK_S0D12_PER 31
#define R8A779H0_CLK_S0D24_PER 32
#define R8A779H0_CLK_S0D1_HSC 33
#define R8A779H0_CLK_S0D2_HSC 34
#define R8A779H0_CLK_S0D4_HSC 35
#define R8A779H0_CLK_S0D8_HSC 36
#define R8A779H0_CLK_SVD1_IR 37
#define R8A779H0_CLK_SVD2_IR 38
#define R8A779H0_CLK_IMPAD1 39
#define R8A779H0_CLK_IMPAD4 40
#define R8A779H0_CLK_IMPB 41
#define R8A779H0_CLK_SVD1_VIP 42
#define R8A779H0_CLK_SVD2_VIP 43
#define R8A779H0_CLK_CL 44
#define R8A779H0_CLK_CL16M 45
#define R8A779H0_CLK_CL16M_MM 46
#define R8A779H0_CLK_CL16M_RT 47
#define R8A779H0_CLK_CL16M_PER 48
#define R8A779H0_CLK_CL16M_HSC 49
#define R8A779H0_CLK_ZC0 50
#define R8A779H0_CLK_ZC1 51
#define R8A779H0_CLK_ZC2 52
#define R8A779H0_CLK_ZC3 53
#define R8A779H0_CLK_ZB3 54
#define R8A779H0_CLK_ZB3D2 55
#define R8A779H0_CLK_ZB3D4 56
#define R8A779H0_CLK_ZG 57
#define R8A779H0_CLK_SD0H 58
#define R8A779H0_CLK_SD0 59
#define R8A779H0_CLK_RPC 60
#define R8A779H0_CLK_RPCD2 61
#define R8A779H0_CLK_MSO 62
#define R8A779H0_CLK_CANFD 63
#define R8A779H0_CLK_CSI 64
#define R8A779H0_CLK_FRAY 65
#define R8A779H0_CLK_IPC 66
#define R8A779H0_CLK_SASYNCRT 67
#define R8A779H0_CLK_SASYNCPERD1 68
#define R8A779H0_CLK_SASYNCPERD2 69
#define R8A779H0_CLK_SASYNCPERD4 70
#define R8A779H0_CLK_DSIEXT 71
#define R8A779H0_CLK_DSIREF 72
#define R8A779H0_CLK_ADGH 73
#define R8A779H0_CLK_OSC 74
#define R8A779H0_CLK_ZR0 75
#define R8A779H0_CLK_ZR1 76
#define R8A779H0_CLK_ZR2 77
#define R8A779H0_CLK_RGMII 78
#define R8A779H0_CLK_CPEX 79
#define R8A779H0_CLK_CP 80
#define R8A779H0_CLK_CBFUSA 81
#define R8A779H0_CLK_R 82
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */

49
include/dt-bindings/power/renesas,r8a779h0-sysc.h Normal file
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@ -0,0 +1,49 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2023 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__
/*
* These power domain indices match the Power Domain Register Numbers (PDR)
*/
#define R8A779H0_PD_A1E0D0C0 0
#define R8A779H0_PD_A1E0D0C1 1
#define R8A779H0_PD_A1E0D0C2 2
#define R8A779H0_PD_A1E0D0C3 3
#define R8A779H0_PD_A2E0D0 16
#define R8A779H0_PD_A3CR0 21
#define R8A779H0_PD_A3CR1 22
#define R8A779H0_PD_A3CR2 23
#define R8A779H0_PD_A33DGA 24
#define R8A779H0_PD_A23DGB 25
#define R8A779H0_PD_C4 31
#define R8A779H0_PD_A1DSP0 33
#define R8A779H0_PD_A2IMP01 34
#define R8A779H0_PD_A2PSC 35
#define R8A779H0_PD_A2CV0 36
#define R8A779H0_PD_A2CV1 37
#define R8A779H0_PD_A3IMR0 38
#define R8A779H0_PD_A3IMR1 39
#define R8A779H0_PD_A3VC 40
#define R8A779H0_PD_A2CN0 42
#define R8A779H0_PD_A1CN0 44
#define R8A779H0_PD_A1DSP1 45
#define R8A779H0_PD_A2DMA 47
#define R8A779H0_PD_A2CV2 48
#define R8A779H0_PD_A2CV3 49
#define R8A779H0_PD_A3IMR2 50
#define R8A779H0_PD_A3IMR3 51
#define R8A779H0_PD_A3PCI 52
#define R8A779H0_PD_A2PCIPHY 53
#define R8A779H0_PD_A3VIP0 56
#define R8A779H0_PD_A3VIP2 58
#define R8A779H0_PD_A3ISP0 60
#define R8A779H0_PD_A3DUL 62
/* Always-on power area */
#define R8A779H0_PD_ALWAYS_ON 64
#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */