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mmc: rtsx_pci: Fix support for speed-modes that relies on tuning
The TX/RX register should not be treated the same way to allow for better support of tuning. Fix this by using a default initial value for TX. Signed-off-by: Ricky Wu <ricky_wu@realtek.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200316025232.1167-1-ricky_wu@realtek.com [Ulf: Updated changelog] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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53dd0a7cd6
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4686392c32
5 changed files with 13 additions and 8 deletions
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@ -394,7 +394,7 @@ static const struct pcr_ops rts522a_pcr_ops = {
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void rts522a_init_params(struct rtsx_pcr *pcr)
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{
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rts5227_init_params(pcr);
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pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
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pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
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pcr->option.ocp_en = 1;
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@ -618,6 +618,7 @@ static const struct pcr_ops rts524a_pcr_ops = {
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void rts524a_init_params(struct rtsx_pcr *pcr)
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{
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rts5249_init_params(pcr);
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pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
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pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
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pcr->option.ltr_l1off_snooze_sspwrgate =
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LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
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@ -733,6 +734,7 @@ static const struct pcr_ops rts525a_pcr_ops = {
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void rts525a_init_params(struct rtsx_pcr *pcr)
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{
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rts5249_init_params(pcr);
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pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
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pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
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pcr->option.ltr_l1off_snooze_sspwrgate =
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LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
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@ -662,7 +662,7 @@ void rts5260_init_params(struct rtsx_pcr *pcr)
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pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
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pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
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pcr->aspm_en = ASPM_L1_EN;
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pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
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pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
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pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
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pcr->ic_version = rts5260_get_ic_version(pcr);
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@ -764,7 +764,7 @@ void rts5261_init_params(struct rtsx_pcr *pcr)
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pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
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pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
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pcr->aspm_en = ASPM_L1_EN;
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pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 27, 16);
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pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
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pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
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pcr->ic_version = rts5261_get_ic_version(pcr);
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@ -606,19 +606,22 @@ static int sd_change_phase(struct realtek_pci_sdmmc *host,
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u8 sample_point, bool rx)
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{
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struct rtsx_pcr *pcr = host->pcr;
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u16 SD_VP_CTL = 0;
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dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
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__func__, rx ? "RX" : "TX", sample_point);
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rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
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if (rx)
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if (rx) {
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SD_VP_CTL = SD_VPRX_CTL;
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rtsx_pci_write_register(pcr, SD_VPRX_CTL,
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PHASE_SELECT_MASK, sample_point);
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else
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} else {
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SD_VP_CTL = SD_VPTX_CTL;
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rtsx_pci_write_register(pcr, SD_VPTX_CTL,
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PHASE_SELECT_MASK, sample_point);
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rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
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rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET,
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}
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rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
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rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
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PHASE_NOT_RESET);
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rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
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rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
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