mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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ARM: tegra: single-zImage preparation work
Various cleanups and enhancements are made to core Tegra code towards the aim of including Tegra in a multi-platform ARM kernel: RTC, timer, and TWD are configured via device tree. SPARSE_IRQ is enabled. Tegra's debug_ll options are simplified, and the macros brought into line with other multi-platform implementations, and moved to the new common location. Two headers still need to be eliminated in order to include Tegra in a multi-platform kernel/ <mach/{clk,powergate}.h>. A new common API needs to be invented to replace parts of clk.h. powergate.h might be replaced by regulators; this needs more investigation. This pull request is based on tegra-for-3.8-dt, followed by a merge of arm-soc's devel/debug_ll_init branch. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJQppQBAAoJEMzrak5tbycxoz0P/REooomHVeI5CNyKMxp0rzQv dSGfnWD2nuRJ3k36VOdGpa+BYW/xjYuYdIAKNrfAEnfeQRbYp1VGIfyjgMEcx7Yi TzNmangYj+9f60u1MQq2YQytFFtgfcG1utTIuvKKhuJ/pZEjCkYKBQjNOLFuetaI oCxNDklcnCn5zxUGsQwpxxMf+A1Ja6tPHkqdN2p+0OQpUpr0i2mCMMrSPEHY0RgV zRBhsIwwe9eTAOPkZmr6SnCVIAs2rANVnBfZGJC/k9bT7cckhmL/EcGZLBIvRe8L gD4HtZsltNwbCh/cV4qIvx/nUaW1No/iqvQERtgAGWQtCUp/Jgmy3roV4zzWBiOR /N88kBaO5fw7crVFDMLTlHVKc2IKWTzSnpEUIllLw/G8ySjW5tjXP57gaxb712BU KYmcl6KFZ8Uu8OfyDYR6dRPtk+ayqAhSqBql+NveOWLk+nYFFyoob62FPTFq64eu MwM1BKlFKxLmMUeBTpSJXG/rtVkE+kgocZrB6GEofhIn7gjELqsaWutOJ6LYQ4wY i4N0NcBA3/oFu7N9T7yY+mKJCwRovyrpqW3Lp62xvns8+Y2ziUNxY4e0NvopzIOi GYz+ktI3CT1cZv9zkdEI+TOnRrWze8N7Xzt9ii8SD456to5wcaRCjmpATnNIKTTi uLmNaB6M9+mTjIXR8MDb =qXVf -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.8-single-zimage' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/multiplatform From Stephen Warren: ARM: tegra: single-zImage preparation work Various cleanups and enhancements are made to core Tegra code towards the aim of including Tegra in a multi-platform ARM kernel: RTC, timer, and TWD are configured via device tree. SPARSE_IRQ is enabled. Tegra's debug_ll options are simplified, and the macros brought into line with other multi-platform implementations, and moved to the new common location. Two headers still need to be eliminated in order to include Tegra in a multi-platform kernel/ <mach/{clk,powergate}.h>. A new common API needs to be invented to replace parts of clk.h. powergate.h might be replaced by regulators; this needs more investigation. This pull request is based on tegra-for-3.8-dt, followed by a merge of arm-soc's devel/debug_ll_init branch. * tag 'tegra-for-3.8-single-zimage' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (58 commits) ARM: tegra: move debug-macro.S to include/debug ARM: tegra: don't include iomap.h from debug-macro.S ARM: tegra: decouple uncompress.h and debug-macro.S ARM: tegra: simplify DEBUG_LL UART selection options ARM: tegra: select SPARSE_IRQ ARM: tegra: enhance timer.c to get IO address from device tree ARM: tegra: enhance timer.c to get IRQ info from device tree ARM: timer: fix checkpatch warnings ARM: tegra: add TWD to device tree ARM: tegra: define DT bindings for and instantiate RTC ARM: tegra: define DT bindings for and instantiate timer ARM: tegra: whistler: enable HDMI port ARM: tegra: tec: Enable HDMI output ARM: tegra: plutux: Enable HDMI output ARM: tegra: tamonten: Add host1x support ARM: tegra: trimslice: enable HDMI port ARM: tegra: harmony: enable HDMI port ARM: tegra: Add Tegra30 host1x support ARM: tegra: Add Tegra20 host1x support ARM: tegra: trimslice: enable SPI flash ...
This commit is contained in:
commit
46e8a79eb5
70 changed files with 1878 additions and 966 deletions
19
Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
Normal file
19
Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
Normal file
|
@ -0,0 +1,19 @@
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|||
NVIDIA Tegra20 real-time clock
|
||||
|
||||
The Tegra RTC maintains seconds and milliseconds counters, and five alarm
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||||
registers. The alarms and other interrupts may wake the system from low-power
|
||||
state.
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||||
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Required properties:
|
||||
|
||||
- compatible : should be "nvidia,tegra20-rtc".
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||||
- reg : Specifies base physical address and size of the registers.
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- interrupts : A single interrupt specifier.
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Example:
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timer {
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compatible = "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <0 2 0x04>;
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};
|
|
@ -0,0 +1,21 @@
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|||
NVIDIA Tegra20 timer
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The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
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running counter. The first two channels may also trigger a watchdog reset.
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Required properties:
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||||
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- compatible : should be "nvidia,tegra20-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 4 interrupts; one per timer channel.
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Example:
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timer {
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compatible = "nvidia,tegra20-timer";
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reg = <0x60005000 0x60>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04>;
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};
|
|
@ -0,0 +1,23 @@
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|||
NVIDIA Tegra30 timer
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The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
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running counter, and 5 watchdog modules. The first two channels may also
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trigger a legacy watchdog reset.
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Required properties:
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- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 6 interrupts; one per each of timer channels 1
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through 5, and one for the shared interrupt for the remaining channels.
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timer {
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04
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0 121 0x04
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0 122 0x04>;
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};
|
|
@ -51,4 +51,5 @@ ti Texas Instruments
|
|||
via VIA Technologies, Inc.
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||||
wlf Wolfson Microelectronics
|
||||
wm Wondermedia Technologies, Inc.
|
||||
winbond Winbond Electronics corp.
|
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xlnx Xilinx
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|
|
|
@ -644,6 +644,7 @@ config ARCH_TEGRA
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select HAVE_CLK
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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select SPARSE_IRQ
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select USE_OF
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help
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This enables support for NVIDIA Tegra based systems (Tegra APX,
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|
|
|
@ -345,6 +345,13 @@ choice
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Say Y here if you want kernel low-level debugging support
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on SOCFPGA based platforms.
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config DEBUG_TEGRA_UART
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depends on ARCH_TEGRA
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bool "Use Tegra UART for low-level debug"
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help
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Say Y here if you want kernel low-level debugging support
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on Tegra based platforms.
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config DEBUG_VEXPRESS_UART0_DETECT
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bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
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depends on ARCH_VEXPRESS && CPU_CP15_MMU
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|
@ -409,6 +416,36 @@ choice
|
|||
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endchoice
|
||||
|
||||
choice
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prompt "Low-level debug console UART"
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depends on DEBUG_LL && DEBUG_TEGRA_UART
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config TEGRA_DEBUG_UART_AUTO_ODMDATA
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bool "Via ODMDATA"
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help
|
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Automatically determines which UART to use for low-level debug based
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on the ODMDATA value. This value is part of the BCT, and is written
|
||||
to the boot memory device using nvflash, or other flashing tool.
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When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
|
||||
0/1/2/3/4 are UART A/B/C/D/E.
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||||
|
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config TEGRA_DEBUG_UARTA
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bool "UART A"
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config TEGRA_DEBUG_UARTB
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bool "UART B"
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|
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config TEGRA_DEBUG_UARTC
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bool "UART C"
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|
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config TEGRA_DEBUG_UARTD
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bool "UART D"
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config TEGRA_DEBUG_UARTE
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bool "UART E"
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||||
endchoice
|
||||
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||||
config DEBUG_LL_INCLUDE
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string
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default "debug/icedcc.S" if DEBUG_ICEDCC
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|
@ -418,6 +455,7 @@ config DEBUG_LL_INCLUDE
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|||
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
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default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
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DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
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default "debug/tegra.S" if DEBUG_TEGRA_UART
|
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default "mach/debug-macro.S"
|
||||
|
||||
config EARLY_PRINTK
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||||
|
|
|
@ -10,6 +10,18 @@ memory {
|
|||
reg = <0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
host1x {
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hdmi {
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||||
status = "okay";
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|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
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pll-supply = <&hdmi_pll_reg>;
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|
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nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
|
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};
|
||||
};
|
||||
|
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pinmux {
|
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
|
||||
|
@ -262,9 +274,9 @@ wm8903: wm8903@1a {
|
|||
};
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
hdmi_ddc: i2c@7000c400 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
|
@ -297,131 +309,98 @@ pmic: tps6586x@34 {
|
|||
vinldo9-supply = <&sm2_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sys_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "sys";
|
||||
sys_reg: sys {
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sm0";
|
||||
sm0 {
|
||||
regulator-name = "vdd_sm0,vdd_core";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sm1";
|
||||
sm1 {
|
||||
regulator-name = "vdd_sm1,vdd_cpu";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sm2";
|
||||
sm2_reg: sm2 {
|
||||
regulator-name = "vdd_sm2,vin_ldo*";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "ldo0";
|
||||
ldo0 {
|
||||
regulator-name = "vdd_ldo0,vddio_pex_clk";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo1";
|
||||
ldo1 {
|
||||
regulator-name = "vdd_ldo1,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo2";
|
||||
ldo2 {
|
||||
regulator-name = "vdd_ldo2,vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo3";
|
||||
ldo3 {
|
||||
regulator-name = "vdd_ldo3,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo4";
|
||||
ldo4 {
|
||||
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo5";
|
||||
ldo5 {
|
||||
regulator-name = "vdd_ldo5,vcore_mmc";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
ldo6 {
|
||||
regulator-name = "vdd_ldo6,avdd_vdac";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo7";
|
||||
hdmi_vdd_reg: ldo7 {
|
||||
regulator-name = "vdd_ldo7,avdd_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo8";
|
||||
hdmi_pll_reg: ldo8 {
|
||||
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo9";
|
||||
ldo9 {
|
||||
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo_rtc";
|
||||
ldo_rtc {
|
||||
regulator-name = "vdd_rtc_out,vdd_cell";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
@ -429,6 +408,11 @@ regulator@14 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
temperature-sensor@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
|
|
|
@ -291,37 +291,26 @@ pmic: tps6586x@34 {
|
|||
vinldo9-supply = <&sm2_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sys_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "sys";
|
||||
sys_reg: sys {
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sm0";
|
||||
sm0 {
|
||||
regulator-name = "+1.2vs_sm0,vdd_core";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sm1";
|
||||
sm1 {
|
||||
regulator-name = "+1.0vs_sm1,vdd_cpu";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sm2";
|
||||
sm2_reg: sm2 {
|
||||
regulator-name = "+3.7vs_sm2,vin_ldo*";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
|
@ -330,53 +319,41 @@ sm2_reg: regulator@3 {
|
|||
|
||||
/* LDO0 is not connected to anything */
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo1";
|
||||
ldo1 {
|
||||
regulator-name = "+1.1vs_ldo1,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo2";
|
||||
ldo2 {
|
||||
regulator-name = "+1.2vs_ldo2,vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo3";
|
||||
ldo3 {
|
||||
regulator-name = "+3.3vs_ldo3,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo4";
|
||||
ldo4 {
|
||||
regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo5";
|
||||
ldo5 {
|
||||
regulator-name = "+2.85vs_ldo5,vcore_mmc";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
ldo6 {
|
||||
/*
|
||||
* Research indicates this should be
|
||||
* 1.8v; other boards that use this
|
||||
|
@ -390,34 +367,26 @@ regulator@10 {
|
|||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo7";
|
||||
ldo7 {
|
||||
regulator-name = "+3.3vs_ldo7,avdd_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo8";
|
||||
ldo8 {
|
||||
regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo9";
|
||||
ldo9 {
|
||||
regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo_rtc";
|
||||
ldo_rtc {
|
||||
regulator-name = "+3.3vs_rtc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
|
|
@ -6,6 +6,12 @@ / {
|
|||
model = "Avionic Design Plutux board";
|
||||
compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
wm8903: wm8903@1a {
|
||||
compatible = "wlf,wm8903";
|
||||
|
|
|
@ -395,37 +395,26 @@ pmic: tps6586x@34 {
|
|||
vinldo9-supply = <&sm2_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sys_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "sys";
|
||||
sys_reg: sys {
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sm0";
|
||||
sm0 {
|
||||
regulator-name = "vdd_sm0,vdd_core";
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sm1";
|
||||
sm1 {
|
||||
regulator-name = "vdd_sm1,vdd_cpu";
|
||||
regulator-min-microvolt = <1125000>;
|
||||
regulator-max-microvolt = <1125000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sm2";
|
||||
sm2_reg: sm2 {
|
||||
regulator-name = "vdd_sm2,vin_ldo*";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
|
@ -434,86 +423,66 @@ sm2_reg: regulator@3 {
|
|||
|
||||
/* LDO0 is not connected to anything */
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo1";
|
||||
ldo1 {
|
||||
regulator-name = "vdd_ldo1,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo2";
|
||||
ldo2 {
|
||||
regulator-name = "vdd_ldo2,vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo3";
|
||||
ldo3 {
|
||||
regulator-name = "vdd_ldo3,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo4";
|
||||
ldo4 {
|
||||
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo5";
|
||||
ldo5 {
|
||||
regulator-name = "vdd_ldo5,vcore_mmc";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
ldo6 {
|
||||
regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo7";
|
||||
ldo7 {
|
||||
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo8";
|
||||
ldo8 {
|
||||
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo9";
|
||||
ldo9 {
|
||||
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo_rtc";
|
||||
ldo_rtc {
|
||||
regulator-name = "vdd_rtc_out,vdd_cell";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
@ -592,6 +561,12 @@ usb@c5008000 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@c8000000 {
|
||||
status = "okay";
|
||||
power-gpios = <&gpio 86 0>; /* gpio PK6 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sdhci@c8000400 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
|
|
|
@ -8,6 +8,16 @@ memory {
|
|||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
pll-supply = <&hdmi_pll_reg>;
|
||||
|
||||
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
||||
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
|
||||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
@ -62,10 +72,6 @@ dap4 {
|
|||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtd";
|
||||
nvidia,function = "sdio2";
|
||||
|
@ -91,7 +97,7 @@ gpv {
|
|||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "pta";
|
||||
nvidia,pins = "hdint";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
|
@ -230,6 +236,39 @@ conf_ld17_0 {
|
|||
nvidia,pull = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
state_i2cmux_ddc: pinmux_i2cmux_ddc {
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
pta {
|
||||
nvidia,pins = "pta";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
};
|
||||
|
||||
state_i2cmux_pta: pinmux_i2cmux_pta {
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
pta {
|
||||
nvidia,pins = "pta";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
};
|
||||
|
||||
state_i2cmux_idle: pinmux_i2cmux_idle {
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
pta {
|
||||
nvidia,pins = "pta";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2s@70002800 {
|
||||
|
@ -246,6 +285,36 @@ i2c@7000c000 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2cmux {
|
||||
compatible = "i2c-mux-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c-parent = <&{/i2c@7000c400}>;
|
||||
|
||||
pinctrl-names = "ddc", "pta", "idle";
|
||||
pinctrl-0 = <&state_i2cmux_ddc>;
|
||||
pinctrl-1 = <&state_i2cmux_pta>;
|
||||
pinctrl-2 = <&state_i2cmux_idle>;
|
||||
|
||||
hdmi_ddc: i2c@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
@ -271,97 +340,72 @@ pmic: tps6586x@34 {
|
|||
vinldo9-supply = <&sm2_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sys_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "sys";
|
||||
sys_reg: sys {
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sm0";
|
||||
sm0 {
|
||||
regulator-name = "vdd_sys_sm0,vdd_core";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sm1";
|
||||
sm1 {
|
||||
regulator-name = "vdd_sys_sm1,vdd_cpu";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sm2";
|
||||
sm2_reg: sm2 {
|
||||
regulator-name = "vdd_sys_sm2,vin_ldo*";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "ldo0";
|
||||
ldo0 {
|
||||
regulator-name = "vdd_ldo0,vddio_pex_clk";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo1";
|
||||
ldo1 {
|
||||
regulator-name = "vdd_ldo1,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo2";
|
||||
ldo2 {
|
||||
regulator-name = "vdd_ldo2,vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo3";
|
||||
ldo3 {
|
||||
regulator-name = "vdd_ldo3,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo4";
|
||||
ldo4 {
|
||||
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo5";
|
||||
ldo5 {
|
||||
regulator-name = "vdd_ldo5,vcore_mmc";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
ldo6 {
|
||||
regulator-name = "vdd_ldo6,avdd_vdac";
|
||||
/*
|
||||
* According to the Tegra 2 Automotive
|
||||
|
@ -373,25 +417,19 @@ regulator@10 {
|
|||
regulator-max-microvolt = <2850000>;
|
||||
};
|
||||
|
||||
regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo7";
|
||||
hdmi_vdd_reg: ldo7 {
|
||||
regulator-name = "vdd_ldo7,avdd_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo8";
|
||||
hdmi_pll_reg: ldo8 {
|
||||
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo9";
|
||||
ldo9 {
|
||||
regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
|
||||
/*
|
||||
* According to the Tegra 2 Automotive
|
||||
|
@ -404,9 +442,7 @@ regulator@13 {
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo_rtc";
|
||||
ldo_rtc {
|
||||
regulator-name = "vdd_rtc_out";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
@ -414,6 +450,11 @@ regulator@14 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
temperature-sensor@4c {
|
||||
compatible = "onnn,nct1008";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
|
|
|
@ -6,10 +6,13 @@ / {
|
|||
model = "Avionic Design Tamonten Evaluation Carrier";
|
||||
compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
host1x {
|
||||
hdmi {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
wm8903: wm8903@1a {
|
||||
compatible = "wlf,wm8903";
|
||||
reg = <0x1a>;
|
||||
|
|
|
@ -10,6 +10,18 @@ memory {
|
|||
reg = <0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
pll-supply = <&hdmi_pll_reg>;
|
||||
|
||||
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
||||
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
|
||||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
@ -249,14 +261,24 @@ serial@70006000 {
|
|||
clock-frequency = <216000000>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
dvi_ddc: i2c@7000c000 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
spi@7000c380 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
spi-max-frequency = <48000000>;
|
||||
spi-flash@0 {
|
||||
compatible = "winbond,w25q80bl";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <48000000>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_ddc: i2c@7000c400 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
|
@ -300,6 +322,30 @@ sdhci@c8000600 {
|
|||
bus-width = <4>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hdmi_vdd_reg: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "avdd_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
hdmi_pll_reg: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-trimslice";
|
||||
nvidia,i2s-controller = <&tegra_i2s1>;
|
||||
|
|
|
@ -64,11 +64,6 @@ dap4 {
|
|||
nvidia,pins = "dap4";
|
||||
nvidia,function = "dap4";
|
||||
};
|
||||
ddc {
|
||||
nvidia,pins = "ddc", "owc", "spdi", "spdo",
|
||||
"uac";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
|
||||
nvidia,function = "vi";
|
||||
|
@ -98,7 +93,7 @@ gpv {
|
|||
nvidia,function = "pcie";
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint", "pta";
|
||||
nvidia,pins = "hdint";
|
||||
nvidia,function = "hdmi";
|
||||
};
|
||||
i2cp {
|
||||
|
@ -129,6 +124,10 @@ ld0 {
|
|||
"lspi", "lvp1", "lvs";
|
||||
nvidia,function = "displaya";
|
||||
};
|
||||
owc {
|
||||
nvidia,pins = "owc", "spdi", "spdo", "uac";
|
||||
nvidia,function = "rsvd2";
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
|
@ -237,6 +236,49 @@ conf_ld17_0 {
|
|||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
};
|
||||
drive_sdio1 {
|
||||
nvidia,pins = "drive_sdio1";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <1>;
|
||||
nvidia,low-power-mode = <3>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <3>;
|
||||
nvidia,slew-rate-falling = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
state_i2cmux_ddc: pinmux_i2cmux_ddc {
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
pta {
|
||||
nvidia,pins = "pta";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
};
|
||||
|
||||
state_i2cmux_pta: pinmux_i2cmux_pta {
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
pta {
|
||||
nvidia,pins = "pta";
|
||||
nvidia,function = "i2c2";
|
||||
};
|
||||
};
|
||||
|
||||
state_i2cmux_idle: pinmux_i2cmux_idle {
|
||||
ddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
pta {
|
||||
nvidia,pins = "pta";
|
||||
nvidia,function = "rsvd4";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -281,6 +323,31 @@ i2c@7000c400 {
|
|||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2cmux {
|
||||
compatible = "i2c-mux-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c-parent = <&{/i2c@7000c400}>;
|
||||
|
||||
pinctrl-names = "ddc", "pta", "idle";
|
||||
pinctrl-0 = <&state_i2cmux_ddc>;
|
||||
pinctrl-1 = <&state_i2cmux_pta>;
|
||||
pinctrl-2 = <&state_i2cmux_idle>;
|
||||
|
||||
i2c@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
@ -311,37 +378,26 @@ pmic: tps6586x@34 {
|
|||
vinldo9-supply = <&sm2_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sys_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "sys";
|
||||
sys_reg: sys {
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sm0";
|
||||
sm0 {
|
||||
regulator-name = "vdd_sm0,vdd_core";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sm1";
|
||||
sm1 {
|
||||
regulator-name = "vdd_sm1,vdd_cpu";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sm2";
|
||||
sm2_reg: sm2 {
|
||||
regulator-name = "vdd_sm2,vin_ldo*";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
|
@ -350,86 +406,66 @@ sm2_reg: regulator@3 {
|
|||
|
||||
/* LDO0 is not connected to anything */
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo1";
|
||||
ldo1 {
|
||||
regulator-name = "vdd_ldo1,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo2";
|
||||
ldo2 {
|
||||
regulator-name = "vdd_ldo2,vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo3";
|
||||
ldo3 {
|
||||
regulator-name = "vdd_ldo3,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo4";
|
||||
ldo4 {
|
||||
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo5";
|
||||
ldo5 {
|
||||
regulator-name = "vdd_ldo5,vcore_mmc";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
ldo6 {
|
||||
regulator-name = "vdd_ldo6,avdd_vdac";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo7";
|
||||
ldo7 {
|
||||
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo8";
|
||||
ldo8 {
|
||||
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo9";
|
||||
ldo9 {
|
||||
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo_rtc";
|
||||
ldo_rtc {
|
||||
regulator-name = "vdd_rtc_out,vdd_cell";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
@ -437,6 +473,11 @@ regulator@14 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
temperature-sensor@4c {
|
||||
compatible = "onnn,nct1008";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
|
@ -456,6 +497,12 @@ usb@c5008000 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@c8000000 {
|
||||
status = "okay";
|
||||
power-gpios = <&gpio 86 0>; /* gpio PK6 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sdhci@c8000400 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
|
|
|
@ -10,6 +10,18 @@ memory {
|
|||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
pll-supply = <&hdmi_pll_reg>;
|
||||
|
||||
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
||||
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
|
||||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
@ -246,6 +258,11 @@ serial@70006000 {
|
|||
clock-frequency = <216000000>;
|
||||
};
|
||||
|
||||
hdmi_ddc: i2c@7000c400 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
@ -295,243 +312,182 @@ max8907@3c {
|
|||
in20-supply = <&mbatt_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mbatt_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "mbatt";
|
||||
mbatt_reg: mbatt {
|
||||
regulator-name = "vbat_pmu";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sd1";
|
||||
sd1 {
|
||||
regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sd2";
|
||||
sd2 {
|
||||
regulator-name = "nvvdd_sv2,vdd_core";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
nvvdd_sv3_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sd3";
|
||||
nvvdd_sv3_reg: sd3 {
|
||||
regulator-name = "nvvdd_sv3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "ldo1";
|
||||
ldo1 {
|
||||
regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo2";
|
||||
ldo2 {
|
||||
regulator-name = "nvvdd_ldo2,avdd_pll*";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo3";
|
||||
ldo3 {
|
||||
regulator-name = "nvvdd_ldo3,vcom_1v8b";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo4";
|
||||
ldo4 {
|
||||
regulator-name = "nvvdd_ldo4,avdd_usb*";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo5";
|
||||
ldo5 {
|
||||
regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo6";
|
||||
hdmi_pll_reg: ldo6 {
|
||||
regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo7";
|
||||
ldo7 {
|
||||
regulator-name = "nvvdd_ldo7,avddio_audio";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo8";
|
||||
ldo8 {
|
||||
regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo9";
|
||||
ldo9 {
|
||||
regulator-name = "nvvdd_ldo9,avdd_cam*";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo10";
|
||||
ldo10 {
|
||||
regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@14 {
|
||||
reg = <14>;
|
||||
regulator-compatible = "ldo11";
|
||||
hdmi_vdd_reg: ldo11 {
|
||||
regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@15 {
|
||||
reg = <15>;
|
||||
regulator-compatible = "ldo12";
|
||||
ldo12 {
|
||||
regulator-name = "nvvdd_ldo12,vddio_sdio";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@16 {
|
||||
reg = <16>;
|
||||
regulator-compatible = "ldo13";
|
||||
ldo13 {
|
||||
regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
regulator@17 {
|
||||
reg = <17>;
|
||||
regulator-compatible = "ldo14";
|
||||
ldo14 {
|
||||
regulator-name = "nvvdd_ldo14,avdd_vdac";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
regulator@18 {
|
||||
reg = <18>;
|
||||
regulator-compatible = "ldo15";
|
||||
ldo15 {
|
||||
regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
regulator@19 {
|
||||
reg = <19>;
|
||||
regulator-compatible = "ldo16";
|
||||
ldo16 {
|
||||
regulator-name = "nvvdd_ldo16,vdd_dbrtr";
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
|
||||
regulator@20 {
|
||||
reg = <20>;
|
||||
regulator-compatible = "ldo17";
|
||||
ldo17 {
|
||||
regulator-name = "nvvdd_ldo17,vddio_mipi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
regulator@21 {
|
||||
reg = <21>;
|
||||
regulator-compatible = "ldo18";
|
||||
ldo18 {
|
||||
regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
regulator@22 {
|
||||
reg = <22>;
|
||||
regulator-compatible = "ldo19";
|
||||
ldo19 {
|
||||
regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
regulator@23 {
|
||||
reg = <23>;
|
||||
regulator-compatible = "ldo20";
|
||||
ldo20 {
|
||||
regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@24 {
|
||||
reg = <24>;
|
||||
regulator-compatible = "out5v";
|
||||
out5v {
|
||||
regulator-name = "usb0_vbus_reg";
|
||||
};
|
||||
|
||||
regulator@25 {
|
||||
reg = <25>;
|
||||
regulator-compatible = "out33v";
|
||||
out33v {
|
||||
regulator-name = "pmu_out3v3";
|
||||
};
|
||||
|
||||
regulator@26 {
|
||||
reg = <26>;
|
||||
regulator-compatible = "bbat";
|
||||
bbat {
|
||||
regulator-name = "pmu_bbat";
|
||||
regulator-min-microvolt = <2400000>;
|
||||
regulator-max-microvolt = <2400000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@27 {
|
||||
reg = <27>;
|
||||
regulator-compatible = "sdby";
|
||||
sdby {
|
||||
regulator-name = "vdd_aon";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@28 {
|
||||
reg = <28>;
|
||||
regulator-compatible = "vrtc";
|
||||
vrtc {
|
||||
regulator-name = "vrtc,pmu_vccadc";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
|
@ -4,6 +4,108 @@ / {
|
|||
compatible = "nvidia,tegra20";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
host1x {
|
||||
compatible = "nvidia,tegra20-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00024000>;
|
||||
interrupts = <0 65 0x04 /* mpcore syncpt */
|
||||
0 67 0x04>; /* mpcore general */
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0x54000000 0x54000000 0x04000000>;
|
||||
|
||||
mpe {
|
||||
compatible = "nvidia,tegra20-mpe";
|
||||
reg = <0x54040000 0x00040000>;
|
||||
interrupts = <0 68 0x04>;
|
||||
};
|
||||
|
||||
vi {
|
||||
compatible = "nvidia,tegra20-vi";
|
||||
reg = <0x54080000 0x00040000>;
|
||||
interrupts = <0 69 0x04>;
|
||||
};
|
||||
|
||||
epp {
|
||||
compatible = "nvidia,tegra20-epp";
|
||||
reg = <0x540c0000 0x00040000>;
|
||||
interrupts = <0 70 0x04>;
|
||||
};
|
||||
|
||||
isp {
|
||||
compatible = "nvidia,tegra20-isp";
|
||||
reg = <0x54100000 0x00040000>;
|
||||
interrupts = <0 71 0x04>;
|
||||
};
|
||||
|
||||
gr2d {
|
||||
compatible = "nvidia,tegra20-gr2d";
|
||||
reg = <0x54140000 0x00040000>;
|
||||
interrupts = <0 72 0x04>;
|
||||
};
|
||||
|
||||
gr3d {
|
||||
compatible = "nvidia,tegra20-gr3d";
|
||||
reg = <0x54180000 0x00040000>;
|
||||
};
|
||||
|
||||
dc@54200000 {
|
||||
compatible = "nvidia,tegra20-dc";
|
||||
reg = <0x54200000 0x00040000>;
|
||||
interrupts = <0 73 0x04>;
|
||||
|
||||
rgb {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dc@54240000 {
|
||||
compatible = "nvidia,tegra20-dc";
|
||||
reg = <0x54240000 0x00040000>;
|
||||
interrupts = <0 74 0x04>;
|
||||
|
||||
rgb {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
hdmi {
|
||||
compatible = "nvidia,tegra20-hdmi";
|
||||
reg = <0x54280000 0x00040000>;
|
||||
interrupts = <0 75 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tvo {
|
||||
compatible = "nvidia,tegra20-tvo";
|
||||
reg = <0x542c0000 0x00040000>;
|
||||
interrupts = <0 76 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi {
|
||||
compatible = "nvidia,tegra20-dsi";
|
||||
reg = <0x54300000 0x00040000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer@50004600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x50040600 0x20>;
|
||||
interrupts = <1 13 0x304>;
|
||||
};
|
||||
|
||||
cache-controller@50043000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x50043000 0x1000>;
|
||||
arm,data-latency = <5 5 2>;
|
||||
arm,tag-latency = <4 4 2>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0x50041000 0x1000
|
||||
|
@ -12,6 +114,15 @@ intc: interrupt-controller {
|
|||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
timer@60005000 {
|
||||
compatible = "nvidia,tegra20-timer";
|
||||
reg = <0x60005000 0x60>;
|
||||
interrupts = <0 0 0x04
|
||||
0 1 0x04
|
||||
0 41 0x04
|
||||
0 42 0x04>;
|
||||
};
|
||||
|
||||
apbdma: dma {
|
||||
compatible = "nvidia,tegra20-apbdma";
|
||||
reg = <0x6000a000 0x1200>;
|
||||
|
@ -129,6 +240,12 @@ pwm: pwm {
|
|||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
compatible = "nvidia,tegra20-i2c";
|
||||
reg = <0x7000c000 0x100>;
|
||||
|
@ -138,6 +255,16 @@ i2c@7000c000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000c380 {
|
||||
compatible = "nvidia,tegra20-sflash";
|
||||
reg = <0x7000c380 0x80>;
|
||||
interrupts = <0 39 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 11>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
compatible = "nvidia,tegra20-i2c";
|
||||
reg = <0x7000c400 0x100>;
|
||||
|
@ -165,6 +292,46 @@ i2c@7000d000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d400 {
|
||||
compatible = "nvidia,tegra20-slink";
|
||||
reg = <0x7000d400 0x200>;
|
||||
interrupts = <0 59 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 15>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d600 {
|
||||
compatible = "nvidia,tegra20-slink";
|
||||
reg = <0x7000d600 0x200>;
|
||||
interrupts = <0 82 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d800 {
|
||||
compatible = "nvidia,tegra20-slink";
|
||||
reg = <0x7000d480 0x200>;
|
||||
interrupts = <0 83 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 17>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000da00 {
|
||||
compatible = "nvidia,tegra20-slink";
|
||||
reg = <0x7000da00 0x200>;
|
||||
interrupts = <0 93 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 18>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmc {
|
||||
compatible = "nvidia,tegra20-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
|
|
|
@ -83,5 +83,11 @@ vdd_bl_reg: regulator@105 {
|
|||
gpio = <&gpio 83 0>; /* GPIO PK3 */
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000400 {
|
||||
status = "okay";
|
||||
power-gpios = <&gpio 28 0>; /* gpio PD4 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -95,4 +95,10 @@ vdd_bl2_reg: regulator@106 {
|
|||
gpio = <&gpio 232 0>; /* GPIO PDD0 */
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000400 {
|
||||
status = "okay";
|
||||
power-gpios = <&gpio 27 0>; /* gpio PD3 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -52,6 +52,22 @@ sdmmc1_cmd_pz1 {
|
|||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc3_clk_pa6 {
|
||||
nvidia,pins = "sdmmc3_clk_pa6";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc3_cmd_pa7 {
|
||||
nvidia,pins = "sdmmc3_cmd_pa7",
|
||||
"sdmmc3_dat0_pb7",
|
||||
"sdmmc3_dat1_pb6",
|
||||
"sdmmc3_dat2_pb5",
|
||||
"sdmmc3_dat3_pb4";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
|
@ -81,6 +97,15 @@ dap2_fs_pa2 {
|
|||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdio3 {
|
||||
nvidia,pins = "drive_sdio3";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <0>;
|
||||
nvidia,pull-down-strength = <46>;
|
||||
nvidia,pull-up-strength = <42>;
|
||||
nvidia,slew-rate-rising = <1>;
|
||||
nvidia,slew-rate-falling = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -171,56 +196,41 @@ pmic: tps65911@2d {
|
|||
vccio-supply = <&vdd_ac_bat_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd1_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "vdd1";
|
||||
vdd1_reg: vdd1 {
|
||||
regulator-name = "vddio_ddr_1v2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "vdd2";
|
||||
vdd2_reg: vdd2 {
|
||||
regulator-name = "vdd_1v5_gen";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddctrl_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "vddctrl";
|
||||
vddctrl_reg: vddctrl {
|
||||
regulator-name = "vdd_cpu,vdd_sys";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "vio";
|
||||
vio_reg: vio {
|
||||
regulator-name = "vdd_1v8_gen";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "ldo1";
|
||||
ldo1_reg: ldo1 {
|
||||
regulator-name = "vdd_pexa,vdd_pexb";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo2";
|
||||
ldo2_reg: ldo2 {
|
||||
regulator-name = "vdd_sata,avdd_plle";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
|
@ -228,44 +238,34 @@ ldo2_reg: regulator@5 {
|
|||
|
||||
/* LDO3 is not connected to anything */
|
||||
|
||||
ldo4_reg: regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo4";
|
||||
ldo4_reg: ldo4 {
|
||||
regulator-name = "vdd_rtc";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo5";
|
||||
ldo5_reg: ldo5 {
|
||||
regulator-name = "vddio_sdmmc,avdd_vdac";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo6";
|
||||
ldo6_reg: ldo6 {
|
||||
regulator-name = "avdd_dsi_csi,pwrdet_mipi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
ldo7_reg: regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo7";
|
||||
ldo7_reg: ldo7 {
|
||||
regulator-name = "vdd_pllm,x,u,a_p_c_s";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo8";
|
||||
ldo8_reg: ldo8 {
|
||||
regulator-name = "vdd_ddr_hs";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
|
@ -275,6 +275,16 @@ ldo8_reg: regulator@11 {
|
|||
};
|
||||
};
|
||||
|
||||
spi@7000da00 {
|
||||
status = "okay";
|
||||
spi-max-frequency = <25000000>;
|
||||
spi-flash@1 {
|
||||
compatible = "winbond,w25q32";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahub {
|
||||
i2s@70080400 {
|
||||
status = "okay";
|
||||
|
@ -409,6 +419,8 @@ vdd_com_reg: regulator@9 {
|
|||
regulator-name = "vdd_com";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio 24 0>; /* gpio PD0 */
|
||||
vin-supply = <&sys_3v3_reg>;
|
||||
|
|
|
@ -4,6 +4,108 @@ / {
|
|||
compatible = "nvidia,tegra30";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
host1x {
|
||||
compatible = "nvidia,tegra30-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00024000>;
|
||||
interrupts = <0 65 0x04 /* mpcore syncpt */
|
||||
0 67 0x04>; /* mpcore general */
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0x54000000 0x54000000 0x04000000>;
|
||||
|
||||
mpe {
|
||||
compatible = "nvidia,tegra30-mpe";
|
||||
reg = <0x54040000 0x00040000>;
|
||||
interrupts = <0 68 0x04>;
|
||||
};
|
||||
|
||||
vi {
|
||||
compatible = "nvidia,tegra30-vi";
|
||||
reg = <0x54080000 0x00040000>;
|
||||
interrupts = <0 69 0x04>;
|
||||
};
|
||||
|
||||
epp {
|
||||
compatible = "nvidia,tegra30-epp";
|
||||
reg = <0x540c0000 0x00040000>;
|
||||
interrupts = <0 70 0x04>;
|
||||
};
|
||||
|
||||
isp {
|
||||
compatible = "nvidia,tegra30-isp";
|
||||
reg = <0x54100000 0x00040000>;
|
||||
interrupts = <0 71 0x04>;
|
||||
};
|
||||
|
||||
gr2d {
|
||||
compatible = "nvidia,tegra30-gr2d";
|
||||
reg = <0x54140000 0x00040000>;
|
||||
interrupts = <0 72 0x04>;
|
||||
};
|
||||
|
||||
gr3d {
|
||||
compatible = "nvidia,tegra30-gr3d";
|
||||
reg = <0x54180000 0x00040000>;
|
||||
};
|
||||
|
||||
dc@54200000 {
|
||||
compatible = "nvidia,tegra30-dc";
|
||||
reg = <0x54200000 0x00040000>;
|
||||
interrupts = <0 73 0x04>;
|
||||
|
||||
rgb {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dc@54240000 {
|
||||
compatible = "nvidia,tegra30-dc";
|
||||
reg = <0x54240000 0x00040000>;
|
||||
interrupts = <0 74 0x04>;
|
||||
|
||||
rgb {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
hdmi {
|
||||
compatible = "nvidia,tegra30-hdmi";
|
||||
reg = <0x54280000 0x00040000>;
|
||||
interrupts = <0 75 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tvo {
|
||||
compatible = "nvidia,tegra30-tvo";
|
||||
reg = <0x542c0000 0x00040000>;
|
||||
interrupts = <0 76 0x04>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi {
|
||||
compatible = "nvidia,tegra30-dsi";
|
||||
reg = <0x54300000 0x00040000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer@50004600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x50040600 0x20>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
};
|
||||
|
||||
cache-controller@50043000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x50043000 0x1000>;
|
||||
arm,data-latency = <6 6 2>;
|
||||
arm,tag-latency = <5 5 2>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0x50041000 0x1000
|
||||
|
@ -12,6 +114,17 @@ intc: interrupt-controller {
|
|||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
timer@60005000 {
|
||||
compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
|
||||
reg = <0x60005000 0x400>;
|
||||
interrupts = <0 0 0x04
|
||||
0 1 0x04
|
||||
0 41 0x04
|
||||
0 42 0x04
|
||||
0 121 0x04
|
||||
0 122 0x04>;
|
||||
};
|
||||
|
||||
apbdma: dma {
|
||||
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
|
||||
reg = <0x6000a000 0x1400>;
|
||||
|
@ -123,6 +236,12 @@ pwm: pwm {
|
|||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
||||
reg = <0x7000c000 0x100>;
|
||||
|
@ -168,6 +287,66 @@ i2c@7000d000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d400 {
|
||||
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
||||
reg = <0x7000d400 0x200>;
|
||||
interrupts = <0 59 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 15>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d600 {
|
||||
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
||||
reg = <0x7000d600 0x200>;
|
||||
interrupts = <0 82 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d800 {
|
||||
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
||||
reg = <0x7000d480 0x200>;
|
||||
interrupts = <0 83 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 17>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000da00 {
|
||||
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
||||
reg = <0x7000da00 0x200>;
|
||||
interrupts = <0 93 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 18>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000dc00 {
|
||||
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
||||
reg = <0x7000dc00 0x200>;
|
||||
interrupts = <0 94 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 27>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000de00 {
|
||||
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
||||
reg = <0x7000de00 0x200>;
|
||||
interrupts = <0 79 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 28>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmc {
|
||||
compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
|
|
223
arch/arm/include/debug/tegra.S
Normal file
223
arch/arm/include/debug/tegra.S
Normal file
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* Copyright (C) 2010,2011 Google, Inc.
|
||||
* Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
|
||||
*
|
||||
* Author:
|
||||
* Colin Cross <ccross@google.com>
|
||||
* Erik Gilling <konkers@google.com>
|
||||
* Doug Anderson <dianders@chromium.org>
|
||||
* Stephen Warren <swarren@nvidia.com>
|
||||
*
|
||||
* Portions based on mach-omap2's debug-macro.S
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/serial_reg.h>
|
||||
|
||||
#define UART_SHIFT 2
|
||||
|
||||
/* Physical addresses */
|
||||
#define TEGRA_CLK_RESET_BASE 0x60006000
|
||||
#define TEGRA_APB_MISC_BASE 0x70000000
|
||||
#define TEGRA_UARTA_BASE 0x70006000
|
||||
#define TEGRA_UARTB_BASE 0x70006040
|
||||
#define TEGRA_UARTC_BASE 0x70006200
|
||||
#define TEGRA_UARTD_BASE 0x70006300
|
||||
#define TEGRA_UARTE_BASE 0x70006400
|
||||
#define TEGRA_PMC_BASE 0x7000e400
|
||||
|
||||
#define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
|
||||
#define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
|
||||
#define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
|
||||
#define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
|
||||
#define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
|
||||
#define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
|
||||
#define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
|
||||
#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
|
||||
|
||||
/*
|
||||
* Must be 1MB-aligned since a 1MB mapping is used early on.
|
||||
* Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
|
||||
*/
|
||||
#define UART_VIRTUAL_BASE 0xfe100000
|
||||
|
||||
#define checkuart(rp, rv, lhu, bit, uart) \
|
||||
/* Load address of CLK_RST register */ \
|
||||
movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
|
||||
movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
|
||||
/* Load value from CLK_RST register */ \
|
||||
ldr rp, [rp, #0] ; \
|
||||
/* Test UART's reset bit */ \
|
||||
tst rp, #(1 << bit) ; \
|
||||
/* If set, can't use UART; jump to save no UART */ \
|
||||
bne 90f ; \
|
||||
/* Load address of CLK_OUT_ENB register */ \
|
||||
movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
|
||||
movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
|
||||
/* Load value from CLK_OUT_ENB register */ \
|
||||
ldr rp, [rp, #0] ; \
|
||||
/* Test UART's clock enable bit */ \
|
||||
tst rp, #(1 << bit) ; \
|
||||
/* If clear, can't use UART; jump to save no UART */ \
|
||||
beq 90f ; \
|
||||
/* Passed all tests, load address of UART registers */ \
|
||||
movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
|
||||
movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \
|
||||
/* Jump to save UART address */ \
|
||||
b 91f
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
adr \rp, 99f @ actual addr of 99f
|
||||
ldr \rv, [\rp] @ linked addr is stored there
|
||||
sub \rv, \rv, \rp @ offset between the two
|
||||
ldr \rp, [\rp, #4] @ linked tegra_uart_config
|
||||
sub \tmp, \rp, \rv @ actual tegra_uart_config
|
||||
ldr \rp, [\tmp] @ Load tegra_uart_config
|
||||
cmp \rp, #1 @ needs initialization?
|
||||
bne 100f @ no; go load the addresses
|
||||
mov \rv, #0 @ yes; record init is done
|
||||
str \rv, [\tmp]
|
||||
|
||||
#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
|
||||
/* Check ODMDATA */
|
||||
10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
|
||||
movt \rp, #TEGRA_PMC_SCRATCH20 >> 16
|
||||
ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
|
||||
ubfx \rv, \rp, #18, #2 @ 19:18 are console type
|
||||
cmp \rv, #2 @ 2 and 3 mean DCC, UART
|
||||
beq 11f @ some boards swap the meaning
|
||||
cmp \rv, #3 @ so accept either
|
||||
bne 90f
|
||||
11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID
|
||||
cmp \rv, #0 @ UART 0?
|
||||
beq 20f
|
||||
cmp \rv, #1 @ UART 1?
|
||||
beq 21f
|
||||
cmp \rv, #2 @ UART 2?
|
||||
beq 22f
|
||||
cmp \rv, #3 @ UART 3?
|
||||
beq 23f
|
||||
cmp \rv, #4 @ UART 4?
|
||||
beq 24f
|
||||
b 90f @ invalid
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
|
||||
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
/* Check UART A validity */
|
||||
20: checkuart(\rp, \rv, L, 6, A)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
|
||||
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
/* Check UART B validity */
|
||||
21: checkuart(\rp, \rv, L, 7, B)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
|
||||
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
/* Check UART C validity */
|
||||
22: checkuart(\rp, \rv, H, 23, C)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
|
||||
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
/* Check UART D validity */
|
||||
23: checkuart(\rp, \rv, U, 1, D)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
|
||||
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
/* Check UART E validity */
|
||||
24:
|
||||
checkuart(\rp, \rv, U, 2, E)
|
||||
#endif
|
||||
|
||||
/* No valid UART found */
|
||||
90: mov \rp, #0
|
||||
/* fall through */
|
||||
|
||||
/* Record whichever UART we chose */
|
||||
91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
|
||||
cmp \rp, #0 @ Valid UART address?
|
||||
bne 92f @ Yes, go process it
|
||||
str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt
|
||||
b 100f @ Done
|
||||
92: and \rv, \rp, #0xffffff @ offset within 1MB section
|
||||
add \rv, \rv, #UART_VIRTUAL_BASE
|
||||
str \rv, [\tmp, #8] @ Store in tegra_uart_virt
|
||||
movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
|
||||
movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
|
||||
ldr \rv, [\rv, #0] @ Load HIDREV
|
||||
ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
|
||||
cmp \rv, #0x20 @ Tegra20?
|
||||
moveq \rv, #0x75 @ Tegra20 divisor
|
||||
movne \rv, #0xdd @ Tegra30 divisor
|
||||
str \rv, [\tmp, #12] @ Save divisor to scratch
|
||||
/* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
|
||||
mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
|
||||
str \rv, [\rp, #UART_LCR << UART_SHIFT]
|
||||
/* uart[UART_DLL] = div & 0xff; */
|
||||
ldr \rv, [\tmp, #12]
|
||||
and \rv, \rv, #0xff
|
||||
str \rv, [\rp, #UART_DLL << UART_SHIFT]
|
||||
/* uart[UART_DLM] = div >> 8; */
|
||||
ldr \rv, [\tmp, #12]
|
||||
lsr \rv, \rv, #8
|
||||
str \rv, [\rp, #UART_DLM << UART_SHIFT]
|
||||
/* uart[UART_LCR] = UART_LCR_WLEN8; */
|
||||
mov \rv, #UART_LCR_WLEN8
|
||||
str \rv, [\rp, #UART_LCR << UART_SHIFT]
|
||||
b 100f
|
||||
|
||||
.align
|
||||
99: .word .
|
||||
.word tegra_uart_config
|
||||
.ltorg
|
||||
|
||||
/* Load previously selected UART address */
|
||||
100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
|
||||
ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
|
||||
* check to make sure that the UART address is actually valid.
|
||||
*/
|
||||
|
||||
.macro senduart, rd, rx
|
||||
cmp \rx, #0
|
||||
strneb \rd, [\rx, #UART_TX << UART_SHIFT]
|
||||
1001:
|
||||
.endm
|
||||
|
||||
.macro busyuart, rd, rx
|
||||
cmp \rx, #0
|
||||
beq 1002f
|
||||
1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
|
||||
and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
|
||||
teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
|
||||
bne 1001b
|
||||
1002:
|
||||
.endm
|
||||
|
||||
.macro waituart, rd, rx
|
||||
#ifdef FLOW_CONTROL
|
||||
cmp \rx, #0
|
||||
beq 1002f
|
||||
1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
|
||||
tst \rd, #UART_MSR_CTS
|
||||
beq 1001b
|
||||
1002:
|
||||
#endif
|
||||
.endm
|
|
@ -57,57 +57,6 @@ config TEGRA_AHB
|
|||
which controls AHB bus master arbitration and some
|
||||
perfomance parameters(priority, prefech size).
|
||||
|
||||
choice
|
||||
prompt "Default low-level debug console UART"
|
||||
default TEGRA_DEBUG_UART_NONE
|
||||
|
||||
config TEGRA_DEBUG_UART_NONE
|
||||
bool "None"
|
||||
|
||||
config TEGRA_DEBUG_UARTA
|
||||
bool "UART-A"
|
||||
|
||||
config TEGRA_DEBUG_UARTB
|
||||
bool "UART-B"
|
||||
|
||||
config TEGRA_DEBUG_UARTC
|
||||
bool "UART-C"
|
||||
|
||||
config TEGRA_DEBUG_UARTD
|
||||
bool "UART-D"
|
||||
|
||||
config TEGRA_DEBUG_UARTE
|
||||
bool "UART-E"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Automatic low-level debug console UART"
|
||||
default TEGRA_DEBUG_UART_AUTO_NONE
|
||||
|
||||
config TEGRA_DEBUG_UART_AUTO_NONE
|
||||
bool "None"
|
||||
|
||||
config TEGRA_DEBUG_UART_AUTO_ODMDATA
|
||||
bool "Via ODMDATA"
|
||||
help
|
||||
Automatically determines which UART to use for low-level debug based
|
||||
on the ODMDATA value. This value is part of the BCT, and is written
|
||||
to the boot memory device using nvflash, or other flashing tool.
|
||||
When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
|
||||
0/1/2/3/4 are UART A/B/C/D/E.
|
||||
|
||||
config TEGRA_DEBUG_UART_AUTO_SCRATCH
|
||||
bool "Via UART scratch register"
|
||||
help
|
||||
Automatically determines which UART to use for low-level debug based
|
||||
on the UART scratch register value. Some bootloaders put ASCII 'D'
|
||||
in this register when they initialize their own console UART output.
|
||||
Using this option allows the kernel to automatically pick the same
|
||||
UART.
|
||||
|
||||
endchoice
|
||||
|
||||
config TEGRA_EMC_SCALING_ENABLE
|
||||
bool "Enable scaling the memory frequency"
|
||||
|
||||
|
|
|
@ -12,10 +12,12 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o
|
|||
obj-$(CONFIG_CPU_IDLE) += sleep.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-t20.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
|
||||
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-t30.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
obj-$(CONFIG_SMP) += reset.o
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/iomap.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
@ -24,9 +23,8 @@
|
|||
#include <linux/sched.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include "apbio.h"
|
||||
#include "iomap.h"
|
||||
|
||||
#if defined(CONFIG_TEGRA20_APB_DMA)
|
||||
static DEFINE_MUTEX(tegra_apb_dma_lock);
|
||||
|
@ -71,7 +69,6 @@ bool tegra_apb_dma_init(void)
|
|||
|
||||
dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR;
|
||||
dma_sconfig.src_maxburst = 1;
|
||||
dma_sconfig.dst_maxburst = 1;
|
||||
|
||||
|
|
|
@ -40,12 +40,10 @@
|
|||
#include <asm/mach/time.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "clock.h"
|
||||
#include "common.h"
|
||||
#include "iomap.h"
|
||||
|
||||
struct tegra_ehci_platform_data tegra_ehci1_pdata = {
|
||||
.operating_mode = TEGRA_USB_OTG,
|
||||
|
@ -91,6 +89,17 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
|
|||
&tegra_ehci3_pdata),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL),
|
||||
{}
|
||||
};
|
||||
|
||||
|
@ -104,8 +113,20 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
|
|||
{ "pll_a", "pll_p_out1", 56448000, true },
|
||||
{ "pll_a_out0", "pll_a", 11289600, true },
|
||||
{ "cdev1", NULL, 0, true },
|
||||
{ "blink", "clk_32k", 32768, true },
|
||||
{ "i2s1", "pll_a_out0", 11289600, false},
|
||||
{ "i2s2", "pll_a_out0", 11289600, false},
|
||||
{ "sdmmc1", "pll_p", 48000000, false},
|
||||
{ "sdmmc3", "pll_p", 48000000, false},
|
||||
{ "sdmmc4", "pll_p", 48000000, false},
|
||||
{ "spi", "pll_p", 20000000, false },
|
||||
{ "sbc1", "pll_p", 100000000, false },
|
||||
{ "sbc2", "pll_p", 100000000, false },
|
||||
{ "sbc3", "pll_p", 100000000, false },
|
||||
{ "sbc4", "pll_p", 100000000, false },
|
||||
{ "host1x", "pll_c", 150000000, false },
|
||||
{ "disp1", "pll_p", 600000000, false },
|
||||
{ "disp2", "pll_p", 600000000, false },
|
||||
{ NULL, NULL, 0, 0},
|
||||
};
|
||||
|
||||
|
|
|
@ -33,11 +33,10 @@
|
|||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "clock.h"
|
||||
#include "common.h"
|
||||
#include "iomap.h"
|
||||
|
||||
struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
|
||||
|
@ -52,6 +51,18 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
|
|||
OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
|
||||
OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
|
||||
{}
|
||||
};
|
||||
|
||||
|
@ -62,11 +73,24 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
|
|||
{ "pll_a_out0", "pll_a", 11289600, true },
|
||||
{ "extern1", "pll_a_out0", 0, true },
|
||||
{ "clk_out_1", "extern1", 0, true },
|
||||
{ "blink", "clk_32k", 32768, true },
|
||||
{ "i2s0", "pll_a_out0", 11289600, false},
|
||||
{ "i2s1", "pll_a_out0", 11289600, false},
|
||||
{ "i2s2", "pll_a_out0", 11289600, false},
|
||||
{ "i2s3", "pll_a_out0", 11289600, false},
|
||||
{ "i2s4", "pll_a_out0", 11289600, false},
|
||||
{ "sdmmc1", "pll_p", 48000000, false},
|
||||
{ "sdmmc3", "pll_p", 48000000, false},
|
||||
{ "sdmmc4", "pll_p", 48000000, false},
|
||||
{ "sbc1", "pll_p", 100000000, false},
|
||||
{ "sbc2", "pll_p", 100000000, false},
|
||||
{ "sbc3", "pll_p", 100000000, false},
|
||||
{ "sbc4", "pll_p", 100000000, false},
|
||||
{ "sbc5", "pll_p", 100000000, false},
|
||||
{ "sbc6", "pll_p", 100000000, false},
|
||||
{ "host1x", "pll_c", 150000000, false},
|
||||
{ "disp1", "pll_p", 600000000, false},
|
||||
{ "disp2", "pll_p", 600000000, false},
|
||||
{ NULL, NULL, 0, 0},
|
||||
};
|
||||
|
||||
|
|
|
@ -27,8 +27,6 @@
|
|||
#include <linux/seq_file.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <mach/clk.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "clock.h"
|
||||
#include "tegra_cpu_car.h"
|
||||
|
|
|
@ -26,13 +26,13 @@
|
|||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/powergate.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "clock.h"
|
||||
#include "common.h"
|
||||
#include "fuse.h"
|
||||
#include "iomap.h"
|
||||
#include "pmc.h"
|
||||
#include "apbio.h"
|
||||
#include "sleep.h"
|
||||
|
@ -44,14 +44,15 @@
|
|||
* kernel is loaded. The data is declared here rather than debug-macro.S so
|
||||
* that multiple inclusions of debug-macro.S point at the same data.
|
||||
*/
|
||||
#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
|
||||
u32 tegra_uart_config[3] = {
|
||||
u32 tegra_uart_config[4] = {
|
||||
/* Debug UART initialization required */
|
||||
1,
|
||||
/* Debug UART physical address */
|
||||
(u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
|
||||
0,
|
||||
/* Debug UART virtual address */
|
||||
(u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
|
||||
0,
|
||||
/* Scratch space for debug macro */
|
||||
0,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
@ -104,25 +105,26 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
|
|||
{ "clk_m", NULL, 0, true },
|
||||
{ "pll_p", "clk_m", 408000000, true },
|
||||
{ "pll_p_out1", "pll_p", 9600000, true },
|
||||
{ "pll_p_out4", "pll_p", 102000000, true },
|
||||
{ "sclk", "pll_p_out4", 102000000, true },
|
||||
{ "hclk", "sclk", 102000000, true },
|
||||
{ "pclk", "hclk", 51000000, true },
|
||||
{ NULL, NULL, 0, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
|
||||
static void __init tegra_init_cache(void)
|
||||
{
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
|
||||
u32 aux_ctrl, cache_type;
|
||||
|
||||
writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
|
||||
writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
|
||||
|
||||
cache_type = readl(p + L2X0_CACHE_TYPE);
|
||||
aux_ctrl = (cache_type & 0x700) << (17-8);
|
||||
aux_ctrl |= 0x6C000001;
|
||||
aux_ctrl |= 0x7C400001;
|
||||
|
||||
l2x0_init(p, aux_ctrl, 0x8200c3fe);
|
||||
l2x0_of_init(aux_ctrl, 0x8200c3fe);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
@ -134,7 +136,7 @@ void __init tegra20_init_early(void)
|
|||
tegra_init_fuse();
|
||||
tegra2_init_clocks();
|
||||
tegra_clk_init_from_table(tegra20_clk_init_table);
|
||||
tegra_init_cache(0x331, 0x441);
|
||||
tegra_init_cache();
|
||||
tegra_pmc_init();
|
||||
tegra_powergate_init();
|
||||
tegra20_hotplug_init();
|
||||
|
@ -147,7 +149,7 @@ void __init tegra30_init_early(void)
|
|||
tegra_init_fuse();
|
||||
tegra30_init_clocks();
|
||||
tegra_clk_init_from_table(tegra30_clk_init_table);
|
||||
tegra_init_cache(0x441, 0x551);
|
||||
tegra_init_cache();
|
||||
tegra_pmc_init();
|
||||
tegra_powergate_init();
|
||||
tegra30_hotplug_init();
|
||||
|
|
|
@ -30,9 +30,6 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/suspend.h>
|
||||
|
||||
|
||||
#include <mach/clk.h>
|
||||
|
||||
/* Frequency table index must be sequential starting at 0 */
|
||||
static struct cpufreq_frequency_table freq_table[] = {
|
||||
{ 0, 216000 },
|
||||
|
|
|
@ -29,8 +29,6 @@
|
|||
|
||||
#include <asm/proc-fns.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv, int index);
|
||||
|
||||
|
|
|
@ -22,9 +22,8 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "flowctrl.h"
|
||||
#include "iomap.h"
|
||||
|
||||
u8 flowctrl_offset_halt_cpu[] = {
|
||||
FLOW_CTRL_HALT_CPU0_EVENTS,
|
||||
|
|
|
@ -21,22 +21,28 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "fuse.h"
|
||||
#include "iomap.h"
|
||||
#include "apbio.h"
|
||||
|
||||
#define FUSE_UID_LOW 0x108
|
||||
#define FUSE_UID_HIGH 0x10c
|
||||
#define FUSE_SKU_INFO 0x110
|
||||
#define FUSE_SPARE_BIT 0x200
|
||||
|
||||
#define TEGRA20_FUSE_SPARE_BIT 0x200
|
||||
#define TEGRA30_FUSE_SPARE_BIT 0x244
|
||||
|
||||
int tegra_sku_id;
|
||||
int tegra_cpu_process_id;
|
||||
int tegra_core_process_id;
|
||||
int tegra_chip_id;
|
||||
int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
|
||||
int tegra_soc_speedo_id;
|
||||
enum tegra_revision tegra_revision;
|
||||
|
||||
static int tegra_fuse_spare_bit;
|
||||
static void (*tegra_init_speedo_data)(void);
|
||||
|
||||
/* The BCT to use at boot is specified by board straps that can be read
|
||||
* through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
|
||||
*/
|
||||
|
@ -57,14 +63,14 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
|
|||
[TEGRA_REVISION_A04] = "A04",
|
||||
};
|
||||
|
||||
static inline u32 tegra_fuse_readl(unsigned long offset)
|
||||
u32 tegra_fuse_readl(unsigned long offset)
|
||||
{
|
||||
return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
|
||||
}
|
||||
|
||||
static inline bool get_spare_fuse(int bit)
|
||||
bool tegra_spare_fuse(int bit)
|
||||
{
|
||||
return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
|
||||
return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
|
||||
}
|
||||
|
||||
static enum tegra_revision tegra_get_revision(u32 id)
|
||||
|
@ -78,7 +84,7 @@ static enum tegra_revision tegra_get_revision(u32 id)
|
|||
return TEGRA_REVISION_A02;
|
||||
case 3:
|
||||
if (tegra_chip_id == TEGRA20 &&
|
||||
(get_spare_fuse(18) || get_spare_fuse(19)))
|
||||
(tegra_spare_fuse(18) || tegra_spare_fuse(19)))
|
||||
return TEGRA_REVISION_A03p;
|
||||
else
|
||||
return TEGRA_REVISION_A03;
|
||||
|
@ -89,6 +95,16 @@ static enum tegra_revision tegra_get_revision(u32 id)
|
|||
}
|
||||
}
|
||||
|
||||
static void tegra_get_process_id(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = tegra_fuse_readl(tegra_fuse_spare_bit);
|
||||
tegra_cpu_process_id = (reg >> 6) & 3;
|
||||
reg = tegra_fuse_readl(tegra_fuse_spare_bit);
|
||||
tegra_core_process_id = (reg >> 12) & 3;
|
||||
}
|
||||
|
||||
void tegra_init_fuse(void)
|
||||
{
|
||||
u32 id;
|
||||
|
@ -100,19 +116,29 @@ void tegra_init_fuse(void)
|
|||
reg = tegra_fuse_readl(FUSE_SKU_INFO);
|
||||
tegra_sku_id = reg & 0xFF;
|
||||
|
||||
reg = tegra_fuse_readl(FUSE_SPARE_BIT);
|
||||
tegra_cpu_process_id = (reg >> 6) & 3;
|
||||
|
||||
reg = tegra_fuse_readl(FUSE_SPARE_BIT);
|
||||
tegra_core_process_id = (reg >> 12) & 3;
|
||||
|
||||
reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
|
||||
tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
|
||||
|
||||
id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
|
||||
tegra_chip_id = (id >> 8) & 0xff;
|
||||
|
||||
switch (tegra_chip_id) {
|
||||
case TEGRA20:
|
||||
tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
|
||||
tegra_init_speedo_data = &tegra20_init_speedo_data;
|
||||
break;
|
||||
case TEGRA30:
|
||||
tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
|
||||
tegra_init_speedo_data = &tegra30_init_speedo_data;
|
||||
break;
|
||||
default:
|
||||
pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
|
||||
tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
|
||||
tegra_init_speedo_data = &tegra_get_process_id;
|
||||
}
|
||||
|
||||
tegra_revision = tegra_get_revision(id);
|
||||
tegra_init_speedo_data();
|
||||
|
||||
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
|
||||
tegra_revision_name[tegra_revision],
|
||||
|
|
|
@ -42,11 +42,27 @@ extern int tegra_sku_id;
|
|||
extern int tegra_cpu_process_id;
|
||||
extern int tegra_core_process_id;
|
||||
extern int tegra_chip_id;
|
||||
extern int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
|
||||
extern int tegra_soc_speedo_id;
|
||||
extern enum tegra_revision tegra_revision;
|
||||
|
||||
extern int tegra_bct_strapping;
|
||||
|
||||
unsigned long long tegra_chip_uid(void);
|
||||
void tegra_init_fuse(void);
|
||||
bool tegra_spare_fuse(int bit);
|
||||
u32 tegra_fuse_readl(unsigned long offset);
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
||||
void tegra20_init_speedo_data(void);
|
||||
#else
|
||||
static inline void tegra20_init_speedo_data(void) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
void tegra30_init_speedo_data(void);
|
||||
#else
|
||||
static inline void tegra30_init_speedo_data(void) {}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
@ -3,9 +3,8 @@
|
|||
|
||||
#include <asm/cache.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "flowctrl.h"
|
||||
#include "iomap.h"
|
||||
#include "reset.h"
|
||||
#include "sleep.h"
|
||||
|
||||
|
|
|
@ -1,100 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-tegra/include/mach/debug-macro.S
|
||||
*
|
||||
* Copyright (C) 2010,2011 Google, Inc.
|
||||
* Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
|
||||
*
|
||||
* Author:
|
||||
* Colin Cross <ccross@google.com>
|
||||
* Erik Gilling <konkers@google.com>
|
||||
* Doug Anderson <dianders@chromium.org>
|
||||
* Stephen Warren <swarren@nvidia.com>
|
||||
*
|
||||
* Portions based on mach-omap2's debug-macro.S
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/serial_reg.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/irammap.h>
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
adr \rp, 99f @ actual addr of 99f
|
||||
ldr \rv, [\rp] @ linked addr is stored there
|
||||
sub \rv, \rv, \rp @ offset between the two
|
||||
ldr \rp, [\rp, #4] @ linked tegra_uart_config
|
||||
sub \tmp, \rp, \rv @ actual tegra_uart_config
|
||||
ldr \rp, [\tmp] @ Load tegra_uart_config
|
||||
cmp \rp, #1 @ needs intitialization?
|
||||
bne 100f @ no; go load the addresses
|
||||
mov \rv, #0 @ yes; record init is done
|
||||
str \rv, [\tmp]
|
||||
mov \rp, #TEGRA_IRAM_BASE @ See if cookie is in IRAM
|
||||
ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET]
|
||||
movw \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff
|
||||
movt \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16
|
||||
cmp \rv, \rp @ Cookie present?
|
||||
bne 100f @ No, use default UART
|
||||
mov \rp, #TEGRA_IRAM_BASE @ Load UART address from IRAM
|
||||
ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4]
|
||||
str \rv, [\tmp, #4] @ Store in tegra_uart_phys
|
||||
sub \rv, \rv, #IO_APB_PHYS @ Calculate virt address
|
||||
add \rv, \rv, #IO_APB_VIRT
|
||||
str \rv, [\tmp, #8] @ Store in tegra_uart_virt
|
||||
b 100f
|
||||
|
||||
.align
|
||||
99: .word .
|
||||
.word tegra_uart_config
|
||||
.ltorg
|
||||
|
||||
100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
|
||||
ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
|
||||
.endm
|
||||
|
||||
#define UART_SHIFT 2
|
||||
|
||||
/*
|
||||
* Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
|
||||
* check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case.
|
||||
* We use the fact that all 5 valid UART addresses all have something in the
|
||||
* 2nd-to-lowest byte.
|
||||
*/
|
||||
|
||||
.macro senduart, rd, rx
|
||||
tst \rx, #0x0000ff00
|
||||
strneb \rd, [\rx, #UART_TX << UART_SHIFT]
|
||||
1001:
|
||||
.endm
|
||||
|
||||
.macro busyuart, rd, rx
|
||||
tst \rx, #0x0000ff00
|
||||
beq 1002f
|
||||
1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
|
||||
and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
|
||||
teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
|
||||
bne 1001b
|
||||
1002:
|
||||
.endm
|
||||
|
||||
.macro waituart, rd, rx
|
||||
#ifdef FLOW_CONTROL
|
||||
tst \rx, #0x0000ff00
|
||||
beq 1002f
|
||||
1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
|
||||
tst \rd, #UART_MSR_CTS
|
||||
beq 1001b
|
||||
1002:
|
||||
#endif
|
||||
.endm
|
|
@ -1,54 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-tegra/include/mach/dma.h
|
||||
*
|
||||
* Copyright (c) 2008-2009, NVIDIA Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_DMA_H
|
||||
#define __MACH_TEGRA_DMA_H
|
||||
|
||||
#include <linux/list.h>
|
||||
|
||||
#define TEGRA_DMA_REQ_SEL_CNTR 0
|
||||
#define TEGRA_DMA_REQ_SEL_I2S_2 1
|
||||
#define TEGRA_DMA_REQ_SEL_I2S_1 2
|
||||
#define TEGRA_DMA_REQ_SEL_SPD_I 3
|
||||
#define TEGRA_DMA_REQ_SEL_UI_I 4
|
||||
#define TEGRA_DMA_REQ_SEL_MIPI 5
|
||||
#define TEGRA_DMA_REQ_SEL_I2S2_2 6
|
||||
#define TEGRA_DMA_REQ_SEL_I2S2_1 7
|
||||
#define TEGRA_DMA_REQ_SEL_UARTA 8
|
||||
#define TEGRA_DMA_REQ_SEL_UARTB 9
|
||||
#define TEGRA_DMA_REQ_SEL_UARTC 10
|
||||
#define TEGRA_DMA_REQ_SEL_SPI 11
|
||||
#define TEGRA_DMA_REQ_SEL_AC97 12
|
||||
#define TEGRA_DMA_REQ_SEL_ACMODEM 13
|
||||
#define TEGRA_DMA_REQ_SEL_SL4B 14
|
||||
#define TEGRA_DMA_REQ_SEL_SL2B1 15
|
||||
#define TEGRA_DMA_REQ_SEL_SL2B2 16
|
||||
#define TEGRA_DMA_REQ_SEL_SL2B3 17
|
||||
#define TEGRA_DMA_REQ_SEL_SL2B4 18
|
||||
#define TEGRA_DMA_REQ_SEL_UARTD 19
|
||||
#define TEGRA_DMA_REQ_SEL_UARTE 20
|
||||
#define TEGRA_DMA_REQ_SEL_I2C 21
|
||||
#define TEGRA_DMA_REQ_SEL_I2C2 22
|
||||
#define TEGRA_DMA_REQ_SEL_I2C3 23
|
||||
#define TEGRA_DMA_REQ_SEL_DVC_I2C 24
|
||||
#define TEGRA_DMA_REQ_SEL_OWR 25
|
||||
#define TEGRA_DMA_REQ_SEL_INVALID 31
|
||||
|
||||
#endif
|
|
@ -1,182 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-tegra/include/mach/irqs.h
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
*
|
||||
* Author:
|
||||
* Colin Cross <ccross@google.com>
|
||||
* Erik Gilling <konkers@google.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_IRQS_H
|
||||
#define __MACH_TEGRA_IRQS_H
|
||||
|
||||
#define INT_GIC_BASE 0
|
||||
|
||||
#define IRQ_LOCALTIMER 29
|
||||
|
||||
/* Primary Interrupt Controller */
|
||||
#define INT_PRI_BASE (INT_GIC_BASE + 32)
|
||||
#define INT_TMR1 (INT_PRI_BASE + 0)
|
||||
#define INT_TMR2 (INT_PRI_BASE + 1)
|
||||
#define INT_RTC (INT_PRI_BASE + 2)
|
||||
#define INT_I2S2 (INT_PRI_BASE + 3)
|
||||
#define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4)
|
||||
#define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5)
|
||||
#define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6)
|
||||
#define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7)
|
||||
#define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8)
|
||||
#define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9)
|
||||
#define INT_VDE_BSE_V (INT_PRI_BASE + 10)
|
||||
#define INT_VDE_BSE_A (INT_PRI_BASE + 11)
|
||||
#define INT_VDE_SXE (INT_PRI_BASE + 12)
|
||||
#define INT_I2S1 (INT_PRI_BASE + 13)
|
||||
#define INT_SDMMC1 (INT_PRI_BASE + 14)
|
||||
#define INT_SDMMC2 (INT_PRI_BASE + 15)
|
||||
#define INT_XIO (INT_PRI_BASE + 16)
|
||||
#define INT_VDE (INT_PRI_BASE + 17)
|
||||
#define INT_AVP_UCQ (INT_PRI_BASE + 18)
|
||||
#define INT_SDMMC3 (INT_PRI_BASE + 19)
|
||||
#define INT_USB (INT_PRI_BASE + 20)
|
||||
#define INT_USB2 (INT_PRI_BASE + 21)
|
||||
#define INT_PRI_RES_22 (INT_PRI_BASE + 22)
|
||||
#define INT_EIDE (INT_PRI_BASE + 23)
|
||||
#define INT_NANDFLASH (INT_PRI_BASE + 24)
|
||||
#define INT_VCP (INT_PRI_BASE + 25)
|
||||
#define INT_APB_DMA (INT_PRI_BASE + 26)
|
||||
#define INT_AHB_DMA (INT_PRI_BASE + 27)
|
||||
#define INT_GNT_0 (INT_PRI_BASE + 28)
|
||||
#define INT_GNT_1 (INT_PRI_BASE + 29)
|
||||
#define INT_OWR (INT_PRI_BASE + 30)
|
||||
#define INT_SDMMC4 (INT_PRI_BASE + 31)
|
||||
|
||||
/* Secondary Interrupt Controller */
|
||||
#define INT_SEC_BASE (INT_PRI_BASE + 32)
|
||||
#define INT_GPIO1 (INT_SEC_BASE + 0)
|
||||
#define INT_GPIO2 (INT_SEC_BASE + 1)
|
||||
#define INT_GPIO3 (INT_SEC_BASE + 2)
|
||||
#define INT_GPIO4 (INT_SEC_BASE + 3)
|
||||
#define INT_UARTA (INT_SEC_BASE + 4)
|
||||
#define INT_UARTB (INT_SEC_BASE + 5)
|
||||
#define INT_I2C (INT_SEC_BASE + 6)
|
||||
#define INT_SPI (INT_SEC_BASE + 7)
|
||||
#define INT_TWC (INT_SEC_BASE + 8)
|
||||
#define INT_TMR3 (INT_SEC_BASE + 9)
|
||||
#define INT_TMR4 (INT_SEC_BASE + 10)
|
||||
#define INT_FLOW_RSM0 (INT_SEC_BASE + 11)
|
||||
#define INT_FLOW_RSM1 (INT_SEC_BASE + 12)
|
||||
#define INT_SPDIF (INT_SEC_BASE + 13)
|
||||
#define INT_UARTC (INT_SEC_BASE + 14)
|
||||
#define INT_MIPI (INT_SEC_BASE + 15)
|
||||
#define INT_EVENTA (INT_SEC_BASE + 16)
|
||||
#define INT_EVENTB (INT_SEC_BASE + 17)
|
||||
#define INT_EVENTC (INT_SEC_BASE + 18)
|
||||
#define INT_EVENTD (INT_SEC_BASE + 19)
|
||||
#define INT_VFIR (INT_SEC_BASE + 20)
|
||||
#define INT_DVC (INT_SEC_BASE + 21)
|
||||
#define INT_SYS_STATS_MON (INT_SEC_BASE + 22)
|
||||
#define INT_GPIO5 (INT_SEC_BASE + 23)
|
||||
#define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24)
|
||||
#define INT_CPU1_PMU_INTR (INT_SEC_BASE + 25)
|
||||
#define INT_SEC_RES_26 (INT_SEC_BASE + 26)
|
||||
#define INT_S_LINK1 (INT_SEC_BASE + 27)
|
||||
#define INT_APB_DMA_COP (INT_SEC_BASE + 28)
|
||||
#define INT_AHB_DMA_COP (INT_SEC_BASE + 29)
|
||||
#define INT_DMA_TX (INT_SEC_BASE + 30)
|
||||
#define INT_DMA_RX (INT_SEC_BASE + 31)
|
||||
|
||||
/* Tertiary Interrupt Controller */
|
||||
#define INT_TRI_BASE (INT_SEC_BASE + 32)
|
||||
#define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0)
|
||||
#define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1)
|
||||
#define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2)
|
||||
#define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3)
|
||||
#define INT_MPE_GENERAL (INT_TRI_BASE + 4)
|
||||
#define INT_VI_GENERAL (INT_TRI_BASE + 5)
|
||||
#define INT_EPP_GENERAL (INT_TRI_BASE + 6)
|
||||
#define INT_ISP_GENERAL (INT_TRI_BASE + 7)
|
||||
#define INT_2D_GENERAL (INT_TRI_BASE + 8)
|
||||
#define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9)
|
||||
#define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10)
|
||||
#define INT_HDMI (INT_TRI_BASE + 11)
|
||||
#define INT_TVO_GENERAL (INT_TRI_BASE + 12)
|
||||
#define INT_MC_GENERAL (INT_TRI_BASE + 13)
|
||||
#define INT_EMC_GENERAL (INT_TRI_BASE + 14)
|
||||
#define INT_TRI_RES_15 (INT_TRI_BASE + 15)
|
||||
#define INT_TRI_RES_16 (INT_TRI_BASE + 16)
|
||||
#define INT_AC97 (INT_TRI_BASE + 17)
|
||||
#define INT_SPI_2 (INT_TRI_BASE + 18)
|
||||
#define INT_SPI_3 (INT_TRI_BASE + 19)
|
||||
#define INT_I2C2 (INT_TRI_BASE + 20)
|
||||
#define INT_KBC (INT_TRI_BASE + 21)
|
||||
#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22)
|
||||
#define INT_GPIO6 (INT_TRI_BASE + 23)
|
||||
#define INT_TVDAC (INT_TRI_BASE + 24)
|
||||
#define INT_GPIO7 (INT_TRI_BASE + 25)
|
||||
#define INT_UARTD (INT_TRI_BASE + 26)
|
||||
#define INT_UARTE (INT_TRI_BASE + 27)
|
||||
#define INT_I2C3 (INT_TRI_BASE + 28)
|
||||
#define INT_SPI_4 (INT_TRI_BASE + 29)
|
||||
#define INT_TRI_RES_30 (INT_TRI_BASE + 30)
|
||||
#define INT_SW_RESERVED (INT_TRI_BASE + 31)
|
||||
|
||||
/* Quaternary Interrupt Controller */
|
||||
#define INT_QUAD_BASE (INT_TRI_BASE + 32)
|
||||
#define INT_SNOR (INT_QUAD_BASE + 0)
|
||||
#define INT_USB3 (INT_QUAD_BASE + 1)
|
||||
#define INT_PCIE_INTR (INT_QUAD_BASE + 2)
|
||||
#define INT_PCIE_MSI (INT_QUAD_BASE + 3)
|
||||
#define INT_QUAD_RES_4 (INT_QUAD_BASE + 4)
|
||||
#define INT_QUAD_RES_5 (INT_QUAD_BASE + 5)
|
||||
#define INT_QUAD_RES_6 (INT_QUAD_BASE + 6)
|
||||
#define INT_QUAD_RES_7 (INT_QUAD_BASE + 7)
|
||||
#define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8)
|
||||
#define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9)
|
||||
#define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10)
|
||||
#define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11)
|
||||
#define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12)
|
||||
#define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13)
|
||||
#define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14)
|
||||
#define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15)
|
||||
#define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16)
|
||||
#define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17)
|
||||
#define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18)
|
||||
#define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19)
|
||||
#define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20)
|
||||
#define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21)
|
||||
#define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22)
|
||||
#define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23)
|
||||
#define INT_QUAD_RES_24 (INT_QUAD_BASE + 24)
|
||||
#define INT_QUAD_RES_25 (INT_QUAD_BASE + 25)
|
||||
#define INT_QUAD_RES_26 (INT_QUAD_BASE + 26)
|
||||
#define INT_QUAD_RES_27 (INT_QUAD_BASE + 27)
|
||||
#define INT_QUAD_RES_28 (INT_QUAD_BASE + 28)
|
||||
#define INT_QUAD_RES_29 (INT_QUAD_BASE + 29)
|
||||
#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30)
|
||||
#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31)
|
||||
|
||||
/* Tegra30 has 5 banks of 32 IRQs */
|
||||
#define INT_MAIN_NR (32 * 5)
|
||||
#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR)
|
||||
|
||||
/* Tegra30 has 8 banks of 32 GPIOs */
|
||||
#define INT_GPIO_NR (32 * 8)
|
||||
|
||||
#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR)
|
||||
|
||||
#define INT_BOARD_BASE TEGRA_NR_IRQS
|
||||
#define NR_BOARD_IRQS 32
|
||||
|
||||
#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS)
|
||||
|
||||
#endif
|
|
@ -20,6 +20,8 @@
|
|||
#ifndef _MACH_TEGRA_POWERGATE_H_
|
||||
#define _MACH_TEGRA_POWERGATE_H_
|
||||
|
||||
struct clk;
|
||||
|
||||
#define TEGRA_POWERGATE_CPU 0
|
||||
#define TEGRA_POWERGATE_3D 1
|
||||
#define TEGRA_POWERGATE_VENC 2
|
||||
|
|
|
@ -28,8 +28,7 @@
|
|||
#include <linux/types.h>
|
||||
#include <linux/serial_reg.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/irammap.h>
|
||||
#include "../../iomap.h"
|
||||
|
||||
#define BIT(x) (1 << (x))
|
||||
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
|
||||
|
@ -52,17 +51,6 @@ static inline void flush(void)
|
|||
{
|
||||
}
|
||||
|
||||
static inline void save_uart_address(void)
|
||||
{
|
||||
u32 *buf = (u32 *)(TEGRA_IRAM_BASE + TEGRA_IRAM_DEBUG_UART_OFFSET);
|
||||
|
||||
if (uart) {
|
||||
buf[0] = TEGRA_IRAM_DEBUG_UART_COOKIE;
|
||||
buf[1] = (u32)uart;
|
||||
} else
|
||||
buf[0] = 0;
|
||||
}
|
||||
|
||||
static const struct {
|
||||
u32 base;
|
||||
u32 reset_reg;
|
||||
|
@ -139,51 +127,19 @@ int auto_odmdata(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH
|
||||
int auto_scratch(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Look for the first UART that:
|
||||
* a) Is not in reset.
|
||||
* b) Is clocked.
|
||||
* c) Has a 'D' in the scratchpad register.
|
||||
*
|
||||
* Note that on Tegra30, the first two conditions are required, since
|
||||
* if not true, accesses to the UART scratch register will hang.
|
||||
* Tegra20 doesn't have this issue.
|
||||
*
|
||||
* The intent is that the bootloader will tell the kernel which UART
|
||||
* to use by setting up those conditions. If nothing found, we'll fall
|
||||
* back to what's specified in TEGRA_DEBUG_UART_BASE.
|
||||
*/
|
||||
for (i = 0; i < ARRAY_SIZE(uarts); i++) {
|
||||
if (!uart_clocked(i))
|
||||
continue;
|
||||
|
||||
uart = (volatile u8 *)uarts[i].base;
|
||||
if (uart[UART_SCR << DEBUG_UART_SHIFT] != 'D')
|
||||
continue;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Setup before decompression. This is where we do UART selection for
|
||||
* earlyprintk and init the uart_base register.
|
||||
*/
|
||||
static inline void arch_decomp_setup(void)
|
||||
{
|
||||
int uart_id, auto_uart_id;
|
||||
int uart_id;
|
||||
volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
|
||||
u32 chip, div;
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTA)
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
uart_id = auto_odmdata();
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
|
||||
uart_id = 0;
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
|
||||
uart_id = 1;
|
||||
|
@ -193,27 +149,14 @@ static inline void arch_decomp_setup(void)
|
|||
uart_id = 3;
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
|
||||
uart_id = 4;
|
||||
#else
|
||||
uart_id = -1;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
auto_uart_id = auto_odmdata();
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH)
|
||||
auto_uart_id = auto_scratch();
|
||||
#else
|
||||
auto_uart_id = -1;
|
||||
#endif
|
||||
if (auto_uart_id != -1)
|
||||
uart_id = auto_uart_id;
|
||||
|
||||
if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) ||
|
||||
!uart_clocked(uart_id))
|
||||
uart = NULL;
|
||||
else
|
||||
uart = (volatile u8 *)uarts[uart_id].base;
|
||||
|
||||
save_uart_address();
|
||||
if (uart == NULL)
|
||||
return;
|
||||
|
||||
|
|
|
@ -26,9 +26,9 @@
|
|||
|
||||
#include <asm/page.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "iomap.h"
|
||||
|
||||
static struct map_desc tegra_io_desc[] __initdata = {
|
||||
{
|
||||
|
@ -59,5 +59,6 @@ static struct map_desc tegra_io_desc[] __initdata = {
|
|||
|
||||
void __init tegra_map_common_io(void)
|
||||
{
|
||||
debug_ll_io_init();
|
||||
iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
|
||||
}
|
||||
|
|
|
@ -1,6 +1,4 @@
|
|||
/*
|
||||
* arch/arm/mach-tegra/include/mach/iomap.h
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
*
|
||||
* Author:
|
||||
|
@ -263,20 +261,6 @@
|
|||
#define TEGRA_SDMMC4_BASE 0xC8000600
|
||||
#define TEGRA_SDMMC4_SIZE SZ_512
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
|
||||
# define TEGRA_DEBUG_UART_BASE 0
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
|
||||
# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
|
||||
# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
|
||||
# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
|
||||
# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
|
||||
# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
|
||||
#endif
|
||||
|
||||
/* On TEGRA, many peripherals are very closely packed in
|
||||
* two 256MB io windows (that actually only use about 64KB
|
||||
* at the start of each).
|
|
@ -23,13 +23,4 @@
|
|||
#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
|
||||
#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
|
||||
|
||||
/*
|
||||
* These locations are written to by uncompress.h, and read by debug-macro.S.
|
||||
* The first word holds the cookie value if the data is valid. The second
|
||||
* word holds the UART physical address.
|
||||
*/
|
||||
#define TEGRA_IRAM_DEBUG_UART_OFFSET SZ_1K
|
||||
#define TEGRA_IRAM_DEBUG_UART_SIZE 8
|
||||
#define TEGRA_IRAM_DEBUG_UART_COOKIE 0x55415254
|
||||
|
||||
#endif
|
|
@ -25,9 +25,8 @@
|
|||
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "iomap.h"
|
||||
|
||||
#define ICTLR_CPU_IEP_VFIQ 0x08
|
||||
#define ICTLR_CPU_IEP_FIR 0x14
|
||||
|
|
|
@ -37,11 +37,14 @@
|
|||
#include <asm/sizes.h>
|
||||
#include <asm/mach/pci.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/clk.h>
|
||||
#include <mach/powergate.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "iomap.h"
|
||||
|
||||
/* Hack - need to parse this from DT */
|
||||
#define INT_PCIE_INTR 130
|
||||
|
||||
/* register definitions */
|
||||
#define AFI_OFFSET 0x3800
|
||||
|
|
|
@ -24,8 +24,6 @@
|
|||
#include <asm/mach-types.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
||||
#include <mach/clk.h>
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/powergate.h>
|
||||
|
||||
#include "fuse.h"
|
||||
|
@ -34,6 +32,7 @@
|
|||
#include "tegra_cpu_car.h"
|
||||
|
||||
#include "common.h"
|
||||
#include "iomap.h"
|
||||
|
||||
extern void tegra_secondary_startup(void);
|
||||
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include "iomap.h"
|
||||
|
||||
#define PMC_CTRL 0x0
|
||||
#define PMC_CTRL_INTR_LOW (1 << 17)
|
||||
|
|
|
@ -28,10 +28,10 @@
|
|||
#include <linux/spinlock.h>
|
||||
|
||||
#include <mach/clk.h>
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/powergate.h>
|
||||
|
||||
#include "fuse.h"
|
||||
#include "iomap.h"
|
||||
|
||||
#define PWRGATE_TOGGLE 0x30
|
||||
#define PWRGATE_TOGGLE_START (1 << 8)
|
||||
|
|
|
@ -22,9 +22,8 @@
|
|||
#include <asm/cacheflush.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/irammap.h>
|
||||
|
||||
#include "iomap.h"
|
||||
#include "irammap.h"
|
||||
#include "reset.h"
|
||||
#include "fuse.h"
|
||||
|
||||
|
|
|
@ -22,8 +22,6 @@
|
|||
|
||||
#include <asm/assembler.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "sleep.h"
|
||||
#include "flowctrl.h"
|
||||
|
||||
|
|
|
@ -18,8 +18,6 @@
|
|||
|
||||
#include <asm/assembler.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "sleep.h"
|
||||
#include "flowctrl.h"
|
||||
|
||||
|
|
|
@ -26,7 +26,7 @@
|
|||
|
||||
#include <asm/assembler.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include "iomap.h"
|
||||
|
||||
#include "flowctrl.h"
|
||||
#include "sleep.h"
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
#ifndef __MACH_TEGRA_SLEEP_H
|
||||
#define __MACH_TEGRA_SLEEP_H
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include "iomap.h"
|
||||
|
||||
#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
|
||||
+ IO_CPU_VIRT)
|
||||
|
|
|
@ -27,10 +27,9 @@
|
|||
#include <linux/clkdev.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "fuse.h"
|
||||
#include "iomap.h"
|
||||
#include "tegra2_emc.h"
|
||||
#include "tegra_cpu_car.h"
|
||||
|
||||
|
|
|
@ -27,8 +27,6 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "fuse.h"
|
||||
#include "tegra2_emc.h"
|
||||
|
@ -248,11 +246,16 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
|
|||
{ 19200000, 216000000, 135, 12, 1, 3},
|
||||
{ 26000000, 216000000, 216, 26, 1, 4},
|
||||
|
||||
{ 12000000, 297000000, 99, 4, 1, 4 },
|
||||
{ 12000000, 339000000, 113, 4, 1, 4 },
|
||||
|
||||
{ 12000000, 594000000, 594, 12, 1, 8},
|
||||
{ 13000000, 594000000, 594, 13, 1, 8},
|
||||
{ 19200000, 594000000, 495, 16, 1, 8},
|
||||
{ 26000000, 594000000, 594, 26, 1, 8},
|
||||
|
||||
{ 12000000, 616000000, 616, 12, 1, 8},
|
||||
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 1, 8},
|
||||
|
@ -1038,9 +1041,6 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
|
|||
CLK_DUPLICATE("usbd", "utmip-pad", NULL),
|
||||
CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
|
||||
CLK_DUPLICATE("usbd", "tegra-otg", NULL),
|
||||
CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
|
||||
CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
|
||||
CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
|
||||
CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
|
||||
CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
|
||||
CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
|
||||
|
@ -1053,6 +1053,9 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
|
|||
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
|
||||
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
|
||||
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
|
||||
CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
|
||||
CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
|
||||
CLK_DUPLICATE("pll_d_out0", "hdmi", "parent"),
|
||||
};
|
||||
|
||||
#define CLK(dev, con, ck) \
|
||||
|
|
109
arch/arm/mach-tegra/tegra20_speedo.c
Normal file
109
arch/arm/mach-tegra/tegra20_speedo.c
Normal file
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/bug.h>
|
||||
|
||||
#include "fuse.h"
|
||||
|
||||
#define CPU_SPEEDO_LSBIT 20
|
||||
#define CPU_SPEEDO_MSBIT 29
|
||||
#define CPU_SPEEDO_REDUND_LSBIT 30
|
||||
#define CPU_SPEEDO_REDUND_MSBIT 39
|
||||
#define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
|
||||
|
||||
#define CORE_SPEEDO_LSBIT 40
|
||||
#define CORE_SPEEDO_MSBIT 47
|
||||
#define CORE_SPEEDO_REDUND_LSBIT 48
|
||||
#define CORE_SPEEDO_REDUND_MSBIT 55
|
||||
#define CORE_SPEEDO_REDUND_OFFS (CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT)
|
||||
|
||||
#define SPEEDO_MULT 4
|
||||
|
||||
#define PROCESS_CORNERS_NUM 4
|
||||
|
||||
#define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2)
|
||||
#define SPEEDO_ID_SELECT_1(sku) \
|
||||
(((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
|
||||
((sku) != 27) && ((sku) != 28))
|
||||
|
||||
enum {
|
||||
SPEEDO_ID_0,
|
||||
SPEEDO_ID_1,
|
||||
SPEEDO_ID_2,
|
||||
SPEEDO_ID_COUNT,
|
||||
};
|
||||
|
||||
static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
|
||||
{315, 366, 420, UINT_MAX},
|
||||
{303, 368, 419, UINT_MAX},
|
||||
{316, 331, 383, UINT_MAX},
|
||||
};
|
||||
|
||||
static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = {
|
||||
{165, 195, 224, UINT_MAX},
|
||||
{165, 195, 224, UINT_MAX},
|
||||
{165, 195, 224, UINT_MAX},
|
||||
};
|
||||
|
||||
void tegra20_init_speedo_data(void)
|
||||
{
|
||||
u32 reg;
|
||||
u32 val;
|
||||
int i;
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT);
|
||||
|
||||
if (SPEEDO_ID_SELECT_0(tegra_revision))
|
||||
tegra_soc_speedo_id = SPEEDO_ID_0;
|
||||
else if (SPEEDO_ID_SELECT_1(tegra_sku_id))
|
||||
tegra_soc_speedo_id = SPEEDO_ID_1;
|
||||
else
|
||||
tegra_soc_speedo_id = SPEEDO_ID_2;
|
||||
|
||||
val = 0;
|
||||
for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
|
||||
reg = tegra_spare_fuse(i) |
|
||||
tegra_spare_fuse(i + CPU_SPEEDO_REDUND_OFFS);
|
||||
val = (val << 1) | (reg & 0x1);
|
||||
}
|
||||
val = val * SPEEDO_MULT;
|
||||
pr_debug("%s CPU speedo value %u\n", __func__, val);
|
||||
|
||||
for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
|
||||
if (val <= cpu_process_speedos[tegra_soc_speedo_id][i])
|
||||
break;
|
||||
}
|
||||
tegra_cpu_process_id = i;
|
||||
|
||||
val = 0;
|
||||
for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) {
|
||||
reg = tegra_spare_fuse(i) |
|
||||
tegra_spare_fuse(i + CORE_SPEEDO_REDUND_OFFS);
|
||||
val = (val << 1) | (reg & 0x1);
|
||||
}
|
||||
val = val * SPEEDO_MULT;
|
||||
pr_debug("%s Core speedo value %u\n", __func__, val);
|
||||
|
||||
for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
|
||||
if (val <= core_process_speedos[tegra_soc_speedo_id][i])
|
||||
break;
|
||||
}
|
||||
tegra_core_process_id = i;
|
||||
|
||||
pr_info("Tegra20 Soc Speedo ID %d", tegra_soc_speedo_id);
|
||||
}
|
|
@ -25,8 +25,6 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/platform_data/tegra_emc.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "tegra2_emc.h"
|
||||
#include "fuse.h"
|
||||
|
||||
|
|
|
@ -31,10 +31,9 @@
|
|||
|
||||
#include <asm/clkdev.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "fuse.h"
|
||||
#include "iomap.h"
|
||||
#include "tegra_cpu_car.h"
|
||||
|
||||
#define USE_PLL_LOCK_BITS 0
|
||||
|
@ -792,6 +791,112 @@ struct clk_ops tegra30_twd_ops = {
|
|||
.recalc_rate = tegra30_twd_clk_recalc_rate,
|
||||
};
|
||||
|
||||
/* bus clock functions */
|
||||
static int tegra30_bus_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_tegra *c = to_clk_tegra(hw);
|
||||
u32 val = clk_readl(c->reg);
|
||||
|
||||
c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
|
||||
return c->state;
|
||||
}
|
||||
|
||||
static int tegra30_bus_clk_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_tegra *c = to_clk_tegra(hw);
|
||||
u32 val;
|
||||
|
||||
val = clk_readl(c->reg);
|
||||
val &= ~(BUS_CLK_DISABLE << c->reg_shift);
|
||||
clk_writel(val, c->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra30_bus_clk_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_tegra *c = to_clk_tegra(hw);
|
||||
u32 val;
|
||||
|
||||
val = clk_readl(c->reg);
|
||||
val |= BUS_CLK_DISABLE << c->reg_shift;
|
||||
clk_writel(val, c->reg);
|
||||
}
|
||||
|
||||
static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long prate)
|
||||
{
|
||||
struct clk_tegra *c = to_clk_tegra(hw);
|
||||
u32 val = clk_readl(c->reg);
|
||||
u64 rate = prate;
|
||||
|
||||
c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
|
||||
c->mul = 1;
|
||||
|
||||
if (c->mul != 0 && c->div != 0) {
|
||||
rate *= c->mul;
|
||||
rate += c->div - 1; /* round up */
|
||||
do_div(rate, c->div);
|
||||
}
|
||||
return rate;
|
||||
}
|
||||
|
||||
static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_tegra *c = to_clk_tegra(hw);
|
||||
int ret = -EINVAL;
|
||||
u32 val;
|
||||
int i;
|
||||
|
||||
val = clk_readl(c->reg);
|
||||
for (i = 1; i <= 4; i++) {
|
||||
if (rate == parent_rate / i) {
|
||||
val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
|
||||
val |= (i - 1) << c->reg_shift;
|
||||
clk_writel(val, c->reg);
|
||||
c->div = i;
|
||||
c->mul = 1;
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
unsigned long parent_rate = *prate;
|
||||
s64 divider;
|
||||
|
||||
if (rate >= parent_rate)
|
||||
return parent_rate;
|
||||
|
||||
divider = parent_rate;
|
||||
divider += rate - 1;
|
||||
do_div(divider, rate);
|
||||
|
||||
if (divider < 0)
|
||||
return divider;
|
||||
|
||||
if (divider > 4)
|
||||
divider = 4;
|
||||
do_div(parent_rate, divider);
|
||||
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
struct clk_ops tegra30_bus_ops = {
|
||||
.is_enabled = tegra30_bus_clk_is_enabled,
|
||||
.enable = tegra30_bus_clk_enable,
|
||||
.disable = tegra30_bus_clk_disable,
|
||||
.set_rate = tegra30_bus_clk_set_rate,
|
||||
.round_rate = tegra30_bus_clk_round_rate,
|
||||
.recalc_rate = tegra30_bus_clk_recalc_rate,
|
||||
};
|
||||
|
||||
/* Blink output functions */
|
||||
static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
|
|
|
@ -34,6 +34,7 @@ extern struct clk_ops tegra_clk_out_ops;
|
|||
extern struct clk_ops tegra30_super_ops;
|
||||
extern struct clk_ops tegra30_blink_clk_ops;
|
||||
extern struct clk_ops tegra30_twd_ops;
|
||||
extern struct clk_ops tegra30_bus_ops;
|
||||
extern struct clk_ops tegra30_periph_clk_ops;
|
||||
extern struct clk_ops tegra30_dsib_clk_ops;
|
||||
extern struct clk_ops tegra_nand_clk_ops;
|
||||
|
|
|
@ -711,6 +711,50 @@ static struct clk tegra_clk_sclk = {
|
|||
.num_parents = ARRAY_SIZE(mux_sclk),
|
||||
};
|
||||
|
||||
static const char *tegra_hclk_parent_names[] = {
|
||||
"tegra_sclk",
|
||||
};
|
||||
|
||||
static struct clk *tegra_hclk_parents[] = {
|
||||
&tegra_clk_sclk,
|
||||
};
|
||||
|
||||
static struct clk tegra_hclk;
|
||||
static struct clk_tegra tegra_hclk_hw = {
|
||||
.hw = {
|
||||
.clk = &tegra_hclk,
|
||||
},
|
||||
.flags = DIV_BUS,
|
||||
.reg = 0x30,
|
||||
.reg_shift = 4,
|
||||
.max_rate = 378000000,
|
||||
.min_rate = 12000000,
|
||||
};
|
||||
DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names,
|
||||
tegra_hclk_parents, &tegra_clk_sclk);
|
||||
|
||||
static const char *tegra_pclk_parent_names[] = {
|
||||
"tegra_hclk",
|
||||
};
|
||||
|
||||
static struct clk *tegra_pclk_parents[] = {
|
||||
&tegra_hclk,
|
||||
};
|
||||
|
||||
static struct clk tegra_pclk;
|
||||
static struct clk_tegra tegra_pclk_hw = {
|
||||
.hw = {
|
||||
.clk = &tegra_pclk,
|
||||
},
|
||||
.flags = DIV_BUS,
|
||||
.reg = 0x30,
|
||||
.reg_shift = 0,
|
||||
.max_rate = 167000000,
|
||||
.min_rate = 12000000,
|
||||
};
|
||||
DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names,
|
||||
tegra_pclk_parents, &tegra_hclk);
|
||||
|
||||
static const char *mux_blink[] = {
|
||||
"clk_32k",
|
||||
};
|
||||
|
@ -1254,8 +1298,6 @@ struct clk_duplicate tegra_clk_duplicates[] = {
|
|||
CLK_DUPLICATE("usbd", "utmip-pad", NULL),
|
||||
CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
|
||||
CLK_DUPLICATE("usbd", "tegra-otg", NULL),
|
||||
CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
|
||||
CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
|
||||
CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
|
||||
CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
|
||||
CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
|
||||
|
@ -1293,6 +1335,9 @@ struct clk_duplicate tegra_clk_duplicates[] = {
|
|||
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
|
||||
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
|
||||
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
|
||||
CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
|
||||
CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
|
||||
CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"),
|
||||
};
|
||||
|
||||
struct clk *tegra_ptr_clks[] = {
|
||||
|
@ -1325,6 +1370,8 @@ struct clk *tegra_ptr_clks[] = {
|
|||
&tegra_cml1,
|
||||
&tegra_pciex,
|
||||
&tegra_clk_sclk,
|
||||
&tegra_hclk,
|
||||
&tegra_pclk,
|
||||
&tegra_clk_blink,
|
||||
&tegra30_clk_twd,
|
||||
};
|
||||
|
|
292
arch/arm/mach-tegra/tegra30_speedo.c
Normal file
292
arch/arm/mach-tegra/tegra30_speedo.c
Normal file
|
@ -0,0 +1,292 @@
|
|||
/*
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/bug.h>
|
||||
|
||||
#include "fuse.h"
|
||||
|
||||
#define CORE_PROCESS_CORNERS_NUM 1
|
||||
#define CPU_PROCESS_CORNERS_NUM 6
|
||||
|
||||
#define FUSE_SPEEDO_CALIB_0 0x114
|
||||
#define FUSE_PACKAGE_INFO 0X1FC
|
||||
#define FUSE_TEST_PROG_VER 0X128
|
||||
|
||||
#define G_SPEEDO_BIT_MINUS1 58
|
||||
#define G_SPEEDO_BIT_MINUS1_R 59
|
||||
#define G_SPEEDO_BIT_MINUS2 60
|
||||
#define G_SPEEDO_BIT_MINUS2_R 61
|
||||
#define LP_SPEEDO_BIT_MINUS1 62
|
||||
#define LP_SPEEDO_BIT_MINUS1_R 63
|
||||
#define LP_SPEEDO_BIT_MINUS2 64
|
||||
#define LP_SPEEDO_BIT_MINUS2_R 65
|
||||
|
||||
enum {
|
||||
THRESHOLD_INDEX_0,
|
||||
THRESHOLD_INDEX_1,
|
||||
THRESHOLD_INDEX_2,
|
||||
THRESHOLD_INDEX_3,
|
||||
THRESHOLD_INDEX_4,
|
||||
THRESHOLD_INDEX_5,
|
||||
THRESHOLD_INDEX_6,
|
||||
THRESHOLD_INDEX_7,
|
||||
THRESHOLD_INDEX_8,
|
||||
THRESHOLD_INDEX_9,
|
||||
THRESHOLD_INDEX_10,
|
||||
THRESHOLD_INDEX_11,
|
||||
THRESHOLD_INDEX_COUNT,
|
||||
};
|
||||
|
||||
static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
|
||||
{180},
|
||||
{170},
|
||||
{195},
|
||||
{180},
|
||||
{168},
|
||||
{192},
|
||||
{180},
|
||||
{170},
|
||||
{195},
|
||||
{180},
|
||||
{180},
|
||||
{180},
|
||||
};
|
||||
|
||||
static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
|
||||
{306, 338, 360, 376, UINT_MAX},
|
||||
{295, 336, 358, 375, UINT_MAX},
|
||||
{325, 325, 358, 375, UINT_MAX},
|
||||
{325, 325, 358, 375, UINT_MAX},
|
||||
{292, 324, 348, 364, UINT_MAX},
|
||||
{324, 324, 348, 364, UINT_MAX},
|
||||
{324, 324, 348, 364, UINT_MAX},
|
||||
{295, 336, 358, 375, UINT_MAX},
|
||||
{358, 358, 358, 358, 397, UINT_MAX},
|
||||
{364, 364, 364, 364, 397, UINT_MAX},
|
||||
{295, 336, 358, 375, 391, UINT_MAX},
|
||||
{295, 336, 358, 375, 391, UINT_MAX},
|
||||
};
|
||||
|
||||
static int threshold_index;
|
||||
static int package_id;
|
||||
|
||||
static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
|
||||
{
|
||||
u32 reg;
|
||||
int ate_ver;
|
||||
int bit_minus1;
|
||||
int bit_minus2;
|
||||
|
||||
reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0);
|
||||
|
||||
*speedo_lp = (reg & 0xFFFF) * 4;
|
||||
*speedo_g = ((reg >> 16) & 0xFFFF) * 4;
|
||||
|
||||
ate_ver = tegra_fuse_readl(FUSE_TEST_PROG_VER);
|
||||
pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10);
|
||||
|
||||
if (ate_ver >= 26) {
|
||||
bit_minus1 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1);
|
||||
bit_minus1 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
|
||||
bit_minus2 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2);
|
||||
bit_minus2 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
|
||||
*speedo_lp |= (bit_minus1 << 1) | bit_minus2;
|
||||
|
||||
bit_minus1 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS1);
|
||||
bit_minus1 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
|
||||
bit_minus2 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS2);
|
||||
bit_minus2 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
|
||||
*speedo_g |= (bit_minus1 << 1) | bit_minus2;
|
||||
} else {
|
||||
*speedo_lp |= 0x3;
|
||||
*speedo_g |= 0x3;
|
||||
}
|
||||
}
|
||||
|
||||
static void rev_sku_to_speedo_ids(int rev, int sku)
|
||||
{
|
||||
switch (rev) {
|
||||
case TEGRA_REVISION_A01:
|
||||
tegra_cpu_speedo_id = 0;
|
||||
tegra_soc_speedo_id = 0;
|
||||
threshold_index = THRESHOLD_INDEX_0;
|
||||
break;
|
||||
case TEGRA_REVISION_A02:
|
||||
case TEGRA_REVISION_A03:
|
||||
switch (sku) {
|
||||
case 0x87:
|
||||
case 0x82:
|
||||
tegra_cpu_speedo_id = 1;
|
||||
tegra_soc_speedo_id = 1;
|
||||
threshold_index = THRESHOLD_INDEX_1;
|
||||
break;
|
||||
case 0x81:
|
||||
switch (package_id) {
|
||||
case 1:
|
||||
tegra_cpu_speedo_id = 2;
|
||||
tegra_soc_speedo_id = 2;
|
||||
threshold_index = THRESHOLD_INDEX_2;
|
||||
break;
|
||||
case 2:
|
||||
tegra_cpu_speedo_id = 4;
|
||||
tegra_soc_speedo_id = 1;
|
||||
threshold_index = THRESHOLD_INDEX_7;
|
||||
break;
|
||||
default:
|
||||
pr_err("Tegra30: Unknown pkg %d\n", package_id);
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0x80:
|
||||
switch (package_id) {
|
||||
case 1:
|
||||
tegra_cpu_speedo_id = 5;
|
||||
tegra_soc_speedo_id = 2;
|
||||
threshold_index = THRESHOLD_INDEX_8;
|
||||
break;
|
||||
case 2:
|
||||
tegra_cpu_speedo_id = 6;
|
||||
tegra_soc_speedo_id = 2;
|
||||
threshold_index = THRESHOLD_INDEX_9;
|
||||
break;
|
||||
default:
|
||||
pr_err("Tegra30: Unknown pkg %d\n", package_id);
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0x83:
|
||||
switch (package_id) {
|
||||
case 1:
|
||||
tegra_cpu_speedo_id = 7;
|
||||
tegra_soc_speedo_id = 1;
|
||||
threshold_index = THRESHOLD_INDEX_10;
|
||||
break;
|
||||
case 2:
|
||||
tegra_cpu_speedo_id = 3;
|
||||
tegra_soc_speedo_id = 2;
|
||||
threshold_index = THRESHOLD_INDEX_3;
|
||||
break;
|
||||
default:
|
||||
pr_err("Tegra30: Unknown pkg %d\n", package_id);
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0x8F:
|
||||
tegra_cpu_speedo_id = 8;
|
||||
tegra_soc_speedo_id = 1;
|
||||
threshold_index = THRESHOLD_INDEX_11;
|
||||
break;
|
||||
case 0x08:
|
||||
tegra_cpu_speedo_id = 1;
|
||||
tegra_soc_speedo_id = 1;
|
||||
threshold_index = THRESHOLD_INDEX_4;
|
||||
break;
|
||||
case 0x02:
|
||||
tegra_cpu_speedo_id = 2;
|
||||
tegra_soc_speedo_id = 2;
|
||||
threshold_index = THRESHOLD_INDEX_5;
|
||||
break;
|
||||
case 0x04:
|
||||
tegra_cpu_speedo_id = 3;
|
||||
tegra_soc_speedo_id = 2;
|
||||
threshold_index = THRESHOLD_INDEX_6;
|
||||
break;
|
||||
case 0:
|
||||
switch (package_id) {
|
||||
case 1:
|
||||
tegra_cpu_speedo_id = 2;
|
||||
tegra_soc_speedo_id = 2;
|
||||
threshold_index = THRESHOLD_INDEX_2;
|
||||
break;
|
||||
case 2:
|
||||
tegra_cpu_speedo_id = 3;
|
||||
tegra_soc_speedo_id = 2;
|
||||
threshold_index = THRESHOLD_INDEX_3;
|
||||
break;
|
||||
default:
|
||||
pr_err("Tegra30: Unknown pkg %d\n", package_id);
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
pr_warn("Tegra30: Unknown SKU %d\n", sku);
|
||||
tegra_cpu_speedo_id = 0;
|
||||
tegra_soc_speedo_id = 0;
|
||||
threshold_index = THRESHOLD_INDEX_0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
pr_warn("Tegra30: Unknown chip rev %d\n", rev);
|
||||
tegra_cpu_speedo_id = 0;
|
||||
tegra_soc_speedo_id = 0;
|
||||
threshold_index = THRESHOLD_INDEX_0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void tegra30_init_speedo_data(void)
|
||||
{
|
||||
u32 cpu_speedo_val;
|
||||
u32 core_speedo_val;
|
||||
int i;
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
|
||||
THRESHOLD_INDEX_COUNT);
|
||||
|
||||
package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
|
||||
|
||||
rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id);
|
||||
fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
|
||||
pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
|
||||
pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
|
||||
|
||||
for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) {
|
||||
if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
|
||||
break;
|
||||
}
|
||||
tegra_cpu_process_id = i - 1;
|
||||
|
||||
if (tegra_cpu_process_id == -1) {
|
||||
pr_warn("Tegra30: CPU speedo value %3d out of range",
|
||||
cpu_speedo_val);
|
||||
tegra_cpu_process_id = 0;
|
||||
tegra_cpu_speedo_id = 1;
|
||||
}
|
||||
|
||||
for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) {
|
||||
if (core_speedo_val < core_process_speedos[threshold_index][i])
|
||||
break;
|
||||
}
|
||||
tegra_core_process_id = i - 1;
|
||||
|
||||
if (tegra_core_process_id == -1) {
|
||||
pr_warn("Tegra30: CORE speedo value %3d out of range",
|
||||
core_speedo_val);
|
||||
tegra_core_process_id = 0;
|
||||
tegra_soc_speedo_id = 1;
|
||||
}
|
||||
|
||||
pr_info("Tegra30: CPU Speedo ID %d, Soc Speedo ID %d",
|
||||
tegra_cpu_speedo_id, tegra_soc_speedo_id);
|
||||
}
|
|
@ -26,16 +26,14 @@
|
|||
#include <linux/clocksource.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/smp_twd.h>
|
||||
#include <asm/sched_clock.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "clock.h"
|
||||
|
||||
#define RTC_SECONDS 0x08
|
||||
#define RTC_SHADOW_SECONDS 0x0c
|
||||
|
@ -53,8 +51,8 @@
|
|||
#define TIMER_PTV 0x0
|
||||
#define TIMER_PCR 0x4
|
||||
|
||||
static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
|
||||
static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);
|
||||
static void __iomem *timer_reg_base;
|
||||
static void __iomem *rtc_base;
|
||||
|
||||
static struct timespec persistent_ts;
|
||||
static u64 persistent_ms, last_persistent_ms;
|
||||
|
@ -158,40 +156,66 @@ static struct irqaction tegra_timer_irq = {
|
|||
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
|
||||
.handler = tegra_timer_interrupt,
|
||||
.dev_id = &tegra_clockevent,
|
||||
.irq = INT_TMR3,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_HAVE_ARM_TWD
|
||||
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
|
||||
TEGRA_ARM_PERIF_BASE + 0x600,
|
||||
IRQ_LOCALTIMER);
|
||||
static const struct of_device_id timer_match[] __initconst = {
|
||||
{ .compatible = "nvidia,tegra20-timer" },
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init tegra_twd_init(void)
|
||||
{
|
||||
int err = twd_local_timer_register(&twd_local_timer);
|
||||
if (err)
|
||||
pr_err("twd_local_timer_register failed %d\n", err);
|
||||
}
|
||||
#else
|
||||
#define tegra_twd_init() do {} while(0)
|
||||
#endif
|
||||
static const struct of_device_id rtc_match[] __initconst = {
|
||||
{ .compatible = "nvidia,tegra20-rtc" },
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init tegra_init_timer(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct clk *clk;
|
||||
unsigned long rate;
|
||||
int ret;
|
||||
|
||||
np = of_find_matching_node(NULL, timer_match);
|
||||
if (!np) {
|
||||
pr_err("Failed to find timer DT node\n");
|
||||
BUG();
|
||||
}
|
||||
|
||||
timer_reg_base = of_iomap(np, 0);
|
||||
if (!timer_reg_base) {
|
||||
pr_err("Can't map timer registers");
|
||||
BUG();
|
||||
}
|
||||
|
||||
tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
|
||||
if (tegra_timer_irq.irq <= 0) {
|
||||
pr_err("Failed to map timer IRQ\n");
|
||||
BUG();
|
||||
}
|
||||
|
||||
clk = clk_get_sys("timer", NULL);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_warn("Unable to get timer clock."
|
||||
" Assuming 12Mhz input clock.\n");
|
||||
pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
|
||||
rate = 12000000;
|
||||
} else {
|
||||
clk_prepare_enable(clk);
|
||||
rate = clk_get_rate(clk);
|
||||
}
|
||||
|
||||
of_node_put(np);
|
||||
|
||||
np = of_find_matching_node(NULL, rtc_match);
|
||||
if (!np) {
|
||||
pr_err("Failed to find RTC DT node\n");
|
||||
BUG();
|
||||
}
|
||||
|
||||
rtc_base = of_iomap(np, 0);
|
||||
if (!rtc_base) {
|
||||
pr_err("Can't map RTC registers");
|
||||
BUG();
|
||||
}
|
||||
|
||||
/*
|
||||
* rtc registers are used by read_persistent_clock, keep the rtc clock
|
||||
* enabled
|
||||
|
@ -202,6 +226,8 @@ static void __init tegra_init_timer(void)
|
|||
else
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
of_node_put(np);
|
||||
|
||||
switch (rate) {
|
||||
case 12000000:
|
||||
timer_writel(0x000b, TIMERUS_USEC_CFG);
|
||||
|
@ -223,13 +249,13 @@ static void __init tegra_init_timer(void)
|
|||
|
||||
if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
|
||||
"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
|
||||
printk(KERN_ERR "Failed to register clocksource\n");
|
||||
pr_err("Failed to register clocksource\n");
|
||||
BUG();
|
||||
}
|
||||
|
||||
ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
|
||||
pr_err("Failed to register timer IRQ: %d\n", ret);
|
||||
BUG();
|
||||
}
|
||||
|
||||
|
@ -241,7 +267,9 @@ static void __init tegra_init_timer(void)
|
|||
tegra_clockevent.cpumask = cpu_all_mask;
|
||||
tegra_clockevent.irq = tegra_timer_irq.irq;
|
||||
clockevents_register_device(&tegra_clockevent);
|
||||
tegra_twd_init();
|
||||
#ifdef CONFIG_HAVE_ARM_TWD
|
||||
twd_local_timer_of_register();
|
||||
#endif
|
||||
register_persistent_clock(NULL, tegra_read_persistent_clock);
|
||||
}
|
||||
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/tegra-ahb.h>
|
||||
|
||||
#define DRV_NAME "tegra-ahb"
|
||||
|
||||
|
|
|
@ -41,8 +41,6 @@
|
|||
#include <linux/completion.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#include <mach/clk.h>
|
||||
|
||||
#include <crypto/scatterwalk.h>
|
||||
#include <crypto/aes.h>
|
||||
#include <crypto/internal/rng.h>
|
||||
|
|
|
@ -34,13 +34,11 @@
|
|||
#include <linux/of_iommu.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/tegra-ahb.h>
|
||||
|
||||
#include <asm/page.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#include <mach/iomap.h>
|
||||
#include <mach/tegra-ahb.h>
|
||||
|
||||
enum smmu_hwgrp {
|
||||
HWGRP_AFI,
|
||||
HWGRP_AVPC,
|
||||
|
|
|
@ -39,7 +39,6 @@
|
|||
#include <linux/workqueue.h>
|
||||
|
||||
#include <mach/clk.h>
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#include "nvec.h"
|
||||
|
||||
|
|
|
@ -28,7 +28,10 @@
|
|||
#include <linux/pm_runtime.h>
|
||||
|
||||
#include <linux/usb/tegra_usb_phy.h>
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#define TEGRA_USB_BASE 0xC5000000
|
||||
#define TEGRA_USB2_BASE 0xC5004000
|
||||
#define TEGRA_USB3_BASE 0xC5008000
|
||||
|
||||
#define TEGRA_USB_DMA_ALIGN 32
|
||||
|
||||
|
|
|
@ -29,7 +29,9 @@
|
|||
#include <linux/usb/ulpi.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <linux/usb/tegra_usb_phy.h>
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#define TEGRA_USB_BASE 0xC5000000
|
||||
#define TEGRA_USB_SIZE SZ_16K
|
||||
|
||||
#define ULPI_VIEWPORT 0x170
|
||||
|
||||
|
|
|
@ -11,9 +11,9 @@
|
|||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_AHB_H__
|
||||
#define __MACH_TEGRA_AHB_H__
|
||||
#ifndef __LINUX_AHB_H__
|
||||
#define __LINUX_AHB_H__
|
||||
|
||||
extern int tegra_ahb_enable_smmu(struct device_node *ahb);
|
||||
|
||||
#endif /* __MACH_TEGRA_AHB_H__ */
|
||||
#endif /* __LINUX_AHB_H__ */
|
|
@ -26,7 +26,6 @@
|
|||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
#include <mach/clk.h>
|
||||
#include <mach/dma.h>
|
||||
#include <sound/soc.h>
|
||||
#include "tegra30_ahub.h"
|
||||
|
||||
|
|
|
@ -31,8 +31,6 @@
|
|||
#ifndef __TEGRA_PCM_H__
|
||||
#define __TEGRA_PCM_H__
|
||||
|
||||
#include <mach/dma.h>
|
||||
|
||||
struct tegra_pcm_dma_params {
|
||||
unsigned long addr;
|
||||
unsigned long wrap;
|
||||
|
|
Loading…
Reference in a new issue