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drm/amdgpu: define soc15_ras_field_entry for reuse
The struct soc15_ras_field_entry will be reused by other IPs, such as mmhub and gc v2: rename ras_subblock_regs to gc_ras_fields_vg20, because the future asic maybe have a different table. Signed-off-by: Dennis Li <dennis.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d98a07aea6
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2 changed files with 23 additions and 23 deletions
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@ -131,18 +131,6 @@ MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
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#define mmTCP_CHAN_STEER_5_ARCT 0x0b0c
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#define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0
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struct ras_gfx_subblock_reg {
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const char *name;
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uint32_t hwip;
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uint32_t inst;
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uint32_t seg;
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uint32_t reg_offset;
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uint32_t sec_count_mask;
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uint32_t sec_count_shift;
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uint32_t ded_count_mask;
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uint32_t ded_count_shift;
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};
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enum ta_ras_gfx_subblock {
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/*CPC*/
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TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
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@ -5484,7 +5472,7 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
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}
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static const struct ras_gfx_subblock_reg ras_subblock_regs[] = {
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static const struct soc15_ras_field_entry gc_ras_fields_vg20[] = {
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{ "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
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SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
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SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT)
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@ -6143,29 +6131,29 @@ static int __get_ras_error_count(const struct soc15_reg_entry *reg,
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uint32_t i;
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uint32_t sec_cnt, ded_cnt;
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for (i = 0; i < ARRAY_SIZE(ras_subblock_regs); i++) {
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if(ras_subblock_regs[i].reg_offset != reg->reg_offset ||
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ras_subblock_regs[i].seg != reg->seg ||
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ras_subblock_regs[i].inst != reg->inst)
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for (i = 0; i < ARRAY_SIZE(gc_ras_fields_vg20); i++) {
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if(gc_ras_fields_vg20[i].reg_offset != reg->reg_offset ||
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gc_ras_fields_vg20[i].seg != reg->seg ||
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gc_ras_fields_vg20[i].inst != reg->inst)
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continue;
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sec_cnt = (value &
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ras_subblock_regs[i].sec_count_mask) >>
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ras_subblock_regs[i].sec_count_shift;
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gc_ras_fields_vg20[i].sec_count_mask) >>
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gc_ras_fields_vg20[i].sec_count_shift;
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if (sec_cnt) {
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DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
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ras_subblock_regs[i].name,
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gc_ras_fields_vg20[i].name,
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se_id, inst_id,
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sec_cnt);
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*sec_count += sec_cnt;
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}
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ded_cnt = (value &
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ras_subblock_regs[i].ded_count_mask) >>
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ras_subblock_regs[i].ded_count_shift;
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gc_ras_fields_vg20[i].ded_count_mask) >>
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gc_ras_fields_vg20[i].ded_count_shift;
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if (ded_cnt) {
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DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",
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ras_subblock_regs[i].name,
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gc_ras_fields_vg20[i].name,
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se_id, inst_id,
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ded_cnt);
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*ded_count += ded_cnt;
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@ -60,6 +60,18 @@ struct soc15_allowed_register_entry {
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bool grbm_indexed;
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};
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struct soc15_ras_field_entry {
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const char *name;
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uint32_t hwip;
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uint32_t inst;
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uint32_t seg;
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uint32_t reg_offset;
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uint32_t sec_count_mask;
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uint32_t sec_count_shift;
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uint32_t ded_count_mask;
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uint32_t ded_count_shift;
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};
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#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
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#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
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