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crypto: hisilicon/qm - add a function to set qm algs

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[ Upstream commit f76f0d7f20 ]

Extract a public function to set qm algs and remove
the similar code for setting qm algs in each module.

Signed-off-by: Wenkai Lin <linwenkai6@hisilicon.com>
Signed-off-by: Hao Fang <fanghao11@huawei.com>
Signed-off-by: Zhiqi Song <songzhiqi1@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Stable-dep-of: cf8b5156bb ("crypto: hisilicon/hpre - save capability registers in probe process")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Wenkai Lin 2023-12-02 17:17:18 +08:00 committed by Greg Kroah-Hartman
parent 11d7a33905
commit 4705731fc5
5 changed files with 62 additions and 120 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

42
drivers/crypto/hisilicon/hpre/hpre_main.c
View file

@ -118,8 +118,6 @@
#define HPRE_DFX_COMMON2_LEN 0xE
#define HPRE_DFX_CORE_LEN 0x43
#define HPRE_DEV_ALG_MAX_LEN 256
static const char hpre_name[] = "hisi_hpre";
static struct dentry *hpre_debugfs_root;
static const struct pci_device_id hpre_dev_ids[] = {
@ -135,12 +133,7 @@ struct hpre_hw_error {
const char *msg;
};
struct hpre_dev_alg {
u32 alg_msk;
const char *alg;
};
static const struct hpre_dev_alg hpre_dev_algs[] = {
static const struct qm_dev_alg hpre_dev_algs[] = {
{
.alg_msk = BIT(0),
.alg = "rsa\n"
@ -359,35 +352,6 @@ bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg)
return false;
}
static int hpre_set_qm_algs(struct hisi_qm *qm)
{
struct device *dev = &qm->pdev->dev;
char *algs, *ptr;
u32 alg_msk;
int i;
if (!qm->use_sva)
return 0;
algs = devm_kzalloc(dev, HPRE_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);
if (!algs)
return -ENOMEM;
alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver);
for (i = 0; i < ARRAY_SIZE(hpre_dev_algs); i++)
if (alg_msk & hpre_dev_algs[i].alg_msk)
strcat(algs, hpre_dev_algs[i].alg);
ptr = strrchr(algs, '\n');
if (ptr)
*ptr = '\0';
qm->uacce->algs = algs;
return 0;
}
static int hpre_diff_regs_show(struct seq_file *s, void *unused)
{
struct hisi_qm *qm = s->private;
@ -1138,6 +1102,7 @@ static void hpre_debugfs_exit(struct hisi_qm *qm)
static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
{
u64 alg_msk;
int ret;
if (pdev->revision == QM_HW_V1) {
@ -1168,7 +1133,8 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
return ret;
}
ret = hpre_set_qm_algs(qm);
alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver);
ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs));
if (ret) {
pci_err(pdev, "Failed to set hpre algs!\n");
hisi_qm_uninit(qm);

36
drivers/crypto/hisilicon/qm.c
View file

@ -237,6 +237,8 @@
#define QM_QOS_MAX_CIR_S 11
#define QM_AUTOSUSPEND_DELAY 3000
#define QM_DEV_ALG_MAX_LEN 256
#define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \
(((hop_num) << QM_CQ_HOP_NUM_SHIFT) | \
((pg_sz) << QM_CQ_PAGE_SIZE_SHIFT) | \
@ -795,6 +797,40 @@ static void qm_get_xqc_depth(struct hisi_qm *qm, u16 *low_bits,
*high_bits = (depth >> QM_XQ_DEPTH_SHIFT) & QM_XQ_DEPTH_MASK;
}
int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,
u32 dev_algs_size)
{
struct device *dev = &qm->pdev->dev;
char *algs, *ptr;
int i;
if (!qm->uacce)
return 0;
if (dev_algs_size >= QM_DEV_ALG_MAX_LEN) {
dev_err(dev, "algs size %u is equal or larger than %d.\n",
dev_algs_size, QM_DEV_ALG_MAX_LEN);
return -EINVAL;
}
algs = devm_kzalloc(dev, QM_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);
if (!algs)
return -ENOMEM;
for (i = 0; i < dev_algs_size; i++)
if (alg_msk & dev_algs[i].alg_msk)
strcat(algs, dev_algs[i].alg);
ptr = strrchr(algs, '\n');
if (ptr) {
*ptr = '\0';
qm->uacce->algs = algs;
}
return 0;
}
EXPORT_SYMBOL_GPL(hisi_qm_set_algs);
static u32 qm_get_irq_num(struct hisi_qm *qm)
{
if (qm->fun_type == QM_HW_PF)

47
drivers/crypto/hisilicon/sec2/sec_main.c
View file

@ -121,7 +121,6 @@
GENMASK_ULL(42, 25))
#define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \
GENMASK_ULL(45, 43))
#define SEC_DEV_ALG_MAX_LEN 256
struct sec_hw_error {
u32 int_msk;
@ -133,11 +132,6 @@ struct sec_dfx_item {
u32 offset;
};
struct sec_dev_alg {
u64 alg_msk;
const char *algs;
};
static const char sec_name[] = "hisi_sec2";
static struct dentry *sec_debugfs_root;
@ -174,15 +168,15 @@ static const struct hisi_qm_cap_info sec_basic_info[] = {
{SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
};
static const struct sec_dev_alg sec_dev_algs[] = { {
static const struct qm_dev_alg sec_dev_algs[] = { {
.alg_msk = SEC_CIPHER_BITMAP,
.algs = "cipher\n",
.alg = "cipher\n",
}, {
.alg_msk = SEC_DIGEST_BITMAP,
.algs = "digest\n",
.alg = "digest\n",
}, {
.alg_msk = SEC_AEAD_BITMAP,
.algs = "aead\n",
.alg = "aead\n",
},
};
@ -1079,37 +1073,9 @@ static int sec_pf_probe_init(struct sec_dev *sec)
return ret;
}
static int sec_set_qm_algs(struct hisi_qm *qm)
{
struct device *dev = &qm->pdev->dev;
char *algs, *ptr;
u64 alg_mask;
int i;
if (!qm->use_sva)
return 0;
algs = devm_kzalloc(dev, SEC_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);
if (!algs)
return -ENOMEM;
alg_mask = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW);
for (i = 0; i < ARRAY_SIZE(sec_dev_algs); i++)
if (alg_mask & sec_dev_algs[i].alg_msk)
strcat(algs, sec_dev_algs[i].algs);
ptr = strrchr(algs, '\n');
if (ptr)
*ptr = '\0';
qm->uacce->algs = algs;
return 0;
}
static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
{
u64 alg_msk;
int ret;
qm->pdev = pdev;
@ -1144,7 +1110,8 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
return ret;
}
ret = sec_set_qm_algs(qm);
alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW);
ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs));
if (ret) {
pci_err(qm->pdev, "Failed to set sec algs!\n");
hisi_qm_uninit(qm);

49
drivers/crypto/hisilicon/zip/zip_main.c
View file

@ -74,7 +74,6 @@
#define HZIP_AXI_SHUTDOWN_ENABLE BIT(14)
#define HZIP_WR_PORT BIT(11)
#define HZIP_DEV_ALG_MAX_LEN 256
#define HZIP_ALG_ZLIB_BIT GENMASK(1, 0)
#define HZIP_ALG_GZIP_BIT GENMASK(3, 2)
#define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4)
@ -128,23 +127,18 @@ struct zip_dfx_item {
u32 offset;
};
struct zip_dev_alg {
u32 alg_msk;
const char *algs;
};
static const struct zip_dev_alg zip_dev_algs[] = { {
static const struct qm_dev_alg zip_dev_algs[] = { {
.alg_msk = HZIP_ALG_ZLIB_BIT,
.algs = "zlib\n",
.alg = "zlib\n",
}, {
.alg_msk = HZIP_ALG_GZIP_BIT,
.algs = "gzip\n",
.alg = "gzip\n",
}, {
.alg_msk = HZIP_ALG_DEFLATE_BIT,
.algs = "deflate\n",
.alg = "deflate\n",
}, {
.alg_msk = HZIP_ALG_LZ77_BIT,
.algs = "lz77_zstd\n",
.alg = "lz77_zstd\n",
},
};
@ -478,35 +472,6 @@ static int hisi_zip_set_high_perf(struct hisi_qm *qm)
return ret;
}
static int hisi_zip_set_qm_algs(struct hisi_qm *qm)
{
struct device *dev = &qm->pdev->dev;
char *algs, *ptr;
u32 alg_mask;
int i;
if (!qm->use_sva)
return 0;
algs = devm_kzalloc(dev, HZIP_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);
if (!algs)
return -ENOMEM;
alg_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver);
for (i = 0; i < ARRAY_SIZE(zip_dev_algs); i++)
if (alg_mask & zip_dev_algs[i].alg_msk)
strcat(algs, zip_dev_algs[i].algs);
ptr = strrchr(algs, '\n');
if (ptr)
*ptr = '\0';
qm->uacce->algs = algs;
return 0;
}
static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm)
{
u32 val;
@ -1193,6 +1158,7 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
{
u64 alg_msk;
int ret;
qm->pdev = pdev;
@ -1228,7 +1194,8 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
return ret;
}
ret = hisi_zip_set_qm_algs(qm);
alg_msk = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver);
ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs));
if (ret) {
pci_err(qm->pdev, "Failed to set zip algs!\n");
hisi_qm_uninit(qm);

8
include/linux/hisi_acc_qm.h
View file

@ -161,6 +161,11 @@ enum qm_cap_bits {
QM_SUPPORT_RPM,
};
struct qm_dev_alg {
u64 alg_msk;
const char *alg;
};
struct dfx_diff_registers {
u32 *regs;
u32 reg_offset;
@ -347,7 +352,6 @@ struct hisi_qm {
struct work_struct rst_work;
struct work_struct cmd_process;
const char *algs;
bool use_sva;
bool is_frozen;
@ -533,6 +537,8 @@ void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);
u32 hisi_qm_get_hw_info(struct hisi_qm *qm,
const struct hisi_qm_cap_info *info_table,
u32 index, bool is_read);
int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,
u32 dev_algs_size);
/* Used by VFIO ACC live migration driver */
struct pci_driver *hisi_sec_get_pf_driver(void);