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b43: HT-PHY: rename AFE defines
It you take a look at N-PHY analog switch function it touches every core on the chipset. It seems HT-PHY does they same, it just has 3 cores instead of 2 (which make sense since BCM4331 is 3x3). Rename AFE defines to include core id. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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parent
1a2780e0f3
commit
476069224d
2 changed files with 25 additions and 25 deletions
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@ -176,10 +176,10 @@ static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
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{
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u8 i;
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const u16 ctl_regs[3][2] = {
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{ B43_PHY_HT_AFE_CTL1, B43_PHY_HT_AFE_CTL2 },
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{ B43_PHY_HT_AFE_CTL3, B43_PHY_HT_AFE_CTL4 },
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{ B43_PHY_HT_AFE_CTL5, B43_PHY_HT_AFE_CTL6},
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static const u16 ctl_regs[3][2] = {
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{ B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
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{ B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
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{ B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
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};
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for (i = 0; i < 3; i++) {
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@ -362,9 +362,9 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
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b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0);
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b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
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b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
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b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
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b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
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b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
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@ -511,19 +511,19 @@ static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
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static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
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{
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if (on) {
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00cd);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x0000);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00cd);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x0000);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00cd);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x0000);
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b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
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b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
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b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
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b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
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b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
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b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
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} else {
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x07ff);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00fd);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x07ff);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00fd);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x07ff);
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b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00fd);
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b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
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b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
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b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
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b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
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b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
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b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
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}
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}
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@ -36,12 +36,12 @@
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#define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010)
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#define B43_PHY_HT_AFE_CTL1 B43_PHY_EXTG(0x110)
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#define B43_PHY_HT_AFE_CTL2 B43_PHY_EXTG(0x111)
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#define B43_PHY_HT_AFE_CTL3 B43_PHY_EXTG(0x114)
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#define B43_PHY_HT_AFE_CTL4 B43_PHY_EXTG(0x115)
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#define B43_PHY_HT_AFE_CTL5 B43_PHY_EXTG(0x118)
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#define B43_PHY_HT_AFE_CTL6 B43_PHY_EXTG(0x119)
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#define B43_PHY_HT_AFE_C1_OVER B43_PHY_EXTG(0x110)
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#define B43_PHY_HT_AFE_C1 B43_PHY_EXTG(0x111)
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#define B43_PHY_HT_AFE_C2_OVER B43_PHY_EXTG(0x114)
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#define B43_PHY_HT_AFE_C2 B43_PHY_EXTG(0x115)
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#define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118)
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#define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119)
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/* Values for PHY registers used on channel switching */
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