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ARM: cache-v7: shift CLIDR to extract appropriate field before masking
Rather than have code which masks and then shifts, such as: mrc p15, 1, r0, c0, c0, 1 ALT_SMP(ands r3, r0, #7 << 21) ALT_UP( ands r3, r0, #7 << 27) ALT_SMP(mov r3, r3, lsr #20) ALT_UP( mov r3, r3, lsr #26) re-arrange this as a shift and then mask. The masking is the same for each field which we want to extract, so this allows the mask to be shared amongst code paths: mrc p15, 1, r0, c0, c0, 1 ALT_SMP(mov r3, r0, lsr #20) ALT_UP( mov r3, r0, lsr #26) ands r3, r3, #7 << 1 Use this method for the LoUIS, LoUU and LoC fields. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1 changed files with 6 additions and 7 deletions
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@ -90,8 +90,9 @@ ENDPROC(v7_flush_icache_all)
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ENTRY(v7_flush_dcache_louis)
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ENTRY(v7_flush_dcache_louis)
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dmb @ ensure ordering with previous memory accesses
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
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mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
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ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
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ALT_SMP(mov r3, r0, lsr #20) @ move LoUIS into position
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ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
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ALT_UP( mov r3, r0, lsr #26) @ move LoUU into position
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ands r3, r3, #7 << 1 @ extract LoU*2 field from clidr
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#ifdef CONFIG_ARM_ERRATA_643719
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#ifdef CONFIG_ARM_ERRATA_643719
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ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register
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ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register
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ALT_UP(reteq lr) @ LoUU is zero, so nothing to do
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ALT_UP(reteq lr) @ LoUU is zero, so nothing to do
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@ -99,10 +100,8 @@ ENTRY(v7_flush_dcache_louis)
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movteq r1, #:upper16:0x410fc090
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movteq r1, #:upper16:0x410fc090
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biceq r2, r2, #0x0000000f @ clear minor revision number
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biceq r2, r2, #0x0000000f @ clear minor revision number
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teqeq r2, r1 @ test for errata affected core and if so...
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teqeq r2, r1 @ test for errata affected core and if so...
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orreqs r3, #(1 << 21) @ fix LoUIS value (and set flags state to 'ne')
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moveqs r3, #1 << 1 @ fix LoUIS value (and set flags state to 'ne')
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#endif
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#endif
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ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2
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ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2
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reteq lr @ return if level == 0
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reteq lr @ return if level == 0
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mov r10, #0 @ r10 (starting level) = 0
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mov r10, #0 @ r10 (starting level) = 0
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b flush_levels @ start flushing cache levels
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b flush_levels @ start flushing cache levels
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@ -120,8 +119,8 @@ ENDPROC(v7_flush_dcache_louis)
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ENTRY(v7_flush_dcache_all)
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ENTRY(v7_flush_dcache_all)
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dmb @ ensure ordering with previous memory accesses
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r0, lsr #23 @ move LoC into position
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mov r3, r3, lsr #23 @ left align loc bit field
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ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
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beq finished @ if loc is 0, then no need to clean
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beq finished @ if loc is 0, then no need to clean
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mov r10, #0 @ start clean at cache level 0
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mov r10, #0 @ start clean at cache level 0
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flush_levels:
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flush_levels:
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