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can: flexcan: flexcan_chip_freeze(): fix chip freeze for missing bitrate
For cases when flexcan is built-in, bitrate is still not set at
registering. So flexcan_chip_freeze() generates:
[ 1.860000] *** ZERO DIVIDE *** FORMAT=4
[ 1.860000] Current process id is 1
[ 1.860000] BAD KERNEL TRAP: 00000000
[ 1.860000] PC: [<402e70c8>] flexcan_chip_freeze+0x1a/0xa8
To allow chip freeze, using an hardcoded timeout when bitrate is still
not set.
Fixes: ec15e27cc8
("can: flexcan: enable RX FIFO after FRZ/HALT valid")
Link: https://lore.kernel.org/r/20210315231510.650593-1-angelo@kernel-space.org
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
[mkl: use if instead of ? operator]
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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1 changed files with 7 additions and 1 deletions
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@ -697,9 +697,15 @@ static int flexcan_chip_disable(struct flexcan_priv *priv)
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static int flexcan_chip_freeze(struct flexcan_priv *priv)
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{
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struct flexcan_regs __iomem *regs = priv->regs;
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unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
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unsigned int timeout;
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u32 bitrate = priv->can.bittiming.bitrate;
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u32 reg;
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if (bitrate)
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timeout = 1000 * 1000 * 10 / bitrate;
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else
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timeout = FLEXCAN_TIMEOUT_US / 10;
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reg = priv->read(®s->mcr);
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reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
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priv->write(reg, ®s->mcr);
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