From 2c60dc4342f1d95859232d4cd5f77011fc395b31 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Thu, 8 Sep 2016 19:03:43 +0800 Subject: [PATCH 001/168] arm64: dts: rockchip: fix i2c resource error of rk3368 According to the TRM and downstream code from rockchip, the register address of i2c1 on rk3368 is 0xff660000 and i2c2 is 0xff140000. This patch fix the i2c1 & i2c2 register address definition error, also fix the clk and pinctrl reference error. Signed-off-by: Andy Yan Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 0fcb2147c9f9..2f8e19ff65a5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -315,16 +315,16 @@ spi2: spi@ff130000 { status = "disabled"; }; - i2c1: i2c@ff140000 { + i2c2: i2c@ff140000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff140000 0x0 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; + clocks = <&cru PCLK_I2C2>; pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; + pinctrl-0 = <&i2c2_xfer>; status = "disabled"; }; @@ -554,16 +554,16 @@ i2c0: i2c@ff650000 { status = "disabled"; }; - i2c2: i2c@ff660000 { + i2c1: i2c@ff660000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff660000 0x0 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; + clocks = <&cru PCLK_I2C1>; pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; + pinctrl-0 = <&i2c1_xfer>; status = "disabled"; }; From 06ad4b2fad80713c50a31da6d1048cb1df728558 Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Wed, 7 Sep 2016 16:06:17 -0700 Subject: [PATCH 002/168] arm64: dts: rockchip: add powerdomain for typec on rk3399 The tcpc power domain will try to power up/down the power of Type-C PHY. Hence, we need control it in Type-C PHY driver with the pm_runtime helper. Signed-off-by: Chris Zhong Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index b65c193dc64e..76b28649f0b0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1148,6 +1148,7 @@ tcphy0: phy@ff7c0000 { clock-names = "tcpdcore", "tcpdphy-ref"; assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD0>; resets = <&cru SRST_UPHY0>, <&cru SRST_UPHY0_PIPE_L00>, <&cru SRST_P_UPHY0_TCPHY>; @@ -1176,6 +1177,7 @@ tcphy1: phy@ff800000 { clock-names = "tcpdcore", "tcpdphy-ref"; assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD1>; resets = <&cru SRST_UPHY1>, <&cru SRST_UPHY1_PIPE_L00>, <&cru SRST_P_UPHY1_TCPHY>; From 76c923bb64923a387f0fc95480afb61ff1504eae Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sun, 11 Sep 2016 01:47:03 +0800 Subject: [PATCH 003/168] arm64: dts: rockchip: Add PX5 Evaluation board PX5 EVB is designed by Rockchip for automotive field with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS HDMI video input/output interface, audio codec ES8396, WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity sensor STK3410. Signed-off-by: Andy Yan Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/arm/rockchip.txt | 8 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3368-px5-evb.dts | 293 ++++++++++++++++++ 3 files changed, 302 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 55f388f954de..dfd605fd6848 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -99,6 +99,14 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "mqmaker,miqi", "rockchip,rk3288"; +- Rockchip PX3 Evaluation board: + Required root node properties: + - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; + +- Rockchip PX5 Evaluation board: + Required root node properties: + - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; + - Rockchip RK3368 evb: Required root node properties: - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 87669f656454..3a862894ea44 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,6 +1,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts new file mode 100644 index 000000000000..3ffa71d169e2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include + +/ { + model = "Rockchip PX5 EVB"; + compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; + + chosen { + stdout-path = "serial4:115200n8"; + }; + + memory@0 { + reg = <0x0 0x0 0x0 0x80000000>; + device_type = "memory"; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + wakeup-source; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + clock-frequency = <150000000>; + disable-wp; + keep-power-in-suspend; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_flash>; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&pmic_sleep>; + rockchip,system-power-controller; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu"; + }; + + vdd_log: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_log"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + }; + + vcc18_flash: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_flash"; + }; + + vcca_33: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_33"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + }; + + avdd_33: LDO_REG4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avdd_33"; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + }; + + vcc_sd: SWITCH_REG1 { + regulator-name = "vcc_sd"; + }; + + vcc33_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc33_lcd"; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + accelerometer@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + status = "okay"; + + gsl1680: touchscreen@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupt-parent = <&gpio3>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + power-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + silead,max-fingers = <5>; + }; +}; + +&pinctrl { + keys { + pwr_key: pwr-key { + rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_sleep: pmic-sleep { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <0>; /* CRU */ + rockchip,hw-tshut-polarity = <1>; /* high */ +}; + +&uart4 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; From 674c81cf2c22918e34a8b42b89aaf89247256b6d Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 22 Sep 2016 12:02:17 +0800 Subject: [PATCH 004/168] arm64: dts: rockchip: Add more properties for emmc on px5-evb The emmc on px5-evb can support hs200, so let's add mmc-hs200-1_8v. And in order to speed up the boot time, we could add no-sdio and no-sd to simplify the initialization. Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts index 3ffa71d169e2..4fa5806a0695 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts @@ -87,6 +87,9 @@ &emmc { clock-frequency = <150000000>; disable-wp; keep-power-in-suspend; + mmc-hs200-1_8v; + no-sdio; + no-sd; non-removable; num-slots = <1>; pinctrl-names = "default"; From 41a603b9337c412e5902091f5343f803b36b9995 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 22 Sep 2016 12:02:18 +0800 Subject: [PATCH 005/168] arm64: dts: rockchip: add sdmmc support for px5-evb px5-evb has one sdmmc slot, so we could support sdmmc. Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3368-px5-evb.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts index 4fa5806a0695..85f7a243d744 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts @@ -273,6 +273,24 @@ pmic_int: pmic-int { }; }; +&sdmmc { + status = "okay"; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + no-emmc; + no-sdio; + num-slots = <1>; + sd-uhs-sdr12; + sd-uhs-sdr25; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_bus4>, <&sdmmc_cd>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; +}; + &tsadc { status = "okay"; rockchip,hw-tshut-mode = <0>; /* CRU */ From 2a927eeaf6b64f39b4f0907417f85c7ee1d26119 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 13 Sep 2016 12:56:59 +0200 Subject: [PATCH 006/168] arm64: dts: r8a7795: salvator-x: enable UHS for SDHI 0 & 3 Reviewed-by: Geert Uytterhoeven Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman --- .../boot/dts/renesas/r8a7795-salvator-x.dts | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index b1eab6876f8c..ff4e4fe843ed 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -237,11 +237,25 @@ du_pins: du { sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; }; sdhi3_pins: sd3 { groups = "sdhi3_data4", "sdhi3_ctrl"; function = "sdhi3"; + power-source = <3300>; + }; + + sdhi3_pins_uhs: sd3_uhs { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <1800>; }; sound_pins: sound { @@ -371,25 +385,29 @@ &sata { &sdhi0 { pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; bus-width = <4>; + sd-uhs-sdr50; status = "okay"; }; &sdhi3 { pinctrl-0 = <&sdhi3_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi3_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi3>; vqmmc-supply = <&vccq_sdhi3>; cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; bus-width = <4>; + sd-uhs-sdr50; status = "okay"; }; From ad47fff1941115d8caf88061851993f6e001c03e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 20 Sep 2016 14:25:17 +0200 Subject: [PATCH 007/168] arm64: dts: r8a7796: salvator-x: Populate EXTALR It can be used for the watchdog. Based on similar work for r8a7795/salvator-x by Wolfram Sang. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index 13db7d61c26c..90e9a76c8b30 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -49,6 +49,10 @@ &extal_clk { clock-frequency = <16666666>; }; +&extalr_clk { + clock-frequency = <32768>; +}; + &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; From ea3c17b03b9bb57c0ea05a8afac934649128c2f0 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 3 Oct 2016 20:12:31 +0300 Subject: [PATCH 008/168] arm64: dts: r8a7795: salvator-x: Add DU LVDS output endpoint Declaring the endpoint makes LVDS enablement easier by just including the corresponding panel's dtsi file. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index ff4e4fe843ed..c8f6023c4667 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -191,6 +191,10 @@ endpoint { remote-endpoint = <&adv7123_in>; }; }; + port@3 { + lvds_connector: endpoint { + }; + }; }; }; From e735aaf8fc4ac84dbdb3642a135da8dcdb84587b Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Thu, 6 Oct 2016 11:14:29 +0200 Subject: [PATCH 009/168] arm64: dts: marvell: Add definition for the Globalscale Marvell ESPRESSOBin Board This is a high performance 64 bit dual core low power consuming networking computing platform based on the ARMv8 architecture. It contains an Armada 3720 running up to 1.2Ghz. This commit adds a basic definition for this board. Signed-off-by: Romain Perier Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../dts/marvell/armada-3720-espressobin.dts | 82 +++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index cf3953124cef..1690883b931a 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb # Mvebu SoC Family dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts new file mode 100644 index 000000000000..eadd5993c7bd --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -0,0 +1,82 @@ +/* + * Device Tree file for Globalscale Marvell ESPRESSOBin Board + * Copyright (C) 2016 Marvell + * + * Romain Perier + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "armada-372x.dtsi" + +/ { + model = "Globalscale Marvell ESPRESSOBin Board"; + compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; +}; + +/* J9 */ +&pcie0 { + status = "okay"; +}; + +/* J6 */ +&sata { + status = "okay"; +}; + +/* Exported on the micro USB connector J5 through an FTDI */ +&uart0 { + status = "okay"; +}; + +/* J7 */ +&usb3 { + status = "okay"; +}; From 2ac15068f3468d439c19865fbc04597fc6d98832 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 17 Oct 2016 13:13:34 +0100 Subject: [PATCH 010/168] arm64: dts: juno: Add SMMUs device nodes Juno has separate MMU-401 instances in front of the DMA-330, both HDLCD controllers, the USB host controller, the PCIe root complex, and the CoreSight ETR. Since there is still work to do to make all the relevant subsystems interact nicely with the presence of an IOMMU, add the nodes to aid development and testing but leave them disabled by default to avoid nasty surprises. CC: Liviu Dudau CC: Lorenzo Pieralisi Signed-off-by: Robin Murphy [sudeep.holla@arm.com: reformated subject] Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-base.dtsi | 80 ++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 334271a25f70..100810a8b929 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -29,6 +29,28 @@ mailbox: mhu@2b1f0000 { clock-names = "apb_pclk"; }; + smmu_pcie: iommu@2b500000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x2b500000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + dma-coherent; + status = "disabled"; + }; + + smmu_etr: iommu@2b600000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x2b600000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + dma-coherent; + status = "disabled"; + }; + gic: interrupt-controller@2c010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; reg = <0x0 0x2c010000 0 0x1000>, @@ -146,6 +168,7 @@ main_funnel_in_port1: endpoint { etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20070000 0 0x1000>; + iommus = <&smmu_etr 0>; clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; @@ -404,6 +427,8 @@ pcie_ctlr: pcie-controller@40000000 { <0 0 0 4 &gic 0 0 0 139 4>; msi-parent = <&v2m_0>; status = "disabled"; + iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ + iommu-map = <0x0 &smmu_pcie 0x0 0x1>; }; scpi { @@ -484,6 +509,48 @@ gpu1_thermal_zone: gpu1 { /include/ "juno-clocks.dtsi" + smmu_dma: iommu@7fb00000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x7fb00000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + dma-coherent; + status = "disabled"; + }; + + smmu_hdlcd1: iommu@7fb10000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x7fb10000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + status = "disabled"; + }; + + smmu_hdlcd0: iommu@7fb20000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x7fb20000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + status = "disabled"; + }; + + smmu_usb: iommu@7fb30000 { + compatible = "arm,mmu-401", "arm,smmu-v1"; + reg = <0x0 0x7fb30000 0x0 0x10000>; + interrupts = , + ; + #iommu-cells = <1>; + #global-interrupts = <1>; + dma-coherent; + status = "disabled"; + }; + dma@7ff00000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0x7ff00000 0 0x1000>; @@ -499,6 +566,15 @@ dma@7ff00000 { , , ; + iommus = <&smmu_dma 0>, + <&smmu_dma 1>, + <&smmu_dma 2>, + <&smmu_dma 3>, + <&smmu_dma 4>, + <&smmu_dma 5>, + <&smmu_dma 6>, + <&smmu_dma 7>, + <&smmu_dma 8>; clocks = <&soc_faxiclk>; clock-names = "apb_pclk"; }; @@ -507,6 +583,7 @@ hdlcd@7ff50000 { compatible = "arm,hdlcd"; reg = <0 0x7ff50000 0 0x1000>; interrupts = ; + iommus = <&smmu_hdlcd1 0>; clocks = <&scpi_clk 3>; clock-names = "pxlclk"; @@ -521,6 +598,7 @@ hdlcd@7ff60000 { compatible = "arm,hdlcd"; reg = <0 0x7ff60000 0 0x1000>; interrupts = ; + iommus = <&smmu_hdlcd0 0>; clocks = <&scpi_clk 3>; clock-names = "pxlclk"; @@ -574,6 +652,7 @@ ohci@7ffb0000 { compatible = "generic-ohci"; reg = <0x0 0x7ffb0000 0x0 0x10000>; interrupts = ; + iommus = <&smmu_usb 0>; clocks = <&soc_usb48mhz>; }; @@ -581,6 +660,7 @@ ehci@7ffc0000 { compatible = "generic-ehci"; reg = <0x0 0x7ffc0000 0x0 0x10000>; interrupts = ; + iommus = <&smmu_usb 0>; clocks = <&soc_usb48mhz>; }; From 4d6815b453c60c75c9a910756858a421c0d79a1a Mon Sep 17 00:00:00 2001 From: Juri Lelli Date: Mon, 17 Oct 2016 16:46:46 +0100 Subject: [PATCH 011/168] arm64: dts: juno: add cpu capacity-dmips-mhz information to R0 boards This patch adds cpu capacity-dmips-mhz information to Juno R0 boards. Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Catalin Marinas Cc: Will Deacon Cc: Liviu Dudau Cc: Sudeep Holla Cc: Arnd Bergmann Cc: Jon Medhurst Cc: Olof Johansson Cc: Robin Murphy Cc: devicetree@vger.kernel.org Signed-off-by: Juri Lelli [sudeep.holla@arm.com: reformated subject and updated changelog] Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index a7270eff6939..6b4135e9cfe5 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -90,6 +90,7 @@ A57_0: cpu@0 { next-level-cache = <&A57_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; }; A57_1: cpu@1 { @@ -100,6 +101,7 @@ A57_1: cpu@1 { next-level-cache = <&A57_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; }; A53_0: cpu@100 { @@ -110,6 +112,7 @@ A53_0: cpu@100 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A53_1: cpu@101 { @@ -120,6 +123,7 @@ A53_1: cpu@101 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A53_2: cpu@102 { @@ -130,6 +134,7 @@ A53_2: cpu@102 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A53_3: cpu@103 { @@ -140,6 +145,7 @@ A53_3: cpu@103 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A57_L2: l2-cache0 { From f5ef5c9e01f4e09a3b776956035ee1272bb3375b Mon Sep 17 00:00:00 2001 From: Juri Lelli Date: Mon, 17 Oct 2016 16:46:47 +0100 Subject: [PATCH 012/168] arm64: dts: juno: add cpu capacity-dmips-mhz information to R1 boards This patch adds cpu capacity-dmips-mhz information to Juno R1 boards. Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Catalin Marinas Cc: Will Deacon Cc: Liviu Dudau Cc: Sudeep Holla Cc: Arnd Bergmann Cc: Jon Medhurst Cc: Olof Johansson Cc: Robin Murphy Cc: devicetree@vger.kernel.org Signed-off-by: Juri Lelli [sudeep.holla@arm.com: reformated subject and updated changelog] Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-r1.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index 123a58b29cbd..3be8a3ef671c 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -90,6 +90,7 @@ A57_0: cpu@0 { next-level-cache = <&A57_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; }; A57_1: cpu@1 { @@ -100,6 +101,7 @@ A57_1: cpu@1 { next-level-cache = <&A57_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; }; A53_0: cpu@100 { @@ -110,6 +112,7 @@ A53_0: cpu@100 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A53_1: cpu@101 { @@ -120,6 +123,7 @@ A53_1: cpu@101 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A53_2: cpu@102 { @@ -130,6 +134,7 @@ A53_2: cpu@102 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A53_3: cpu@103 { @@ -140,6 +145,7 @@ A53_3: cpu@103 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <578>; }; A57_L2: l2-cache0 { From c1ab65b24065ab04bdb0bc4e89d88784d38dc644 Mon Sep 17 00:00:00 2001 From: Juri Lelli Date: Mon, 17 Oct 2016 16:46:48 +0100 Subject: [PATCH 013/168] arm64: dts: juno: add cpu capacity-dmips-mhz information to R2 boards This patch adds cpu capacity-dmips-mhz information to Juno R2 boards. Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Catalin Marinas Cc: Will Deacon Cc: Liviu Dudau Cc: Sudeep Holla Cc: Arnd Bergmann Cc: Jon Medhurst Cc: Olof Johansson Cc: Robin Murphy Cc: devicetree@vger.kernel.org Signed-off-by: Juri Lelli [sudeep.holla@arm.com: reformated subject and updated changelog] Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-r2.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index 007be826efce..614fc9227943 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -90,6 +90,7 @@ A72_0: cpu@0 { next-level-cache = <&A72_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; }; A72_1: cpu@1 { @@ -100,6 +101,7 @@ A72_1: cpu@1 { next-level-cache = <&A72_L2>; clocks = <&scpi_dvfs 0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; }; A53_0: cpu@100 { @@ -110,6 +112,7 @@ A53_0: cpu@100 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; }; A53_1: cpu@101 { @@ -120,6 +123,7 @@ A53_1: cpu@101 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; }; A53_2: cpu@102 { @@ -130,6 +134,7 @@ A53_2: cpu@102 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; }; A53_3: cpu@103 { @@ -140,6 +145,7 @@ A53_3: cpu@103 { next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <485>; }; A72_L2: l2-cache0 { From a6d729dbe115d31e6bbd4dd7bfc28b5bcd1db9d1 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 21 Aug 2016 15:10:01 +0000 Subject: [PATCH 014/168] ARM64: dts: bcm283x: Use dtsi for USB host mode In case dr_mode isn't passed via DT, the dwc2 driver defaults to OTG mode. But the Raspberry Pi 3 is designed only for host mode. So fix this issue by linking to the dtsi file which set the dr_mode to host. Signed-off-by: Stefan Wahren Signed-off-by: Eric Anholt Tested-by: Gerd Hoffmann --- arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts | 1 + arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi | 1 + 2 files changed, 2 insertions(+) create mode 120000 arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts index 7841b724e340..7625e57a64b5 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts @@ -2,6 +2,7 @@ #include "bcm2837.dtsi" #include "bcm2835-rpi.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; diff --git a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi new file mode 120000 index 000000000000..cbeebe312ff8 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi @@ -0,0 +1 @@ +../../../../arm/boot/dts/bcm283x-rpi-usb-host.dtsi \ No newline at end of file From c328666d58aac4880bf0934eb915f9c5d1801360 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 4 Oct 2016 17:37:08 +0200 Subject: [PATCH 015/168] ARM64: dts: amlogic: Add Meson GX dtsi from GXBB Move all non-gxbb specific nodes to a common GX dtsi. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 200 +++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 933 +++++++++----------- 2 files changed, 598 insertions(+), 535 deletions(-) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gx.dtsi diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi new file mode 100644 index 000000000000..0737056b369f --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cbus: cbus@c1100000 { + compatible = "simple-bus"; + reg = <0x0 0xc1100000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; + + uart_A: serial@84c0 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x84c0 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@c4301000 { + compatible = "arm,gic-400"; + reg = <0x0 0xc4301000 0 0x1000>, + <0x0 0xc4302000 0 0x2000>, + <0x0 0xc4304000 0 0x2000>, + <0x0 0xc4306000 0 0x2000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + aobus: aobus@c8100000 { + compatible = "simple-bus"; + reg = <0x0 0xc8100000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; + + uart_AO: serial@4c0 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x004c0 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; + status = "disabled"; + }; + }; + + periphs: periphs@c8834000 { + compatible = "simple-bus"; + reg = <0x0 0xc8834000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; + }; + + + hiubus: hiubus@c883c000 { + compatible = "simple-bus"; + reg = <0x0 0xc883c000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; + }; + + apb: apb@d0000000 { + compatible = "simple-bus"; + reg = <0x0 0xd0000000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 610e0e1c3cee..443811b497de 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -40,9 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include -#include -#include +#include "meson-gx.dtsi" #include #include #include @@ -51,56 +49,6 @@ / { compatible = "amlogic,meson-gxbb"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; firmware { sm: secure-monitor { @@ -126,31 +74,7 @@ bid: bid@46 { }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - usb0_phy: phy@c0000000 { compatible = "amlogic,meson-gxbb-usb2-phy"; #phy-cells = <0>; @@ -170,464 +94,6 @@ usb1_phy: phy@c0000020 { status = "disabled"; }; - cbus: cbus@c1100000 { - compatible = "simple-bus"; - reg = <0x0 0xc1100000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; - - reset: reset-controller@4404 { - compatible = "amlogic,meson-gxbb-reset"; - reg = <0x0 0x04404 0x0 0x20>; - #reset-cells = <1>; - }; - - uart_A: serial@84c0 { - compatible = "amlogic,meson-uart"; - reg = <0x0 0x84c0 0x0 0x14>; - interrupts = ; - clocks = <&xtal>; - status = "disabled"; - }; - - uart_B: serial@84dc { - compatible = "amlogic,meson-uart"; - reg = <0x0 0x84dc 0x0 0x14>; - interrupts = ; - clocks = <&xtal>; - status = "disabled"; - }; - - pwm_ab: pwm@8550 { - compatible = "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08550 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@8650 { - compatible = "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08650 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x086c0 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_C: serial@8700 { - compatible = "amlogic,meson-uart"; - reg = <0x0 0x8700 0x0 0x14>; - interrupts = ; - clocks = <&xtal>; - status = "disabled"; - }; - - watchdog@98d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0x098d0 0x0 0x10>; - clocks = <&xtal>; - }; - - spifc: spi@8c80 { - compatible = "amlogic,meson-gxbb-spifc"; - reg = <0x0 0x08c80 0x0 0x80>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_SPI>; - status = "disabled"; - }; - - i2c_A: i2c@8500 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x08500 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_B: i2c@87c0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087c0 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_C: i2c@87e0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087e0 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - gic: interrupt-controller@c4301000 { - compatible = "arm,gic-400"; - reg = <0x0 0xc4301000 0 0x1000>, - <0x0 0xc4302000 0 0x2000>, - <0x0 0xc4304000 0 0x2000>, - <0x0 0xc4306000 0 0x2000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - aobus: aobus@c8100000 { - compatible = "simple-bus"; - reg = <0x0 0xc8100000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; - - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-gxbb-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - }; - }; - - i2c_ao_pins: i2c_ao { - mux { - groups = "i2c_sck_ao", - "i2c_sda_ao"; - function = "i2c_ao"; - }; - }; - - pwm_ao_a_3_pins: pwm_ao_a_3 { - mux { - groups = "pwm_ao_a_3"; - function = "pwm_ao_a_3"; - }; - }; - - pwm_ao_a_6_pins: pwm_ao_a_6 { - mux { - groups = "pwm_ao_a_6"; - function = "pwm_ao_a_6"; - }; - }; - - pwm_ao_a_12_pins: pwm_ao_a_12 { - mux { - groups = "pwm_ao_a_12"; - function = "pwm_ao_a_12"; - }; - }; - - pwm_ao_b_pins: pwm_ao_b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - }; - }; - }; - - clkc_AO: clock-controller@040 { - compatible = "amlogic,gxbb-aoclkc"; - reg = <0x0 0x00040 0x0 0x4>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - uart_AO: serial@4c0 { - compatible = "amlogic,meson-uart"; - reg = <0x0 0x004c0 0x0 0x14>; - interrupts = ; - clocks = <&xtal>; - status = "disabled"; - }; - - ir: ir@580 { - compatible = "amlogic,meson-gxbb-ir"; - reg = <0x0 0x00580 0x0 0x40>; - interrupts = ; - status = "disabled"; - }; - - pwm_ab_AO: pwm@550 { - compatible = "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x0550 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i2c_AO: i2c@500 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x500 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_AO_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - periphs: periphs@c8834000 { - compatible = "simple-bus"; - reg = <0x0 0xc8834000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; - - rng { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x0 0x0 0x4>; - }; - - pinctrl_periphs: pinctrl@4b0 { - compatible = "amlogic,meson-gxbb-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@4b0 { - reg = <0x0 0x004b0 0x0 0x28>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00120 0x0 0x14>, - <0x0 0x00430 0x0 0x40>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - emmc_pins: emmc { - mux { - groups = "emmc_nand_d07", - "emmc_cmd", - "emmc_clk"; - function = "emmc"; - }; - }; - - nor_pins: nor { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_cs"; - function = "nor"; - }; - }; - - sdcard_pins: sdcard { - mux { - groups = "sdcard_d0", - "sdcard_d1", - "sdcard_d2", - "sdcard_d3", - "sdcard_cmd", - "sdcard_clk"; - function = "sdcard"; - }; - }; - - sdio_pins: sdio { - mux { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd", - "sdio_clk"; - function = "sdio"; - }; - }; - - sdio_irq_pins: sdio_irq { - mux { - groups = "sdio_irq"; - function = "sdio"; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - }; - }; - - uart_b_pins: uart_b { - mux { - groups = "uart_tx_b", - "uart_rx_b"; - function = "uart_b"; - }; - }; - - uart_c_pins: uart_c { - mux { - groups = "uart_tx_c", - "uart_rx_c"; - function = "uart_c"; - }; - }; - - i2c_a_pins: i2c_a { - mux { - groups = "i2c_sck_a", - "i2c_sda_a"; - function = "i2c_a"; - }; - }; - - i2c_b_pins: i2c_b { - mux { - groups = "i2c_sck_b", - "i2c_sda_b"; - function = "i2c_b"; - }; - }; - - i2c_c_pins: i2c_c { - mux { - groups = "i2c_sck_c", - "i2c_sda_c"; - function = "i2c_c"; - }; - }; - - eth_pins: eth_c { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_rxd2", - "eth_rxd3", - "eth_rgmii_tx_clk", - "eth_tx_en", - "eth_txd0", - "eth_txd1", - "eth_txd2", - "eth_txd3"; - function = "eth"; - }; - }; - - pwm_a_x_pins: pwm_a_x { - mux { - groups = "pwm_a_x"; - function = "pwm_a_x"; - }; - }; - - pwm_a_y_pins: pwm_a_y { - mux { - groups = "pwm_a_y"; - function = "pwm_a_y"; - }; - }; - - pwm_b_pins: pwm_b { - mux { - groups = "pwm_b"; - function = "pwm_b"; - }; - }; - - pwm_d_pins: pwm_d { - mux { - groups = "pwm_d"; - function = "pwm_d"; - }; - }; - - pwm_e_pins: pwm_e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - }; - }; - - pwm_f_x_pins: pwm_f_x { - mux { - groups = "pwm_f_x"; - function = "pwm_f_x"; - }; - }; - - pwm_f_y_pins: pwm_f_y { - mux { - groups = "pwm_f_y"; - function = "pwm_f_y"; - }; - }; - }; - }; - - hiubus: hiubus@c883c000 { - compatible = "simple-bus"; - reg = <0x0 0xc883c000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; - - clkc: clock-controller@0 { - compatible = "amlogic,gxbb-clkc"; - #clock-cells = <1>; - reg = <0x0 0x0 0x0 0x3db>; - }; - - mailbox: mailbox@404 { - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0x404 0 0x4c>; - interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, - <0 209 IRQ_TYPE_EDGE_RISING>, - <0 210 IRQ_TYPE_EDGE_RISING>; - #mbox-cells = <1>; - }; - }; - - apb: apb@d0000000 { - compatible = "simple-bus"; - reg = <0x0 0xd0000000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; - }; - usb0: usb@c9000000 { compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; reg = <0x0 0xc9000000 0x0 0x40000>; @@ -667,3 +133,400 @@ ethmac: ethernet@c9410000 { }; }; }; + +&cbus { + reset: reset-controller@4404 { + compatible = "amlogic,meson-gxbb-reset"; + reg = <0x0 0x04404 0x0 0x20>; + #reset-cells = <1>; + }; + + uart_B: serial@84dc { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x84dc 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; + status = "disabled"; + }; + + pwm_ab: pwm@8550 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x08550 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@8650 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x08650 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@86c0 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x086c0 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + uart_C: serial@8700 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x8700 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; + status = "disabled"; + }; + + watchdog@98d0 { + compatible = "amlogic,meson-gxbb-wdt"; + reg = <0x0 0x098d0 0x0 0x10>; + clocks = <&xtal>; + }; + + spifc: spi@8c80 { + compatible = "amlogic,meson-gxbb-spifc"; + reg = <0x0 0x08c80 0x0 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_SPI>; + status = "disabled"; + }; + + i2c_A: i2c@8500 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x08500 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_B: i2c@87c0 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x087c0 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_C: i2c@87e0 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x087e0 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; + +&aobus { + pinctrl_aobus: pinctrl@14 { + compatible = "amlogic,meson-gxbb-aobus-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_ao: bank@14 { + reg = <0x0 0x00014 0x0 0x8>, + <0x0 0x0002c 0x0 0x4>, + <0x0 0x00024 0x0 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; + }; + + remote_input_ao_pins: remote_input_ao { + mux { + groups = "remote_input_ao"; + function = "remote_input_ao"; + }; + }; + + i2c_ao_pins: i2c_ao { + mux { + groups = "i2c_sck_ao", + "i2c_sda_ao"; + function = "i2c_ao"; + }; + }; + + pwm_ao_a_3_pins: pwm_ao_a_3 { + mux { + groups = "pwm_ao_a_3"; + function = "pwm_ao_a_3"; + }; + }; + + pwm_ao_a_6_pins: pwm_ao_a_6 { + mux { + groups = "pwm_ao_a_6"; + function = "pwm_ao_a_6"; + }; + }; + + pwm_ao_a_12_pins: pwm_ao_a_12 { + mux { + groups = "pwm_ao_a_12"; + function = "pwm_ao_a_12"; + }; + }; + + pwm_ao_b_pins: pwm_ao_b { + mux { + groups = "pwm_ao_b"; + function = "pwm_ao_b"; + }; + }; + }; + + clkc_AO: clock-controller@040 { + compatible = "amlogic,gxbb-aoclkc"; + reg = <0x0 0x00040 0x0 0x4>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + ir: ir@580 { + compatible = "amlogic,meson-gxbb-ir"; + reg = <0x0 0x00580 0x0 0x40>; + interrupts = ; + status = "disabled"; + }; + + pwm_ab_AO: pwm@550 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x0550 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i2c_AO: i2c@500 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x500 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_AO_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; + +&periphs { + rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x0 0x0 0x4>; + }; + + pinctrl_periphs: pinctrl@4b0 { + compatible = "amlogic,meson-gxbb-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4b0 { + reg = <0x0 0x004b0 0x0 0x28>, + <0x0 0x004e8 0x0 0x14>, + <0x0 0x00120 0x0 0x14>, + <0x0 0x00430 0x0 0x40>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d07", + "emmc_cmd", + "emmc_clk"; + function = "emmc"; + }; + }; + + nor_pins: nor { + mux { + groups = "nor_d", + "nor_q", + "nor_c", + "nor_cs"; + function = "nor"; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + }; + }; + + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_cmd", + "sdio_clk"; + function = "sdio"; + }; + }; + + sdio_irq_pins: sdio_irq { + mux { + groups = "sdio_irq"; + function = "sdio"; + }; + }; + + uart_a_pins: uart_a { + mux { + groups = "uart_tx_a", + "uart_rx_a"; + function = "uart_a"; + }; + }; + + uart_b_pins: uart_b { + mux { + groups = "uart_tx_b", + "uart_rx_b"; + function = "uart_b"; + }; + }; + + uart_c_pins: uart_c { + mux { + groups = "uart_tx_c", + "uart_rx_c"; + function = "uart_c"; + }; + }; + + i2c_a_pins: i2c_a { + mux { + groups = "i2c_sck_a", + "i2c_sda_a"; + function = "i2c_a"; + }; + }; + + i2c_b_pins: i2c_b { + mux { + groups = "i2c_sck_b", + "i2c_sda_b"; + function = "i2c_b"; + }; + }; + + i2c_c_pins: i2c_c { + mux { + groups = "i2c_sck_c", + "i2c_sda_c"; + function = "i2c_c"; + }; + }; + + eth_pins: eth_c { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_clk_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2", + "eth_rxd3", + "eth_rgmii_tx_clk", + "eth_tx_en", + "eth_txd0", + "eth_txd1", + "eth_txd2", + "eth_txd3"; + function = "eth"; + }; + }; + + pwm_a_x_pins: pwm_a_x { + mux { + groups = "pwm_a_x"; + function = "pwm_a_x"; + }; + }; + + pwm_a_y_pins: pwm_a_y { + mux { + groups = "pwm_a_y"; + function = "pwm_a_y"; + }; + }; + + pwm_b_pins: pwm_b { + mux { + groups = "pwm_b"; + function = "pwm_b"; + }; + }; + + pwm_d_pins: pwm_d { + mux { + groups = "pwm_d"; + function = "pwm_d"; + }; + }; + + pwm_e_pins: pwm_e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_x_pins: pwm_f_x { + mux { + groups = "pwm_f_x"; + function = "pwm_f_x"; + }; + }; + + pwm_f_y_pins: pwm_f_y { + mux { + groups = "pwm_f_y"; + function = "pwm_f_y"; + }; + }; + }; +}; + +&hiubus { + clkc: clock-controller@0 { + compatible = "amlogic,gxbb-clkc"; + #clock-cells = <1>; + reg = <0x0 0x0 0x0 0x3db>; + }; + + mailbox: mailbox@404 { + compatible = "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; + interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, + <0 209 IRQ_TYPE_EDGE_RISING>, + <0 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; +}; From 15abee8ab055f774cf93d2866ab423c4ec1756db Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Tue, 4 Oct 2016 17:37:09 +0200 Subject: [PATCH 016/168] ARM64: dts: amlogic: Add basic support for Amlogic S905X MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch introduces the basic support for the Amlogic S905X (Meson GXL) and for the Amlogic evaluation board P212. No documentation has been released yet for this SoC, so for now only the bare minimum has been added in the DT. Acked-by: Rob Herring Reviewed-by: Andreas Färber Signed-off-by: Carlo Caione Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- .../devicetree/bindings/arm/amlogic.txt | 7 ++ arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-gxl-s905x-p212.dts | 69 +++++++++++++++++++ .../boot/dts/amlogic/meson-gxl-s905x.dtsi | 48 +++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 48 +++++++++++++ 5 files changed, 173 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index fcc6f6c10803..7edb635d61ac 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -17,6 +17,10 @@ Boards with the Amlogic Meson GXBaby SoC shall have the following properties: Required root node property: compatible: "amlogic,meson-gxbb"; +Boards with the Amlogic Meson GXL S905X SoC shall have the following properties: + Required root node property: + compatible: "amlogic,s905x", "amlogic,meson-gxl"; + Board compatible values: - "geniatech,atv1200" (Meson6) - "minix,neo-x8" (Meson8) @@ -28,3 +32,6 @@ Board compatible values: - "hardkernel,odroid-c2" (Meson gxbb) - "amlogic,p200" (Meson gxbb) - "amlogic,p201" (Meson gxbb) + - "amlogic,p212" (Meson gxl s905x) + - "amlogic,p230" (Meson gxl s905d) + - "amlogic,p231" (Meson gxl s905d) diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 47ec703cb230..1f78b07657ee 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts new file mode 100644 index 000000000000..9639f012b02b --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-gxl-s905x.dtsi" + +/ { + compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl"; + model = "Amlogic Meson GXL (S905X) P212 Development Board"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_AO { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi new file mode 100644 index 000000000000..07f0e0bdb363 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-gxl.dtsi" + +/ { + compatible = "amlogic,s905x", "amlogic,meson-gxl"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi new file mode 100644 index 000000000000..13b10eeb80b2 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-gx.dtsi" + +/ { + compatible = "amlogic,meson-gxl"; +}; From da47515ee63f3a993e492f41fde9f70c51e5eee8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 4 Oct 2016 17:37:10 +0200 Subject: [PATCH 017/168] ARM64: dts: amlogic: Add basic support for Amlogic S905D This patch introduces the basic support for the Amlogic S905D (MesonGXL) and for the Amlogic evaluation boards P230 and P231. No documentation has been released yet for this SoC, so for now only the bare minimum has been added in the DT. Acked-by: Rob Herring Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- .../devicetree/bindings/arm/amlogic.txt | 4 ++ arch/arm64/boot/dts/amlogic/Makefile | 2 + .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 51 +++++++++++++++ .../boot/dts/amlogic/meson-gxl-s905d-p231.dts | 51 +++++++++++++++ .../dts/amlogic/meson-gxl-s905d-p23x.dtsi | 63 +++++++++++++++++++ .../boot/dts/amlogic/meson-gxl-s905d.dtsi | 48 ++++++++++++++ 6 files changed, 219 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 7edb635d61ac..fffc17992510 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -21,6 +21,10 @@ Boards with the Amlogic Meson GXL S905X SoC shall have the following properties: Required root node property: compatible: "amlogic,s905x", "amlogic,meson-gxl"; +Boards with the Amlogic Meson GXL S905D SoC shall have the following properties: + Required root node property: + compatible: "amlogic,s905d", "amlogic,meson-gxl"; + Board compatible values: - "geniatech,atv1200" (Meson6) - "minix,neo-x8" (Meson8) diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 1f78b07657ee..57e0ae054dbc 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -5,6 +5,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts new file mode 100644 index 000000000000..3dfaa37f78f4 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-gxl-s905d-p23x.dtsi" + +/ { + compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl"; + model = "Amlogic Meson GXL (S905D) P230 Development Board"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts new file mode 100644 index 000000000000..ade8d29e5477 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-gxl-s905d-p23x.dtsi" + +/ { + compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl"; + model = "Amlogic Meson GXL (S905D) P231 Development Board"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi new file mode 100644 index 000000000000..bf08e874eadf --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-gxl-s905d.dtsi" + +/ { + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&uart_AO { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi new file mode 100644 index 000000000000..615308e55576 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-gxl.dtsi" + +/ { + compatible = "amlogic,s905d", "amlogic,meson-gxl"; +}; From 698ec9beba304114b23f72e9684a0282bc49cc94 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 5 Oct 2016 10:09:39 +0200 Subject: [PATCH 018/168] devicetree: Add vendor prefix for Nexbox Nexbox is an IPTV set-top-box distributor, mainly with Amlogic SoCs: https://www.inexbox.com Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index f0a48ea78659..0392cc38af26 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -186,6 +186,7 @@ neonode Neonode Inc. netgear NETGEAR netlogic Broadcom Corporation (formerly NetLogic Microsystems) netxeon Shenzhen Netxeon Technology CO., LTD +nexbox Nexbox newhaven Newhaven Display International nintendo Nintendo nokia Nokia From c246e9d6f6bc04f2abdec41cac28358db58abf2c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 5 Oct 2016 10:09:40 +0200 Subject: [PATCH 019/168] ARM64: dts: meson-gxbb: Add support for the Nexbox A95X Board Add support for the S905 (GXBB) version of the Nexbox A95X. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/meson-gxbb-nexbox-a95x.dts | 108 ++++++++++++++++++ 2 files changed, 109 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 57e0ae054dbc..5a640504a127 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts new file mode 100644 index 000000000000..80d7b35f67fa --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2016 Andreas Färber + * Copyright (c) 2016 BayLibre, Inc. + * Author: Neil Armstrong + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-gxbb.dtsi" +#include +#include + +/ { + compatible = "nexbox,a95x", "amlogic,meson-gxbb"; + model = "NEXBOX A95X"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + blue { + label = "a95x:system-status"; + gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + button@0 { + label = "reset"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; From 214ec5230d216763d0448c6a747a50cef64bcff6 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 5 Oct 2016 15:53:50 +0200 Subject: [PATCH 020/168] ARM64: dts: meson-gx: Add missing L2 cache node In order to remove the boot warning : [ 2.290933] Unable to detect cache hierarchy from DT for CPU 0 And add missing L2 cache hierarchy information, add a simple l2 cache node and reference it from the A53 cpu nodes. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 0737056b369f..a6cd953ef7e1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -64,6 +64,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -71,6 +72,7 @@ cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -78,6 +80,7 @@ cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -85,6 +88,11 @@ cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; }; }; From 3be2d9cf1cfbf5bb1ebb7cf958a665d0cac9e7d6 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 7 Oct 2016 16:59:15 +0200 Subject: [PATCH 021/168] ARM64: dts: meson-gxbb: Add rmii pinctrl node and rename rgmii node For boards only supporting 10/100 ethernet over a RMII PHY link, add a separate pinctrl node. By the way, rename the existing node to rgmii specific naming in all boards dts. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 3 ++- .../boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 +- .../arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 2 +- .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 17 ++++++++++++++++- 5 files changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts index 80d7b35f67fa..399d85f4cd0c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -97,8 +97,9 @@ &uart_AO { ðmac { status = "okay"; - pinctrl-0 = <ð_pins>; + pinctrl-0 = <ð_rmii_pins>; pinctrl-names = "default"; + phy-mode = "rmii"; }; &ir { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index e6e3491d48a5..325b9c5691be 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -83,7 +83,7 @@ &uart_AO { ðmac { status = "okay"; - pinctrl-0 = <ð_pins>; + pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index 06a34dc6002f..031d69bee16a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -81,7 +81,7 @@ &uart_AO { ðmac { status = "okay"; - pinctrl-0 = <ð_pins>; + pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index 73f159370188..e93221af390d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -82,7 +82,7 @@ &ir { ðmac { status = "okay"; - pinctrl-0 = <ð_pins>; + pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 443811b497de..aad639ab0112 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -443,7 +443,7 @@ mux { }; }; - eth_pins: eth_c { + eth_rgmii_pins: eth-rgmii { mux { groups = "eth_mdio", "eth_mdc", @@ -463,6 +463,21 @@ mux { }; }; + eth_rmii_pins: eth-rmii { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_clk_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_tx_en", + "eth_txd0", + "eth_txd1"; + function = "eth"; + }; + }; + pwm_a_x_pins: pwm_a_x { mux { groups = "pwm_a_x"; From 5a0803bd5ae289fbacd4d207e8c5e6719224ef92 Mon Sep 17 00:00:00 2001 From: Brian Kim Date: Tue, 4 Oct 2016 16:06:43 +0900 Subject: [PATCH 022/168] ARM64: dts: meson-gxbb-odroidc2: Enable USB Nodes Enable both gxbb USB controller and add a 5V regulator for the OTG port VBUS Signed-off-by: Brian Kim Signed-off-by: Kevin Hilman --- .../boot/dts/amlogic/meson-gxbb-odroidc2.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 325b9c5691be..a45d1013c225 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -64,6 +64,18 @@ memory@0 { reg = <0x0 0x0 0x0 0x80000000>; }; + usb_otg_pwr: regulator-usb-pwrs { + compatible = "regulator-fixed"; + + regulator-name = "USB_OTG_PWR"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + leds { compatible = "gpio-leds"; blue { @@ -98,3 +110,20 @@ &i2c_A { pinctrl-0 = <&i2c_a_pins>; pinctrl-names = "default"; }; + +&usb0_phy { + status = "okay"; + phy-supply = <&usb_otg_pwr>; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; From ff73917d38a691067fd4fddd90c8dfc0e97935d2 Mon Sep 17 00:00:00 2001 From: Kamal Dasu Date: Wed, 24 Aug 2016 18:04:28 -0400 Subject: [PATCH 023/168] ARM64: dts: Add QSPI Device Tree node for NS2 Adding QSPI node compatible with the new spi-bcm-qspi driver for the Broadcom's Northstar2 SoC. Signed-off-by: Kamal Dasu Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2-svk.dts | 34 ++++++++++++++++++++++++ arch/arm64/boot/dts/broadcom/ns2.dtsi | 18 +++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index 2d7872a36b91..730848740f74 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -185,3 +185,37 @@ nand_sel: nand_sel { groups = "nand_grp"; }; }; + +&qspi { + bspi-sel = <0>; + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index d95dc408629a..ae6c920da56c 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -565,5 +565,23 @@ nand: nand@66460000 { brcm,nand-has-wp; }; + + qspi: spi@66470200 { + compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, + <0x664703a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = ; + interrupt-names = "spi_l1_intr"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; From 3b3de83b7d287f4132310a9b3973fd42d6d2bbae Mon Sep 17 00:00:00 2001 From: Scott Branden Date: Sat, 8 Oct 2016 13:48:04 -0700 Subject: [PATCH 024/168] arm64: dts: rename ns2.txt to brcm,ns2.txt Rename ns2.txt to brcm,ns2.txt to match naming convention followed by rest of Broadcom binding documentation. Signed-off-by: Scott Branden Reviewed-by: Ray Jui Signed-off-by: Florian Fainelli --- .../devicetree/bindings/arm/bcm/{ns2.txt => brcm,ns2.txt} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/devicetree/bindings/arm/bcm/{ns2.txt => brcm,ns2.txt} (100%) diff --git a/Documentation/devicetree/bindings/arm/bcm/ns2.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt similarity index 100% rename from Documentation/devicetree/bindings/arm/bcm/ns2.txt rename to Documentation/devicetree/bindings/arm/bcm/brcm,ns2.txt From f4013cb78ac2c94d1c0aa454911cf7ae8a899d2a Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Wed, 20 Jul 2016 14:53:51 -0700 Subject: [PATCH 025/168] arm64: dts: Updated NAND DT properties for NS2 SVK This patch adds NAND DT properties for NS2 SVK to configure the bus width width and OOB sector size Signed-off-by: Prafulla Kota Signed-off-by: Ray Jui Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2-svk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index 730848740f74..c719bb5e2921 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -164,6 +164,8 @@ nandcs@0 { nand-ecc-mode = "hw"; nand-ecc-strength = <8>; nand-ecc-step-size = <512>; + nand-bus-width = <16>; + brcm,nand-oob-sector-size = <16>; #address-cells = <1>; #size-cells = <1>; }; From 62b69232d68114387b2e4bd30d258e4279b85de4 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Mon, 17 Oct 2016 13:13:36 +0100 Subject: [PATCH 026/168] arm64: dts: Update Broadcom NS2 to generic IOMMU binding With the "mmu-masters" property now deprecated and optional, the generic binding offers a more efficient way to specify no masters. CC: Ray Jui CC: Scott Branden CC: Jon Mason Signed-off-by: Robin Murphy Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index ae6c920da56c..f05b28b4856f 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -248,7 +248,7 @@ smmu: mmu@64000000 { , , ; - mmu-masters; + #iommu-cells = <1>; }; pinctrl: pinctrl@6501d130 { From ef8d2ffedf1878e4dc8d19d83371cef8e2457a44 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Thu, 20 Oct 2016 13:42:54 +0200 Subject: [PATCH 027/168] ARM64: dts: meson-gxbb: add MMC support Add binding and basic support for the SD/eMMC controller on Amlogic S905/GXBB devices. Acked-by: Rob Herring Signed-off-by: Kevin Hilman Signed-off-by: Neil Armstrong [narmstrong: added nodes for GX, enabled SDIO on P20x] Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 21 ++++ .../boot/dts/amlogic/meson-gxbb-odroidc2.dts | 88 +++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-p20x.dtsi | 98 +++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 24 ++++- 4 files changed, 230 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index a6cd953ef7e1..fd1d0deef889 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -203,6 +203,27 @@ apb: apb@d0000000 { #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; + + sd_emmc_a: mmc@70000 { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x70000 0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; + + sd_emmc_b: mmc@72000 { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x72000 0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; + + sd_emmc_c: mmc@74000 { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x74000 0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index a45d1013c225..238fbeacd330 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -85,6 +85,56 @@ blue { default-state = "off"; }; }; + + tflash_vdd: regulator-tflash_vdd { + /* + * signal name from schematics: TFLASH_VDD_EN + */ + compatible = "regulator-fixed"; + + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_ao GPIOAO_12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + tf_io: gpio-regulator-tf_io { + compatible = "regulator-gpio"; + + regulator-name = "TF_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + /* + * signal name from schematics: TF_3V3N_1V8_EN + */ + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0 + 1800000 1>; + }; + + vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; }; &uart_AO { @@ -127,3 +177,41 @@ &usb0 { &usb1 { status = "okay"; }; + +/* SD */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&tf_io>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc3v3>; + vqmmc-supply = <&vcc1v8>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index 031d69bee16a..86e740fb5969 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -70,6 +70,47 @@ usb_pwr: regulator-usb-pwrs { gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + vddio_card: gpio-regulator { + compatible = "regulator-gpio"; + + regulator-name = "VDDIO_CARD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + + /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ + states = <1800000 0 + 3300000 1>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; }; /* This UART is brought out to the DB9 connector */ @@ -107,3 +148,60 @@ &usb0 { &usb1 { status = "okay"; }; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_card>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index aad639ab0112..22940bbab7ff 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -349,7 +349,8 @@ emmc_pins: emmc { mux { groups = "emmc_nand_d07", "emmc_cmd", - "emmc_clk"; + "emmc_clk", + "emmc_ds"; function = "emmc"; }; }; @@ -545,3 +546,24 @@ mailbox: mailbox@404 { #mbox-cells = <1>; }; }; + +&sd_emmc_a { + clocks = <&clkc CLKID_SD_EMMC_A>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +}; + +&sd_emmc_b { + clocks = <&clkc CLKID_SD_EMMC_B>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +}; + +&sd_emmc_c { + clocks = <&clkc CLKID_SD_EMMC_C>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +}; From caafa69d364f922428240dd9e30ae6ae303abc97 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 20 Oct 2016 13:42:55 +0200 Subject: [PATCH 028/168] ARM64: dts: meson-gxbb: Add Wifi 32K clock for p20x boards Add a 32768Hz clock generated by the PWM E port used by the WiFi module. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index 86e740fb5969..6861b0af6573 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -111,6 +111,13 @@ emmc_pwrseq: emmc-pwrseq { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; }; /* This UART is brought out to the DB9 connector */ @@ -205,3 +212,11 @@ &sd_emmc_c { vmmc-supply = <&vcc_3v3>; vqmmc-supply = <&vddio_boot>; }; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; From ab3943fe57a23526ed5a89b3260b5a57d7746e63 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 20 Oct 2016 13:42:56 +0200 Subject: [PATCH 029/168] ARM64: dts: meson-gxbb: Add P20x Wifi SDIO support Add Wifi module support on the Amlogic P20x boards on the SDIO port. The Wifi module also needs a 32768Hz clock provided by the PWM E port through a pwm-clock node in it's power sequence. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index 6861b0af6573..203be28978d5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -118,6 +118,13 @@ wifi32k: wifi32k { clock-frequency = <32768>; pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; }; /* This UART is brought out to the DB9 connector */ @@ -171,8 +178,15 @@ &sd_emmc_a { non-removable; disable-wp; + mmc-pwrseq = <&sdio_pwrseq>; + vmmc-supply = <&vddao_3v3>; vqmmc-supply = <&vddio_boot>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; }; /* SD card */ From a776e045ce3d449ae81626139585f476b1b66baf Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 20 Oct 2016 13:42:57 +0200 Subject: [PATCH 030/168] ARM64: dts: meson-gxbb: Add MMC nodes to Nexbox A95x Add support for eMMC/SD/SDIO on the Nexbox A95x. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- .../dts/amlogic/meson-gxbb-nexbox-a95x.dts | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts index 399d85f4cd0c..969682092e0f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -87,6 +87,61 @@ button@0 { gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; }; }; + + vddio_card: gpio-regulator { + compatible = "regulator-gpio"; + + regulator-name = "VDDIO_CARD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + + /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ + states = <1800000 0 + 3300000 1>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; }; &uart_AO { @@ -107,3 +162,70 @@ &ir { pinctrl-0 = <&remote_input_ao_pins>; pinctrl-names = "default"; }; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_card>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; From fe62a2b232b7ab24ed90fc936e107db9641ff7bc Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 19 Oct 2016 14:51:11 +0200 Subject: [PATCH 031/168] ARM64: dts: meson-gxbb: Add SRAM node Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 22940bbab7ff..f6b68b046b0a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -94,6 +94,15 @@ usb1_phy: phy@c0000020 { status = "disabled"; }; + sram: sram@c8000000 { + compatible = "amlogic,meson-gxbb-sram", "mmio-sram"; + reg = <0x0 0xc8000000 0x0 0x14000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc8000000 0x14000>; + }; + usb0: usb@c9000000 { compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; reg = <0x0 0xc9000000 0x0 0x40000>; From 75b637f3bdd29883e4ab56d4dee39b9a7ef9d501 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 13 Sep 2016 16:09:54 +0800 Subject: [PATCH 032/168] dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings Adds SoC compatible for LS1043A and LS2080A which are supported, and for LS1046A which is going to be supported. Signed-off-by: Shaohui Xie Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index dbbc0952021c..2efbc097c342 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -131,6 +131,10 @@ Example: Freescale ARMv8 based Layerscape SoC family Device Tree Bindings ---------------------------------------------------------------- +LS1043A SoC +Required root node properties: + - compatible = "fsl,ls1043a"; + LS1043A ARMv8 based RDB Board Required root node properties: - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; @@ -139,6 +143,14 @@ LS1043A ARMv8 based QDS Board Required root node properties: - compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; +LS1046A SoC +Required root node properties: + - compatible = "fsl,ls1046a"; + +LS2080A SoC +Required root node properties: + - compatible = "fsl,ls2080a"; + LS2080A ARMv8 based Simulator model Required root node properties: - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; From 981034a2bfcaff5c95dafde24d7abfe7f9025c19 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 13 Sep 2016 16:09:55 +0800 Subject: [PATCH 033/168] dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG SCFG and DCFG are SoC-specific devices can be found on SoCs like LS1021A, LS1043A and LS1046A, this patch updates bindings for SCFG and DCFG to reflect more SoCs. Signed-off-by: Shaohui Xie Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.txt | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index 2efbc097c342..a81277fdc7bc 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -97,7 +97,7 @@ Freescale LS1021A Platform Device Tree Bindings Required root node compatible properties: - compatible = "fsl,ls1021a"; -Freescale LS1021A SoC-specific Device Tree Bindings +Freescale SoC-specific Device Tree Bindings ------------------------------------------- Freescale SCFG @@ -105,7 +105,11 @@ Freescale SCFG configuration and status registers for the chip. Such as getting PEX port status. Required properties: - - compatible: should be "fsl,ls1021a-scfg" + - compatible: Should contain a chip-specific compatible string, + Chip-specific strings are of the form "fsl,-scfg", + The following s are known to be supported: + ls1021a, ls1043a, ls1046a, ls2080a. + - reg: should contain base address and length of SCFG memory-mapped registers Example: @@ -119,7 +123,11 @@ Freescale DCFG configuration and status for the device. Such as setting the secondary core start address and release the secondary core from holdoff and startup. Required properties: - - compatible: should be "fsl,ls1021a-dcfg" + - compatible: Should contain a chip-specific compatible string, + Chip-specific strings are of the form "fsl,-dcfg", + The following s are known to be supported: + ls1021a, ls1043a, ls1046a, ls2080a. + - reg : should contain base address and length of DCFG memory-mapped registers Example: From f849aef6afa710d61e2f17c803f87f793cd2cb6d Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 13 Sep 2016 16:09:56 +0800 Subject: [PATCH 034/168] dt-bindings: i2c: adds two more nxp devices "nxp,pcf2127" and "nxp,pcf2129" are I2c devices, adds them to the list of trivial i2c devices. Signed-off-by: Shaohui Xie Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/i2c/trivial-devices.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index fbbad6446741..8a43a5ebc07c 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -130,6 +130,8 @@ nuvoton,npct501 i2c trusted platform module (TPM) nuvoton,npct601 i2c trusted platform module (TPM2) nxp,pca9556 Octal SMBus and I2C registered interface nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset +nxp,pcf2127 Real-time clock +nxp,pcf2129 Real-time clock nxp,pcf8563 Real-time clock/calendar nxp,pcf85063 Tiny Real-Time Clock oki,ml86v7667 OKI ML86V7667 video decoder From 2b688d5b146e0bb5accb6c51b257345b7263348d Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 13 Sep 2016 16:09:57 +0800 Subject: [PATCH 035/168] dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen Adds compatible for SoCs which use clockgen, the SoCs are LS1043A, LS1046A, LS2080A. Signed-off-by: Shaohui Xie Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/clock/qoriq-clock.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 16a3ec433119..df9cb5ac5f72 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -32,6 +32,9 @@ Required properties: * "fsl,b4420-clockgen" * "fsl,b4860-clockgen" * "fsl,ls1021a-clockgen" + * "fsl,ls1043a-clockgen" + * "fsl,ls1046a-clockgen" + * "fsl,ls2080a-clockgen" Chassis-version clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks From 4afb47445570e0fd5763169c48033c6486aa7709 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 13 Sep 2016 16:09:58 +0800 Subject: [PATCH 036/168] dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a Signed-off-by: Shaohui Xie Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt index 032a7606b862..fc33ca01e9ba 100644 --- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt @@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller Required properties: - reg: Physical base address and size of the controller's register area. - compatible: Compatibility string. Must be 'fsl,-ahci', where - chip could be ls1021a, ls2080a, ls1043a etc. + chip could be ls1021a, ls1043a, ls1046a, ls2080a etc. - clocks: Input clock specifier. Refer to common clock bindings. - interrupts: Interrupt specifier. Refer to interrupt binding. From 8126d88162a5cef24b7d8106b45185bcb3fd3fe8 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 13 Sep 2016 16:09:59 +0800 Subject: [PATCH 037/168] arm64: dts: add QorIQ LS1046A SoC support LS1046A is an SoC with 4 ARMv8 A72 cores and most other IP blocks are similar to LS1043A which also complies to Freescale Chassis 2.1 spec. Created LS1046A SoC DTSI file to be included by board level DTS files. Signed-off-by: Horia Geant? Signed-off-by: Mihai Bantea Signed-off-by: Chenhui Zhao Signed-off-by: Gong Qianyu Signed-off-by: Minghuan Lian Signed-off-by: Hou Zhiqiang Signed-off-by: Mingkai Hu Signed-off-by: Shaohui Xie Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 515 ++++++++++++++++++ 1 file changed, 515 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi new file mode 100644 index 000000000000..38806ca53829 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -0,0 +1,515 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2016, Freescale Semiconductor, Inc. + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +/ { + compatible = "fsl,ls1046a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + crypto = &crypto; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0>; + clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x1>; + clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x2>; + clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x3>; + clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + idle-states { + /* + * PSCI node is not added default, U-boot will add missing + * parts if it determines to use PSCI. + */ + entry-method = "arm,psci"; + + CPU_PH20: cpu-ph20 { + compatible = "arm,idle-state"; + idle-state-name = "PH20"; + arm,psci-suspend-param = <0x00010000>; + entry-latency-us = <1000>; + exit-latency-us = <1000>; + min-residency-us = <3000>; + }; + }; + + memory@80000000 { + device_type = "memory"; + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + reboot { + compatible ="syscon-reboot"; + regmap = <&dcfg>; + offset = <0xb0>; + mask = <0x02>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + gic: interrupt-controller@1400000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1410000 0 0x10000>, /* GICD */ + <0x0 0x1420000 0 0x20000>, /* GICC */ + <0x0 0x1440000 0 0x20000>, /* GICH */ + <0x0 0x1460000 0 0x20000>; /* GICV */ + interrupts = ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ddr: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = ; + big-endian; + }; + + ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = ; + }; + + qspi: quadspi@1550000 { + compatible = "fsl,ls1021a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clock-names = "qspi_en", "qspi"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + fsl,qspi-has-second-chip; + status = "disabled"; + }; + + esdhc: esdhc@1560000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = ; + clock-frequency = <0>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + big-endian; + bus-width = <4>; + }; + + scfg: scfg@1570000 { + compatible = "fsl,ls1046a-scfg", "syscon"; + reg = <0x0 0x1570000 0x0 0x10000>; + big-endian; + }; + + crypto: crypto@1700000 { + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", + "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x1700000 0x100000>; + reg = <0x00 0x1700000 0x0 0x100000>; + interrupts = ; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = ; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = ; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + }; + }; + + dcfg: dcfg@1ee0000 { + compatible = "fsl,ls1046a-dcfg", "syscon"; + reg = <0x0 0x1ee0000 0x0 0x10000>; + big-endian; + }; + + clockgen: clocking@1ee1000 { + compatible = "fsl,ls1046a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + dspi: dspi@2100000 { + compatible = "fsl,ls1021a-v1.0-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = ; + clock-names = "dspi"; + clocks = <&clockgen 4 1>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + dmas = <&edma0 1 39>, + <&edma0 1 38>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + i2c2: i2c@21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21a0000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + i2c3: i2c@21b0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21b0000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0500 0x0 0x100>; + interrupts = ; + clocks = <&clockgen 4 1>; + }; + + duart1: serial@21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0600 0x0 0x100>; + interrupts = ; + clocks = <&clockgen 4 1>; + }; + + duart2: serial@21d0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0500 0x0 0x100>; + interrupts = ; + clocks = <&clockgen 4 1>; + }; + + duart3: serial@21d0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0600 0x0 0x100>; + interrupts = ; + clocks = <&clockgen 4 1>; + }; + + gpio0: gpio@2300000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = ; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + wdog0: watchdog@2ad0000 { + compatible = "fsl,imx21-wdt"; + reg = <0x0 0x2ad0000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + big-endian; + }; + + edma0: edma@2c00000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x0 0x2c00000 0x0 0x10000>, + <0x0 0x2c10000 0x0 0x10000>, + <0x0 0x2c20000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + big-endian; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clockgen 4 1>, + <&clockgen 4 1>; + }; + + usb0: usb@2f00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = ; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + }; + + usb1: usb@3000000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = ; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + }; + + usb2: usb@3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = ; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1046a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + }; + }; +}; From a135b28f23ebed74b30232d83c9fd39e57fe4c8a Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 13 Sep 2016 16:10:00 +0800 Subject: [PATCH 038/168] Documentation: DT: Add entry for QorIQ LS1046A-RDB board Signed-off-by: Shaohui Xie Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index a81277fdc7bc..d6acdb3c77ef 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -155,6 +155,10 @@ LS1046A SoC Required root node properties: - compatible = "fsl,ls1046a"; +LS1046A ARMv8 based RDB Board +Required root node properties: + - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; + LS2080A SoC Required root node properties: - compatible = "fsl,ls2080a"; From 796b436034fbbb3c03b7dd9a6b4adfdcfd57cc1a Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 13 Sep 2016 16:10:01 +0800 Subject: [PATCH 039/168] arm64: dts: add LS1046A-RDB board support The LS1046A reference design board (RDB) is a high-performance computing, evaluation, and development platform that supports the LS1046A SoC. Signed-off-by: Mingkai Hu Signed-off-by: Shaohui Xie Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 150 ++++++++++++++++++ 2 files changed, 151 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 1b7783db7de4..9c81b9e48de5 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -1,5 +1,6 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts new file mode 100644 index 000000000000..d1ccc000d05a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -0,0 +1,150 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2016, Freescale Semiconductor, Inc. + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "fsl-ls1046a.dtsi" + +/ { + model = "LS1046A RDB Board"; + compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; + + aliases { + serial0 = &duart0; + serial1 = &duart1; + serial2 = &duart2; + serial3 = &duart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + temp-sensor@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + + eeprom@56 { + compatible = "atmel,24c512"; + reg = <0x52>; + }; + + eeprom@57 { + compatible = "atmel,24c512"; + reg = <0x53>; + }; +}; + +&i2c3 { + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NAND Flashe and CPLD on board */ + ranges = <0x0 0x0 0x0 0x7e800000 0x00010000 + 0x2 0x0 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + nand@0,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x10000>; + }; + + cpld: board-control@2,0 { + compatible = "fsl,ls1046ardb-cpld"; + reg = <0x2 0x0 0x0000100>; + }; +}; + +&qspi { + num-cs = <2>; + bus-num = <0>; + status = "okay"; + + qflash0: s25fs512s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + }; + + qflash1: s25fs512s@1 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <1>; + }; +}; From 74b037026b9b4e8024a1d7af656f367a7b285074 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 13 Sep 2016 16:10:02 +0800 Subject: [PATCH 040/168] Documentation: DT: Add entry for QorIQ LS1046A-QDS board Signed-off-by: Shaohui Xie Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index d6acdb3c77ef..d6ee9c6e1dbb 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -155,6 +155,10 @@ LS1046A SoC Required root node properties: - compatible = "fsl,ls1046a"; +LS1046A ARMv8 based QDS Board +Required root node properties: + - compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; + LS1046A ARMv8 based RDB Board Required root node properties: - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; From b20ca2af125a2bf9c8dd7cc7241b878a346692f1 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 13 Sep 2016 16:10:03 +0800 Subject: [PATCH 041/168] arm64: dts: add LS1046A-QDS board support The LS1046A QorIQ development system (QDS) board is a high-performance computing, evaluation, development, and test platform supporting the LS1046A SoC. Signed-off-by: Shaohui Xie Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/fsl-ls1046a-qds.dts | 212 ++++++++++++++++++ 2 files changed, 213 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 9c81b9e48de5..66027181fba4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -1,5 +1,6 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts new file mode 100644 index 000000000000..290e5b014414 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts @@ -0,0 +1,212 @@ +/* + * Device Tree Include file for Freescale Layerscape-1046A family SoC. + * + * Copyright 2016, Freescale Semiconductor, Inc. + * + * Shaohui Xie + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "fsl-ls1046a.dtsi" + +/ { + model = "LS1046A QDS Board"; + compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &duart0; + serial1 = &duart1; + serial2 = &duart2; + serial3 = &duart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a11", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst25wf040b", "jedec,spi-nor"; + spi-cpol; + spi-cpha; + reg = <1>; + spi-max-frequency = <10000000>; + }; + + flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "en25s64", "jedec,spi-nor"; + spi-cpol; + spi-cpha; + reg = <2>; + spi-max-frequency = <10000000>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + pca9547@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + /* IRQ10_B */ + interrupts = <0 150 0x4>; + }; + + eeprom@56 { + compatible = "atmel,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "atmel,24c512"; + reg = <0x57>; + }; + + temp-sensor@4c { + compatible = "adi,adt7461a"; + reg = <0x4c>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x1 0x0 0x0 0x7e800000 0x00010000 + 0x2 0x0 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@1,0 { + compatible = "fsl,ifc-nand"; + reg = <0x1 0x0 0x10000>; + }; + + fpga: board-control@2,0 { + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis"; + reg = <0x2 0x0 0x0000100>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&qspi { + num-cs = <2>; + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; From 392ce382743b847eded4b40990de4e78a5eb494d Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Thu, 13 Oct 2016 20:31:21 +0800 Subject: [PATCH 042/168] arm64: dts: zx: Add clock controller nodes Add clock controller nodes, including one top controller two low speed controllers and one audio controller. Signed-off-by: Jun Nie Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/zte/zx296718.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi index a223066f24ce..7a1aed70dbc0 100644 --- a/arch/arm64/boot/dts/zte/zx296718.dtsi +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi @@ -284,9 +284,33 @@ dma: dma-controller@1460000 { dma-requests = <32>; }; + lsp0crm: clock-controller@1420000 { + compatible = "zte,zx296718-lsp0crm"; + reg = <0x01420000 0x1000>; + #clock-cells = <1>; + }; + + lsp1crm: clock-controller@1430000 { + compatible = "zte,zx296718-lsp1crm"; + reg = <0x01430000 0x1000>; + #clock-cells = <1>; + }; + + topcrm: clock-controller@1461000 { + compatible = "zte,zx296718-topcrm"; + reg = <0x01461000 0x1000>; + #clock-cells = <1>; + }; + sysctrl: sysctrl@1463000 { compatible = "zte,zx296718-sysctrl", "syscon"; reg = <0x1463000 0x1000>; }; + + audiocrm: clock-controller@1480000 { + compatible = "zte,zx296718-audiocrm"; + reg = <0x01480000 0x1000>; + #clock-cells = <1>; + }; }; }; From 1a2c9221df645870560ae04cdc0bac6d25c86b31 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 30 Aug 2016 14:09:29 -0700 Subject: [PATCH 043/168] arm64: dts: qcom: msm8916: Add Hexagon SMD edge Add the Hexagon SMD edge, so that QRTR is probed when the Hexagon is booted. Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 466ca5705c99..4f1fa18a341e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -848,6 +848,14 @@ smd_rpm_regulators: pm8916-regulators { }; }; }; + + hexagon { + interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; + + qcom,smd-edge = <0>; + qcom,ipc = <&apcs 8 12>; + qcom,remote-pid = <1>; + }; }; hexagon-smp2p { From 2b98ce134078848e2baf17eef10ee455b7b86996 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 30 Aug 2016 14:09:30 -0700 Subject: [PATCH 044/168] arm64: dts: qcom: msm8916: Add Hexagon PIL node The Hexagon core on the msm8916 provides services for audio control, audio output, sensors and the Hexagon SDK. The Hexagon remoteproc node allows us to boot this core. Although its part of the core platform its left disabled as it will crash without the rmtfs QMI service and we do not yet handle crashes gracefully. Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 45 ++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 4f1fa18a341e..04cde24f9786 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -77,7 +77,7 @@ rfsa@867e00000 { no-map; }; - mpss@86800000 { + mpss_mem: mpss@86800000 { reg = <0x0 0x86800000 0x0 0x2b00000>; no-map; }; @@ -801,6 +801,49 @@ dsi_phy0: dsi-phy@1a98300 { clock-names = "iface_clk"; }; }; + + + hexagon@4080000 { + compatible = "qcom,q6v5-pil"; + reg = <0x04080000 0x100>, + <0x04020000 0x040>; + + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc 0 24 1>, + <&hexagon_smp2p_in 0 0>, + <&hexagon_smp2p_in 1 0>, + <&hexagon_smp2p_in 2 0>, + <&hexagon_smp2p_in 3 0>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>; + clock-names = "iface", "bus", "mem"; + + qcom,smem-states = <&hexagon_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&scm 0>; + reset-names = "mss_restart"; + + mx-supply = <&pm8916_l3>; + pll-supply = <&pm8916_l7>; + + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; + + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { + memory-region = <&mpss_mem>; + }; + }; }; smd { From 50784e61032d89cbbc46ed73a5fb15f27940b947 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 16 Sep 2016 18:41:21 +0100 Subject: [PATCH 045/168] dts: arm64: db820c: add pmic pins specific dts file This patch adds pmic specific dts which are configured specially for db820c. One of such pin is GPIO_F on the Low Speed expansion which has default output voltage of 2.7v. This patch fixes setup for that pin to have an output voltage of 1.8v to comply with 96boards LS expansion specs. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross --- .../boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 2 ++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi new file mode 100644 index 000000000000..0938191c012f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi @@ -0,0 +1,15 @@ + +#include +&pm8994_gpios { + + pinctrl-names = "default"; + pinctrl-0 = <&ls_exp_gpio_f>; + + ls_exp_gpio_f: pm8916_mpp4 { + pinconf { + pins = "gpio5"; + output-low; + power-source = ; // 1.8V + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index afb218cffc60..422959b87d12 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -12,7 +12,9 @@ */ #include "msm8996.dtsi" +#include "pm8994.dtsi" #include "apq8096-db820c-pins.dtsi" +#include "apq8096-db820c-pmic-pins.dtsi" / { aliases { From 4f24450c6e580ac8591942c8bf65355a06b44635 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 24 Oct 2016 17:09:50 +0200 Subject: [PATCH 046/168] ARM64: dts: bcm2835: Fix bcm2837 compatible string MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit bcm2837-rpi-3-b.dts, its only in-tree user, was overriding it as "brcm,bcm2837" already. Fixes: 9d56c22a7861 ("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.") Cc: Stephen Warren Signed-off-by: Andreas Färber Signed-off-by: Eric Anholt --- arch/arm64/boot/dts/broadcom/bcm2837.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi index 8216bbb29fe0..c1f719b7097a 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi @@ -1,7 +1,7 @@ #include "bcm283x.dtsi" / { - compatible = "brcm,bcm2836"; + compatible = "brcm,bcm2837"; soc { ranges = <0x7e000000 0x3f000000 0x1000000>, From a733c81115da9aa501f3cd918fe5b9f3bbe03b11 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 17 Oct 2016 23:29:02 +0300 Subject: [PATCH 047/168] dt-bindings: media: renesas-fcp: Remove SoC-specific compatible strings The FCP IP cores include a version register that identifies which SoC model the IP is integrated in. SoC-specific compatible strings are not needed. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/media/renesas,fcp.txt | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/media/renesas,fcp.txt b/Documentation/devicetree/bindings/media/renesas,fcp.txt index 27f9b8e459ac..3ec91803ba58 100644 --- a/Documentation/devicetree/bindings/media/renesas,fcp.txt +++ b/Documentation/devicetree/bindings/media/renesas,fcp.txt @@ -11,15 +11,9 @@ are paired with. These DT bindings currently support the FCPV and FCPF. - compatible: Must be one or more of the following - - "renesas,r8a7795-fcpv" for R8A7795 (R-Car H3) compatible 'FCP for VSP' - - "renesas,r8a7795-fcpf" for R8A7795 (R-Car H3) compatible 'FCP for FDP' - "renesas,fcpv" for generic compatible 'FCP for VSP' - "renesas,fcpf" for generic compatible 'FCP for FDP' - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first, followed by the - family-specific and/or generic versions. - - reg: the register base and size for the device registers - clocks: Reference to the functional clock @@ -32,7 +26,7 @@ Device node example ------------------- fcpvd1: fcp@fea2f000 { - compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + compatible = "renesas,fcpv"; reg = <0 0xfea2f000 0 0x200>; clocks = <&cpg CPG_MOD 602>; power-domains = <&sysc R8A7795_PD_A3VP>; From ab33da0bd8f9b6a8b16a61bb5baae365a87cd52c Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 17 Oct 2016 23:29:03 +0300 Subject: [PATCH 048/168] arm64: dts: r8a7795: Remove FCP SoC-specific compatible strings The SoC-specific compatible strings have been removed from the FCP DT bindings, removed them from the device tree. Signed-off-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 8c15040f2540..681f54422375 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1306,28 +1306,28 @@ vspbc: vsp@fe920000 { }; fcpvb1: fcp@fe92f000 { - compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + compatible = "renesas,fcpv"; reg = <0 0xfe92f000 0 0x200>; clocks = <&cpg CPG_MOD 606>; power-domains = <&sysc R8A7795_PD_A3VP>; }; fcpf0: fcp@fe950000 { - compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; + compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; clocks = <&cpg CPG_MOD 615>; power-domains = <&sysc R8A7795_PD_A3VP>; }; fcpf1: fcp@fe951000 { - compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; + compatible = "renesas,fcpf"; reg = <0 0xfe951000 0 0x200>; clocks = <&cpg CPG_MOD 614>; power-domains = <&sysc R8A7795_PD_A3VP>; }; fcpf2: fcp@fe952000 { - compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; + compatible = "renesas,fcpf"; reg = <0 0xfe952000 0 0x200>; clocks = <&cpg CPG_MOD 613>; power-domains = <&sysc R8A7795_PD_A3VP>; @@ -1344,7 +1344,7 @@ vspbd: vsp@fe960000 { }; fcpvb0: fcp@fe96f000 { - compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + compatible = "renesas,fcpv"; reg = <0 0xfe96f000 0 0x200>; clocks = <&cpg CPG_MOD 607>; power-domains = <&sysc R8A7795_PD_A3VP>; @@ -1361,7 +1361,7 @@ vspi0: vsp@fe9a0000 { }; fcpvi0: fcp@fe9af000 { - compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + compatible = "renesas,fcpv"; reg = <0 0xfe9af000 0 0x200>; clocks = <&cpg CPG_MOD 611>; power-domains = <&sysc R8A7795_PD_A3VP>; @@ -1378,7 +1378,7 @@ vspi1: vsp@fe9b0000 { }; fcpvi1: fcp@fe9bf000 { - compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + compatible = "renesas,fcpv"; reg = <0 0xfe9bf000 0 0x200>; clocks = <&cpg CPG_MOD 610>; power-domains = <&sysc R8A7795_PD_A3VP>; @@ -1395,7 +1395,7 @@ vspi2: vsp@fe9c0000 { }; fcpvi2: fcp@fe9cf000 { - compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + compatible = "renesas,fcpv"; reg = <0 0xfe9cf000 0 0x200>; clocks = <&cpg CPG_MOD 609>; power-domains = <&sysc R8A7795_PD_A3VP>; @@ -1412,7 +1412,7 @@ vspd0: vsp@fea20000 { }; fcpvd0: fcp@fea27000 { - compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + compatible = "renesas,fcpv"; reg = <0 0xfea27000 0 0x200>; clocks = <&cpg CPG_MOD 603>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -1429,7 +1429,7 @@ vspd1: vsp@fea28000 { }; fcpvd1: fcp@fea2f000 { - compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + compatible = "renesas,fcpv"; reg = <0 0xfea2f000 0 0x200>; clocks = <&cpg CPG_MOD 602>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -1446,7 +1446,7 @@ vspd2: vsp@fea30000 { }; fcpvd2: fcp@fea37000 { - compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + compatible = "renesas,fcpv"; reg = <0 0xfea37000 0 0x200>; clocks = <&cpg CPG_MOD 601>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -1463,7 +1463,7 @@ vspd3: vsp@fea38000 { }; fcpvd3: fcp@fea3f000 { - compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + compatible = "renesas,fcpv"; reg = <0 0xfea3f000 0 0x200>; clocks = <&cpg CPG_MOD 600>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; From a513cf1e645785cd119676aea4aa00c4e1e0c7b3 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Wed, 17 Aug 2016 10:08:05 +0200 Subject: [PATCH 049/168] arm64: dts: r8a7796: add SDHI nodes Add SDHI nodes to the DT of the r8a7796 SoC. Based on the DT of the r8a7795 SoC. Signed-off-by: Simon Horman Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 40 ++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 9217da983525..6ec988c78ff8 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -251,5 +251,45 @@ scif2: serial@e6e88000 { power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; }; }; From 0d326927f9d77ed3da39a8c2da6ad8470f05002f Mon Sep 17 00:00:00 2001 From: Ziyuan Xu Date: Sun, 30 Oct 2016 10:57:25 +0800 Subject: [PATCH 050/168] arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399 There is a 'cpu-id' field in efuse, export it for other drivers reference. Signed-off-by: Ziyuan Xu Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 76b28649f0b0..cbb7f8bb131c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1023,6 +1023,9 @@ efuse0: efuse@ff690000 { clock-names = "pclk_efuse"; /* Data cells */ + cpu_id: cpu-id@7 { + reg = <0x07 0x10>; + }; cpub_leakage: cpu-leakage@17 { reg = <0x17 0x1>; }; From 6bc37fac30cf01c39feb17834090089304bd1d31 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 18 Jan 2016 10:24:31 +0000 Subject: [PATCH 051/168] arm64: dts: add Allwinner A64 SoC .dtsi The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores and the typical tablet / TV box peripherals. The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of the peripherals and the memory map. Although the cores are proper 64-bit ones, the whole SoC is actually limited to 4GB (including all the supported DRAM), so we use 32-bit address and size cells. This has the nice feature of us being able to reuse the DT for 32-bit kernels as well. This .dtsi lists the hardware that we support so far. Signed-off-by: Andre Przywara Acked-by: Rob Herring Acked-by: Chen-Yu Tsai [Maxime: Convert to CCU binding, drop the MMC support for now] Signed-off-by: Maxime Ripard --- .../devicetree/bindings/arm/sunxi.txt | 1 + MAINTAINERS | 1 + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 263 ++++++++++++++++++ 3 files changed, 265 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index 3975d0a0e4c2..4d6467cc2aa2 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,4 +14,5 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h3 allwinner,sun9i-a80 + allwinner,sun50i-a64 nextthing,gr8 diff --git a/MAINTAINERS b/MAINTAINERS index 1cd38a7e0064..86488e92655f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1019,6 +1019,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained N: sun[x456789]i F: arch/arm/boot/dts/ntc-gr8* +F: arch/arm64/boot/dts/allwinner/ ARM/Allwinner SoC Clock Support M: Emilio López diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi new file mode 100644 index 000000000000..3d70be3a0049 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * based on the Allwinner H3 dtsi: + * Copyright (C) 2015 Jens Kuske + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + }; + }; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ccu: clock@01c20000 { + compatible = "allwinner,sun50i-a64-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun50i-a64-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = , + , + ; + clocks = <&ccu CLK_BUS_PIO>; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + i2c1_pins: i2c1_pins { + pins = "PH2", "PH3"; + function = "i2c1"; + }; + + uart0_pins_a: uart0@0 { + pins = "PB8", "PB9"; + function = "uart0"; + }; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + rtc: rtc@1f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = , + ; + }; + }; +}; From bc13d8feb6dc97651ff0e87bafa1e7c63655acfe Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 17 Feb 2016 01:03:46 +0000 Subject: [PATCH 052/168] Documentation: devicetree: add vendor prefix for Pine64 Signed-off-by: Andre Przywara Acked-by: Rob Herring Acked-by: Chen-Yu Tsai [Maxime: Change title prefix to match the usual style] Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index f0a48ea78659..6edd2fe46275 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -208,6 +208,7 @@ parade Parade Technologies Inc. pericom Pericom Technology Inc. phytec PHYTEC Messtechnik GmbH picochip Picochip Ltd +pine64 Pine64 pixcir PIXCIR MICROELECTRONICS Co., Ltd plathome Plat'Home Co., Ltd. plda PLDA From 4e3886081848b7ea16452a92c4324acaab644d49 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 19 Jan 2016 10:36:39 +0000 Subject: [PATCH 053/168] arm64: dts: add Pine64 support The Pine64 is a cost-efficient development board based on the Allwinner A64 SoC. There are three models: the basic version with Fast Ethernet and 512 MB of DRAM (Pine64) and two Pine64+ versions, which both feature Gigabit Ethernet and additional connectors for touchscreens and a camera. Or as my son put it: "Those are smaller and these are missing." ;-) The two Pine64+ models just differ in the amount of DRAM (1GB vs. 2GB). Since U-Boot will figure out the right size for us and patches the DT accordingly we just need to provide one DT for the Pine64+. Signed-off-by: Andre Przywara [Maxime: Removed the common DTSI and include directly the pine64 DTS] Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/allwinner/Makefile | 5 ++ .../dts/allwinner/sun50i-a64-pine64-plus.dts | 50 +++++++++++++ .../boot/dts/allwinner/sun50i-a64-pine64.dts | 74 +++++++++++++++++++ 4 files changed, 130 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/Makefile create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 6684f97c2722..080232b0270e 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,4 +1,5 @@ dts-dirs += al +dts-dirs += allwinner dts-dirs += altera dts-dirs += amd dts-dirs += amlogic diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile new file mode 100644 index 000000000000..1e29a5ae8282 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -0,0 +1,5 @@ +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts new file mode 100644 index 000000000000..790d14daaa6a --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun50i-a64-pine64.dts" + +/ { + model = "Pine64+"; + compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; + + /* TODO: Camera, Ethernet PHY, touchscreen, etc. */ +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts new file mode 100644 index 000000000000..47095909d9d6 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +/ { + model = "Pine64"; + compatible = "pine64,pine64", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +&i2c1_pins { + bias-pull-up; +}; From 5f04c4cfcc92c4de7453037ed2549a96f63ec5a0 Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Thu, 3 Nov 2016 15:39:07 +0900 Subject: [PATCH 054/168] arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi Signed-off-by: Jaehoon Chung Signed-off-by: Seung-Woo Kim Signed-off-by: Joonyoung Shim Signed-off-by: Inki Dae Signed-off-by: Jonghwa Lee Signed-off-by: Beomho Seo Signed-off-by: Jaewon Kim Signed-off-by: Hyungwon Hwang Signed-off-by: Inha Song Signed-off-by: Ingi kim Signed-off-by: Marek Szyprowski Signed-off-by: Andrzej Hajda Signed-off-by: Sylwester Nawrocki Reviewed-by: Javier Martinez Canillas Tested-by: Andi Shyti Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/exynos5433-pinctrl.dtsi | 794 ++++++++++ .../exynos5433-tmu-g3d-sensor-conf.dtsi | 23 + .../exynos/exynos5433-tmu-sensor-conf.dtsi | 22 + .../arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 296 ++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1356 +++++++++++++++++ 5 files changed, 2491 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi new file mode 100644 index 000000000000..796881310bf6 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -0,0 +1,794 @@ +/* + * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * Chanwoo Choi + * + * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define PIN_PULL_NONE 0 +#define PIN_PULL_DOWN 1 +#define PIN_PULL_UP 3 + +#define PIN_DRV_LV1 0 +#define PIN_DRV_LV2 2 +#define PIN_DRV_LV3 1 +#define PIN_DRV_LV4 3 + +#define PIN_IN 0 +#define PIN_OUT 1 +#define PIN_FUNC1 2 + +#define PIN(_func, _pin, _pull, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = ; \ + samsung,pin-pud = ; \ + samsung,pin-drv = ; \ + } + +&pinctrl_alive { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , , , + , , , + , ; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , , , + , , , + , ; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf4: gpf4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf5: gpf5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_aud { + gpz0: gpz0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpz1: gpz1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", + "gpz0-4", "gpz0-5", "gpz0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + pcm0_bus: pcm0-bus { + samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + uart_aud_bus: uart-aud-bus { + samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_cpif { + gpv6: gpv6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_ese { + gpj2: gpj2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_finger { + gpd5: gpd5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c6_bus: hs-i2c6-bus { + samsung,pins = "gpd5-3", "gpd5-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_fsys { + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr4: gpr4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr0: gpr0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr1: gpr1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr2: gpr2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr3: gpr3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpr0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpr0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + + sd0_qrdy: sd0-qrdy { + samsung,pins = "gpr0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpr1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpr2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpr2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpr3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + pcie_bus: pcie_bus { + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpr4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpr4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpr4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk_output: sd2-clk-output { + samsung,pins = "gpr4-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_cmd_output: sd2-cmd-output { + samsung,pins = "gpr4-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; +}; + +&pinctrl_imem { + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_nfc { + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c4_bus: hs-i2c4-bus { + samsung,pins = "gpj0-1", "gpj0-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_peric { + gpv7: gpv7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd4: gpd4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd8: gpd8 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd6: gpd6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd7: gpd7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c8_bus: hs-i2c8-bus { + samsung,pins = "gpb0-1", "gpb0-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c9_bus: hs-i2c9-bus { + samsung,pins = "gpb0-3", "gpb0-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", + "gpd4-3", "gpd4-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", + "gpd4-3", "gpd4-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpd4-3", "gpd4-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + fimc_is_spi_pin0: fimc-is-spi-pin0 { + samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_spi_pin1: fimc-is-spi-pin1 { + samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_bus: uart0-bus { + samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + hs_i2c2_bus: hs-i2c2-bus { + samsung,pins = "gpd0-3", "gpd0-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart2_bus: uart2-bus { + samsung,pins = "gpd1-5", "gpd1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + uart1_bus: uart1-bus { + samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + hs_i2c3_bus: hs-i2c3-bus { + samsung,pins = "gpd1-3", "gpd1-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c0_bus: hs-i2c0-bus { + samsung,pins = "gpd2-1", "gpd2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c1_bus: hs-i2c1-bus { + samsung,pins = "gpd2-3", "gpd2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpd2-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpd2-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpd2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpd2-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c7_bus: hs-i2c7-bus { + samsung,pins = "gpd2-7", "gpd2-6"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c10_bus: hs-i2c10-bus { + samsung,pins = "gpg3-1", "gpg3-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c11_bus: hs-i2c11-bus { + samsung,pins = "gpg3-3", "gpg3-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi3_bus: spi3-bus { + samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi4_bus: spi4-bus { + samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + fimc_is_uart: fimc-is-uart { + samsung,pins = "gpc1-1", "gpc0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch0_i2c: fimc-is-ch0_i2c { + samsung,pins = "gpc2-1", "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch0_mclk: fimc-is-ch0_mclk { + samsung,pins = "gpd7-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch1_i2c: fimc-is-ch1-i2c { + samsung,pins = "gpc2-3", "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch1_mclk: fimc-is-ch1-mclk { + samsung,pins = "gpd7-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch2_i2c: fimc-is-ch2-i2c { + samsung,pins = "gpc2-5", "gpc2-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch2_mclk: fimc-is-ch2-mclk { + samsung,pins = "gpd7-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_touch { + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c5_bus: hs-i2c5-bus { + samsung,pins = "gpj1-1", "gpj1-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi new file mode 100644 index 000000000000..9be2978f1b9a --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi @@ -0,0 +1,23 @@ +/* + * Device tree sources for Exynos5433 TMU sensor configuration + * + * Copyright (c) 2016 Jonghwa Lee + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#thermal-sensor-cells = <0>; +samsung,tmu_gain = <8>; +samsung,tmu_reference_voltage = <23>; +samsung,tmu_noise_cancel_mode = <4>; +samsung,tmu_efuse_value = <75>; +samsung,tmu_min_efuse_value = <40>; +samsung,tmu_max_efuse_value = <150>; +samsung,tmu_first_point_trim = <25>; +samsung,tmu_second_point_trim = <85>; +samsung,tmu_default_temp_offset = <50>; +samsung,tmu_mux_addr = <6>; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi new file mode 100644 index 000000000000..125fe58d77ce --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi @@ -0,0 +1,22 @@ +/* + * Device tree sources for Exynos5433 TMU sensor configuration + * + * Copyright (c) 2016 Chanwoo Choi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#thermal-sensor-cells = <0>; +samsung,tmu_gain = <8>; +samsung,tmu_reference_voltage = <16>; +samsung,tmu_noise_cancel_mode = <4>; +samsung,tmu_efuse_value = <75>; +samsung,tmu_min_efuse_value = <40>; +samsung,tmu_max_efuse_value = <150>; +samsung,tmu_first_point_trim = <25>; +samsung,tmu_second_point_trim = <85>; +samsung,tmu_default_temp_offset = <50>; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi new file mode 100644 index 000000000000..ceaa05145b8a --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi @@ -0,0 +1,296 @@ +/* + * Device tree sources for Exynos5433 thermal zone + * + * Copyright (c) 2016 Chanwoo Choi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +/ { +thermal-zones { + atlas0_thermal: atlas0-thermal { + thermal-sensors = <&tmu_atlas0>; + polling-delay-passive = <0>; + polling-delay = <0>; + trips { + atlas0_alert_0: atlas0-alert-0 { + temperature = <65000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas0_alert_1: atlas0-alert-1 { + temperature = <70000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas0_alert_2: atlas0-alert-2 { + temperature = <75000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas0_alert_3: atlas0-alert-3 { + temperature = <80000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas0_alert_4: atlas0-alert-4 { + temperature = <85000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas0_alert_5: atlas0-alert-5 { + temperature = <90000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas0_alert_6: atlas0-alert-6 { + temperature = <95000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + /* Set maximum frequency as 1800MHz */ + trip = <&atlas0_alert_0>; + cooling-device = <&cpu4 1 2>; + }; + map1 { + /* Set maximum frequency as 1700MHz */ + trip = <&atlas0_alert_1>; + cooling-device = <&cpu4 2 3>; + }; + map2 { + /* Set maximum frequency as 1600MHz */ + trip = <&atlas0_alert_2>; + cooling-device = <&cpu4 3 4>; + }; + map3 { + /* Set maximum frequency as 1500MHz */ + trip = <&atlas0_alert_3>; + cooling-device = <&cpu4 4 5>; + }; + map4 { + /* Set maximum frequency as 1400MHz */ + trip = <&atlas0_alert_4>; + cooling-device = <&cpu4 5 7>; + }; + map5 { + /* Set maximum frequencyas 1200MHz */ + trip = <&atlas0_alert_5>; + cooling-device = <&cpu4 7 9>; + }; + map6 { + /* Set maximum frequency as 1000MHz */ + trip = <&atlas0_alert_6>; + cooling-device = <&cpu4 9 14>; + }; + }; + }; + + atlas1_thermal: atlas1-thermal { + thermal-sensors = <&tmu_atlas1>; + polling-delay-passive = <0>; + polling-delay = <0>; + trips { + atlas1_alert_0: atlas1-alert-0 { + temperature = <65000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas1_alert_1: atlas1-alert-1 { + temperature = <70000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas1_alert_2: atlas1-alert-2 { + temperature = <75000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas1_alert_3: atlas1-alert-3 { + temperature = <80000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas1_alert_4: atlas1-alert-4 { + temperature = <85000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas1_alert_5: atlas1-alert-5 { + temperature = <90000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + atlas1_alert_6: atlas1-alert-6 { + temperature = <95000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + }; + }; + + g3d_thermal: g3d-thermal { + thermal-sensors = <&tmu_g3d>; + polling-delay-passive = <0>; + polling-delay = <0>; + trips { + g3d_alert_0: g3d-alert-0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + g3d_alert_1: g3d-alert-1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + g3d_alert_2: g3d-alert-2 { + temperature = <80000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + g3d_alert_3: g3d-alert-3 { + temperature = <85000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + g3d_alert_4: g3d-alert-4 { + temperature = <90000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + g3d_alert_5: g3d-alert-5 { + temperature = <95000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + g3d_alert_6: g3d-alert-6 { + temperature = <100000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + }; + }; + + apollo_thermal: apollo-thermal { + thermal-sensors = <&tmu_apollo>; + polling-delay-passive = <0>; + polling-delay = <0>; + trips { + apollo_alert_0: apollo-alert-0 { + temperature = <65000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + apollo_alert_1: apollo-alert-1 { + temperature = <70000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + apollo_alert_2: apollo-alert-2 { + temperature = <75000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + apollo_alert_3: apollo-alert-3 { + temperature = <80000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + apollo_alert_4: apollo-alert-4 { + temperature = <85000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + apollo_alert_5: apollo-alert-5 { + temperature = <90000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + apollo_alert_6: apollo-alert-6 { + temperature = <95000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + /* Set maximum frequency as 1200MHz */ + trip = <&apollo_alert_2>; + cooling-device = <&cpu0 1 2>; + }; + map1 { + /* Set maximum frequency as 1100MHz */ + trip = <&apollo_alert_3>; + cooling-device = <&cpu0 2 3>; + }; + map2 { + /* Set maximum frequency as 1000MHz */ + trip = <&apollo_alert_4>; + cooling-device = <&cpu0 3 4>; + }; + map3 { + /* Set maximum frequency as 900MHz */ + trip = <&apollo_alert_5>; + cooling-device = <&cpu0 4 5>; + }; + map4 { + /* Set maximum frequency as 800MHz */ + trip = <&apollo_alert_6>; + cooling-device = <&cpu0 5 9>; + }; + }; + }; + + isp_thermal: isp-thermal { + thermal-sensors = <&tmu_isp>; + polling-delay-passive = <0>; + polling-delay = <0>; + trips { + isp_alert_0: isp-alert-0 { + temperature = <80000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + isp_alert_1: isp-alert-1 { + temperature = <85000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + isp_alert_2: isp-alert-2 { + temperature = <90000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + isp_alert_3: isp-alert-3 { + temperature = <95000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + isp_alert_4: isp-alert-4 { + temperature = <100000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + isp_alert_5: isp-alert-5 { + temperature = <105000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + isp_alert_6: isp-alert-6 { + temperature = <110000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "active"; + }; + }; + }; +}; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi new file mode 100644 index 000000000000..1188630823a7 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -0,0 +1,1356 @@ +/* + * Samsung's Exynos5433 SoC device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * + * Samsung's Exynos5433 SoC device nodes are listed in this file. + * Exynos5433 based board files can include this file and provide + * values for board specific bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos5433 SoC. As device tree coverage for Exynos5433 increases, + * additional nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +/ { + compatible = "samsung,exynos5433"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x100>; + clock-frequency = <1300000000>; + clocks = <&cmu_apollo CLK_SCLK_APOLLO>; + clock-names = "apolloclk"; + operating-points-v2 = <&cluster_a53_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x101>; + clock-frequency = <1300000000>; + operating-points-v2 = <&cluster_a53_opp_table>; + #cooling-cells = <2>; + }; + + cpu2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x102>; + clock-frequency = <1300000000>; + operating-points-v2 = <&cluster_a53_opp_table>; + #cooling-cells = <2>; + }; + + cpu3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x103>; + clock-frequency = <1300000000>; + operating-points-v2 = <&cluster_a53_opp_table>; + #cooling-cells = <2>; + }; + + cpu4: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x0>; + clock-frequency = <1900000000>; + clocks = <&cmu_atlas CLK_SCLK_ATLAS>; + clock-names = "atlasclk"; + operating-points-v2 = <&cluster_a57_opp_table>; + #cooling-cells = <2>; + }; + + cpu5: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x1>; + clock-frequency = <1900000000>; + operating-points-v2 = <&cluster_a57_opp_table>; + #cooling-cells = <2>; + }; + + cpu6: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x2>; + clock-frequency = <1900000000>; + operating-points-v2 = <&cluster_a57_opp_table>; + #cooling-cells = <2>; + }; + + cpu7: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x3>; + clock-frequency = <1900000000>; + operating-points-v2 = <&cluster_a57_opp_table>; + #cooling-cells = <2>; + }; + }; + + cluster_a53_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <925000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <975000>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + }; + opp@900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1050000>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1075000>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1112500>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1112500>; + }; + opp@1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1150000>; + }; + }; + + cluster_a57_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <900000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <912500>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <912500>; + }; + opp@900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <937500>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <975000>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1012500>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1037500>; + }; + opp@1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1062500>; + }; + opp@1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1087500>; + }; + opp@1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1125000>; + }; + opp@1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1137500>; + }; + opp@1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1175000>; + }; + opp@1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1212500>; + }; + opp@1900000000 { + opp-hz = /bits/ 64 <1900000000>; + opp-microvolt = <1262500>; + }; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x400>; /* SWRESET */ + mask = <0x1>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x18000000>; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + xxti: xxti { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + }; + + cmu_top: clock-controller@10030000 { + compatible = "samsung,exynos5433-cmu-top"; + reg = <0x10030000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll", + "sclk_mfc_pll", + "sclk_bus_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>, + <&cmu_mif CLK_SCLK_MFC_PLL>, + <&cmu_mif CLK_SCLK_BUS_PLL>; + }; + + cmu_cpif: clock-controller@10fc0000 { + compatible = "samsung,exynos5433-cmu-cpif"; + reg = <0x10fc0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk"; + clocks = <&xxti>; + }; + + cmu_mif: clock-controller@105b0000 { + compatible = "samsung,exynos5433-cmu-mif"; + reg = <0x105b0000 0x2000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>; + }; + + cmu_peric: clock-controller@14c80000 { + compatible = "samsung,exynos5433-cmu-peric"; + reg = <0x14c80000 0x1000>; + #clock-cells = <1>; + }; + + cmu_peris: clock-controller@0x10040000 { + compatible = "samsung,exynos5433-cmu-peris"; + reg = <0x10040000 0x1000>; + #clock-cells = <1>; + }; + + cmu_fsys: clock-controller@156e0000 { + compatible = "samsung,exynos5433-cmu-fsys"; + reg = <0x156e0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_ufs_mphy", + "div_aclk_fsys_200", + "sclk_pcie_100_fsys", + "sclk_ufsunipro_fsys", + "sclk_mmc2_fsys", + "sclk_mmc1_fsys", + "sclk_mmc0_fsys", + "sclk_usbhost30_fsys", + "sclk_usbdrd30_fsys"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_UFS_MPHY>, + <&cmu_top CLK_DIV_ACLK_FSYS_200>, + <&cmu_top CLK_SCLK_PCIE_100_FSYS>, + <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, + <&cmu_top CLK_SCLK_MMC2_FSYS>, + <&cmu_top CLK_SCLK_MMC1_FSYS>, + <&cmu_top CLK_SCLK_MMC0_FSYS>, + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_top CLK_SCLK_USBDRD30_FSYS>; + }; + + cmu_g2d: clock-controller@12460000 { + compatible = "samsung,exynos5433-cmu-g2d"; + reg = <0x12460000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_g2d_266", + "aclk_g2d_400"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_G2D_266>, + <&cmu_top CLK_ACLK_G2D_400>; + }; + + cmu_disp: clock-controller@13b90000 { + compatible = "samsung,exynos5433-cmu-disp"; + reg = <0x13b90000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_dsim1_disp", + "sclk_dsim0_disp", + "sclk_dsd_disp", + "sclk_decon_tv_eclk_disp", + "sclk_decon_vclk_disp", + "sclk_decon_eclk_disp", + "sclk_decon_tv_vclk_disp", + "aclk_disp_333"; + clocks = <&xxti>, + <&cmu_mif CLK_SCLK_DSIM1_DISP>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_mif CLK_SCLK_DSD_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, + <&cmu_mif CLK_ACLK_DISP_333>; + }; + + cmu_aud: clock-controller@114c0000 { + compatible = "samsung,exynos5433-cmu-aud"; + reg = <0x114c0000 0x1000>; + #clock-cells = <1>; + }; + + cmu_bus0: clock-controller@13600000 { + compatible = "samsung,exynos5433-cmu-bus0"; + reg = <0x13600000 0x1000>; + #clock-cells = <1>; + + clock-names = "aclk_bus0_400"; + clocks = <&cmu_top CLK_ACLK_BUS0_400>; + }; + + cmu_bus1: clock-controller@14800000 { + compatible = "samsung,exynos5433-cmu-bus1"; + reg = <0x14800000 0x1000>; + #clock-cells = <1>; + + clock-names = "aclk_bus1_400"; + clocks = <&cmu_top CLK_ACLK_BUS1_400>; + }; + + cmu_bus2: clock-controller@13400000 { + compatible = "samsung,exynos5433-cmu-bus2"; + reg = <0x13400000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_bus2_400"; + clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; + }; + + cmu_g3d: clock-controller@14aa0000 { + compatible = "samsung,exynos5433-cmu-g3d"; + reg = <0x14aa0000 0x2000>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_g3d_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; + }; + + cmu_gscl: clock-controller@13cf0000 { + compatible = "samsung,exynos5433-cmu-gscl"; + reg = <0x13cf0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_gscl_111", + "aclk_gscl_333"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_GSCL_111>, + <&cmu_top CLK_ACLK_GSCL_333>; + }; + + cmu_apollo: clock-controller@11900000 { + compatible = "samsung,exynos5433-cmu-apollo"; + reg = <0x11900000 0x2000>; + #clock-cells = <1>; + + clock-names = "oscclk", "sclk_bus_pll_apollo"; + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; + }; + + cmu_atlas: clock-controller@11800000 { + compatible = "samsung,exynos5433-cmu-atlas"; + reg = <0x11800000 0x2000>; + #clock-cells = <1>; + + clock-names = "oscclk", "sclk_bus_pll_atlas"; + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; + }; + + cmu_mscl: clock-controller@105d0000 { + compatible = "samsung,exynos5433-cmu-mscl"; + reg = <0x150d0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_jpeg_mscl", + "aclk_mscl_400"; + clocks = <&xxti>, + <&cmu_top CLK_SCLK_JPEG_MSCL>, + <&cmu_top CLK_ACLK_MSCL_400>; + }; + + cmu_mfc: clock-controller@15280000 { + compatible = "samsung,exynos5433-cmu-mfc"; + reg = <0x15280000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_mfc_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; + }; + + cmu_hevc: clock-controller@14f80000 { + compatible = "samsung,exynos5433-cmu-hevc"; + reg = <0x14f80000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_hevc_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; + }; + + cmu_isp: clock-controller@146d0000 { + compatible = "samsung,exynos5433-cmu-isp"; + reg = <0x146d0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_isp_dis_400", + "aclk_isp_400"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_ISP_DIS_400>, + <&cmu_top CLK_ACLK_ISP_400>; + }; + + cmu_cam0: clock-controller@120d0000 { + compatible = "samsung,exynos5433-cmu-cam0"; + reg = <0x120d0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_cam0_333", + "aclk_cam0_400", + "aclk_cam0_552"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_CAM0_333>, + <&cmu_top CLK_ACLK_CAM0_400>, + <&cmu_top CLK_ACLK_CAM0_552>; + }; + + cmu_cam1: clock-controller@145d0000 { + compatible = "samsung,exynos5433-cmu-cam1"; + reg = <0x145d0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_isp_uart_cam1", + "sclk_isp_spi1_cam1", + "sclk_isp_spi0_cam1", + "aclk_cam1_333", + "aclk_cam1_400", + "aclk_cam1_552"; + clocks = <&xxti>, + <&cmu_top CLK_SCLK_ISP_UART_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, + <&cmu_top CLK_ACLK_CAM1_333>, + <&cmu_top CLK_ACLK_CAM1_400>, + <&cmu_top CLK_ACLK_CAM1_552>; + }; + + tmu_atlas0: tmu@10060000 { + compatible = "samsung,exynos5433-tmu"; + reg = <0x10060000 0x200>; + interrupts = ; + clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, + <&cmu_peris CLK_SCLK_TMU0>; + clock-names = "tmu_apbif", "tmu_sclk"; + #include "exynos5433-tmu-sensor-conf.dtsi" + status = "disabled"; + }; + + tmu_atlas1: tmu@10068000 { + compatible = "samsung,exynos5433-tmu"; + reg = <0x10068000 0x200>; + interrupts = ; + clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, + <&cmu_peris CLK_SCLK_TMU0>; + clock-names = "tmu_apbif", "tmu_sclk"; + #include "exynos5433-tmu-sensor-conf.dtsi" + status = "disabled"; + }; + + tmu_g3d: tmu@10070000 { + compatible = "samsung,exynos5433-tmu"; + reg = <0x10070000 0x200>; + interrupts = ; + clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, + <&cmu_peris CLK_SCLK_TMU1>; + clock-names = "tmu_apbif", "tmu_sclk"; + #include "exynos5433-tmu-g3d-sensor-conf.dtsi" + status = "disabled"; + }; + + tmu_apollo: tmu@10078000 { + compatible = "samsung,exynos5433-tmu"; + reg = <0x10078000 0x200>; + interrupts = ; + clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, + <&cmu_peris CLK_SCLK_TMU1>; + clock-names = "tmu_apbif", "tmu_sclk"; + #include "exynos5433-tmu-sensor-conf.dtsi" + status = "disabled"; + }; + + tmu_isp: tmu@1007c000 { + compatible = "samsung,exynos5433-tmu"; + reg = <0x1007c000 0x200>; + interrupts = ; + clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, + <&cmu_peris CLK_SCLK_TMU1>; + clock-names = "tmu_apbif", "tmu_sclk"; + #include "exynos5433-tmu-sensor-conf.dtsi" + status = "disabled"; + }; + + mct@101c0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101c0000 0x800>; + interrupts = , , + , , + , , + , , + , , + , ; + clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>; + clock-names = "fin_pll", "mct"; + }; + + pinctrl_alive: pinctrl@10580000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10580000 0x1a20>, <0x11090000 0x100>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + interrupts = ; + }; + }; + + pinctrl_aud: pinctrl@114b0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x114b0000 0x1000>; + interrupts = ; + }; + + pinctrl_cpif: pinctrl@10fe0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10fe0000 0x1000>; + interrupts = ; + }; + + pinctrl_ese: pinctrl@14ca0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14ca0000 0x1000>; + interrupts = ; + }; + + pinctrl_finger: pinctrl@14cb0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14cb0000 0x1000>; + interrupts = ; + }; + + pinctrl_fsys: pinctrl@15690000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x15690000 0x1000>; + interrupts = ; + }; + + pinctrl_imem: pinctrl@11090000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x11090000 0x1000>; + interrupts = ; + }; + + pinctrl_nfc: pinctrl@14cd0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14cd0000 0x1000>; + interrupts = ; + }; + + pinctrl_peric: pinctrl@14cc0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14cc0000 0x1100>; + interrupts = ; + }; + + pinctrl_touch: pinctrl@14ce0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14ce0000 0x1100>; + interrupts = ; + }; + + pmu_system_controller: system-controller@105c0000 { + compatible = "samsung,exynos5433-pmu", "syscon"; + reg = <0x105c0000 0x5008>; + #clock-cells = <1>; + clock-names = "clkout16"; + clocks = <&xxti>; + }; + + gic: interrupt-controller@11001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x11001000 0x1000>, + <0x11002000 0x2000>, + <0x11004000 0x2000>, + <0x11006000 0x2000>; + interrupts = ; + }; + + mipi_phy: video-phy@105c0710 { + compatible = "samsung,exynos5433-mipi-video-phy"; + #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,cam0-sysreg = <&syscon_cam0>; + samsung,cam1-sysreg = <&syscon_cam1>; + samsung,disp-sysreg = <&syscon_disp>; + }; + + decon: decon@13800000 { + compatible = "samsung,exynos5433-decon"; + reg = <0x13800000 0x2104>; + clocks = <&cmu_disp CLK_PCLK_DECON>, + <&cmu_disp CLK_ACLK_DECON>, + <&cmu_disp CLK_ACLK_SMMU_DECON0X>, + <&cmu_disp CLK_ACLK_XIU_DECON0X>, + <&cmu_disp CLK_PCLK_SMMU_DECON0X>, + <&cmu_disp CLK_SCLK_DECON_VCLK>, + <&cmu_disp CLK_SCLK_DECON_ECLK>; + clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", + "aclk_xiu_decon0x", "pclk_smmu_decon0x", + "sclk_decon_vclk", "sclk_decon_eclk"; + interrupt-names = "fifo", "vsync", "lcd_sys"; + interrupts = , , + ; + samsung,disp-sysreg = <&syscon_disp>; + status = "disabled"; + iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; + iommu-names = "m0", "m1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + decon_to_mic: endpoint { + remote-endpoint = + <&mic_to_decon>; + }; + }; + }; + }; + + dsi: dsi@13900000 { + compatible = "samsung,exynos5433-mipi-dsi"; + reg = <0x13900000 0xC0>; + interrupts = ; + phys = <&mipi_phy 1>; + phy-names = "dsim"; + clocks = <&cmu_disp CLK_PCLK_DSIM0>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, + <&cmu_disp CLK_SCLK_DSIM0>; + clock-names = "bus_clk", + "phyclk_mipidphy0_bitclkdiv8", + "phyclk_mipidphy0_rxclkesc0", + "sclk_rgb_vclk_to_dsim0", + "sclk_mipi"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_to_mic: endpoint { + remote-endpoint = <&mic_to_dsi>; + }; + }; + }; + }; + + mic: mic@13930000 { + compatible = "samsung,exynos5433-mic"; + reg = <0x13930000 0x48>; + clocks = <&cmu_disp CLK_PCLK_MIC0>, + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; + clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; + samsung,disp-syscon = <&syscon_disp>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mic_to_decon: endpoint { + remote-endpoint = + <&decon_to_mic>; + }; + }; + + port@1 { + reg = <1>; + mic_to_dsi: endpoint { + remote-endpoint = <&dsi_to_mic>; + }; + }; + }; + }; + + syscon_disp: syscon@13b80000 { + compatible = "syscon"; + reg = <0x13b80000 0x1010>; + }; + + syscon_cam0: syscon@120f0000 { + compatible = "syscon"; + reg = <0x120f0000 0x1020>; + }; + + syscon_cam1: syscon@145f0000 { + compatible = "syscon"; + reg = <0x145f0000 0x1038>; + }; + + sysmmu_decon0x: sysmmu@0x13a00000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13a00000 0x1000>; + interrupts = ; + clock-names = "pclk", "aclk"; + clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>, + <&cmu_disp CLK_ACLK_SMMU_DECON0X>; + #iommu-cells = <0>; + }; + + sysmmu_decon1x: sysmmu@0x13a10000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13a10000 0x1000>; + interrupts = ; + clock-names = "pclk", "aclk"; + clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>, + <&cmu_disp CLK_ACLK_SMMU_DECON1X>; + #iommu-cells = <0>; + }; + + serial_0: serial@14c10000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14c10000 0x100>; + interrupts = ; + clocks = <&cmu_peric CLK_PCLK_UART0>, + <&cmu_peric CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + status = "disabled"; + }; + + serial_1: serial@14c20000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14c20000 0x100>; + interrupts = ; + clocks = <&cmu_peric CLK_PCLK_UART1>, + <&cmu_peric CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus>; + status = "disabled"; + }; + + serial_2: serial@14c30000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14c30000 0x100>; + interrupts = ; + clocks = <&cmu_peric CLK_PCLK_UART2>, + <&cmu_peric CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_bus>; + status = "disabled"; + }; + + spi_0: spi@14d20000 { + compatible = "samsung,exynos5433-spi"; + reg = <0x14d20000 0x100>; + interrupts = ; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI0>, + <&cmu_peric CLK_SCLK_SPI0>, + <&cmu_peric CLK_SCLK_IOCLK_SPI0>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + num-cs = <1>; + status = "disabled"; + }; + + spi_1: spi@14d30000 { + compatible = "samsung,exynos5433-spi"; + reg = <0x14d30000 0x100>; + interrupts = ; + dmas = <&pdma0 11>, <&pdma0 10>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI1>, + <&cmu_peric CLK_SCLK_SPI1>, + <&cmu_peric CLK_SCLK_IOCLK_SPI1>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + num-cs = <1>; + status = "disabled"; + }; + + spi_2: spi@14d40000 { + compatible = "samsung,exynos5433-spi"; + reg = <0x14d40000 0x100>; + interrupts = ; + dmas = <&pdma0 13>, <&pdma0 12>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI2>, + <&cmu_peric CLK_SCLK_SPI2>, + <&cmu_peric CLK_SCLK_IOCLK_SPI2>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + num-cs = <1>; + status = "disabled"; + }; + + spi_3: spi@14d50000 { + compatible = "samsung,exynos5433-spi"; + reg = <0x14d50000 0x100>; + interrupts = ; + dmas = <&pdma0 23>, <&pdma0 22>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI3>, + <&cmu_peric CLK_SCLK_SPI3>, + <&cmu_peric CLK_SCLK_IOCLK_SPI3>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_bus>; + num-cs = <1>; + status = "disabled"; + }; + + spi_4: spi@14d00000 { + compatible = "samsung,exynos5433-spi"; + reg = <0x14d00000 0x100>; + interrupts = ; + dmas = <&pdma0 25>, <&pdma0 24>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI4>, + <&cmu_peric CLK_SCLK_SPI4>, + <&cmu_peric CLK_SCLK_IOCLK_SPI4>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_bus>; + num-cs = <1>; + status = "disabled"; + }; + + adc: adc@14d10000 { + compatible = "samsung,exynos7-adc"; + reg = <0x14d10000 0x100>; + interrupts = ; + clock-names = "adc"; + clocks = <&cmu_peric CLK_PCLK_ADCIF>; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + + pwm: pwm@14dd0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x14dd0000 0x100>; + interrupts = , , + , , + ; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + clocks = <&cmu_peric CLK_PCLK_PWM>; + clock-names = "timers"; + #pwm-cells = <3>; + status = "disabled"; + }; + + hsi2c_0: hsi2c@14e40000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e40000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c0_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C0>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_1: hsi2c@14e50000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e50000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c1_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C1>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_2: hsi2c@14e60000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e60000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c2_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C2>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_3: hsi2c@14e70000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e70000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c3_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C3>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_4: hsi2c@14ec0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ec0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c4_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C4>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_5: hsi2c@14ed0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ed0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c5_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C5>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_6: hsi2c@14ee0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ee0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c6_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C6>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_7: hsi2c@14ef0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ef0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c7_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C7>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_8: hsi2c@14d90000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14d90000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c8_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C8>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_9: hsi2c@14da0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14da0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c9_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C9>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_10: hsi2c@14de0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14de0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c10_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C10>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_11: hsi2c@14df0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14df0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c11_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C11>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + usbdrd30: usb@15400000 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, + <&cmu_fsys CLK_SCLK_USBDRD30>; + clock-names = "usbdrd30", "usbdrd30_susp_clk"; + assigned-clocks = + <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, + <&cmu_top CLK_MOUT_SCLK_USBDRD30>, + <&cmu_top CLK_DIV_SCLK_USBDRD30>; + assigned-clock-parents = + <&cmu_top CLK_SCLK_USBDRD30_FSYS>, + <&cmu_top CLK_MOUT_BUS_PLL_USER>; + assigned-clock-rates = <0>, <0>, <66700000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + dwc3@15400000 { + compatible = "snps,dwc3"; + reg = <0x15400000 0x10000>; + interrupts = ; + phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usbdrd30_phy: phy@15500000 { + compatible = "samsung,exynos5433-usbdrd-phy"; + reg = <0x15500000 0x100>; + clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>, + <&cmu_fsys CLK_SCLK_USBDRD30>; + clock-names = "phy", "ref", "phy_utmi", "phy_pipe", + "itp"; + assigned-clocks = + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>; + assigned-clock-parents = + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>; + #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; + }; + + usbhost30_phy: phy@15580000 { + compatible = "samsung,exynos5433-usbdrd-phy"; + reg = <0x15580000 0x100>; + clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>, + <&cmu_fsys CLK_SCLK_USBHOST30>; + clock-names = "phy", "ref", "phy_utmi", "phy_pipe", + "itp"; + assigned-clocks = + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>; + assigned-clock-parents = + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; + #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; + }; + + usbhost30: usb@15a00000 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, + <&cmu_fsys CLK_SCLK_USBHOST30>; + clock-names = "usbdrd30", "usbdrd30_susp_clk"; + assigned-clocks = + <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, + <&cmu_top CLK_MOUT_SCLK_USBHOST30>, + <&cmu_top CLK_DIV_SCLK_USBHOST30>; + assigned-clock-parents = + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_top CLK_MOUT_BUS_PLL_USER>; + assigned-clock-rates = <0>, <0>, <66700000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + usbdrd_dwc3_0: dwc3@15a00000 { + compatible = "snps,dwc3"; + reg = <0x15a00000 0x10000>; + interrupts = ; + phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + mshc_0: mshc@15540000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15540000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC0>, + <&cmu_fsys CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_1: mshc@15550000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15550000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC1>, + <&cmu_fsys CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_2: mshc@15560000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15560000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC2>, + <&cmu_fsys CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma0: pdma@15610000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x15610000 0x1000>; + interrupts = ; + clocks = <&cmu_fsys CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@15600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x15600000 0x1000>; + interrupts = ; + clocks = <&cmu_fsys CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + + audio-subsystem@11400000 { + compatible = "samsung,exynos5433-lpass"; + reg = <0x11400000 0x100>, <0x11500000 0x08>; + samsung,pmu-syscon = <&pmu_system_controller>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + adma: adma@11420000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11420000 0x1000>; + interrupts = ; + clocks = <&cmu_aud CLK_ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + i2s0: i2s0@11440000 { + compatible = "samsung,exynos7-i2s"; + reg = <0x11440000 0x100>; + dmas = <&adma 0 &adma 2>; + dma-names = "tx", "rx"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, + <&cmu_aud CLK_SCLK_AUD_I2S>, + <&cmu_aud CLK_SCLK_I2S_BCLK>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + status = "disabled"; + }; + + serial_3: serial@11460000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x11460000 0x100>; + interrupts = ; + clocks = <&cmu_aud CLK_PCLK_AUD_UART>, + <&cmu_aud CLK_SCLK_AUD_UART>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_aud_bus>; + status = "disabled"; + }; + }; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; + +#include "exynos5433-pinctrl.dtsi" +#include "exynos5433-tmu.dtsi" From 01e5d235215209e7a63a143c337c7c7be11930b8 Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Thu, 3 Nov 2016 15:39:08 +0900 Subject: [PATCH 055/168] arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board This patch adds the Device Tree source for Exynos5433-based Samsung TM2 board. This patch adds support for following devices: 1. basic SoC - Initial booting for Samsung Exynos5433 SoC - DRAM LPDDR3 (3GB) - eMMC (32GB) - ARM architecture timer 2. power management devices - Sasmung S2MPS13 PMIC for the power supply - CPUFREQ for big.LITTLE cores - TMU for big.LITTLE cores and GPU - ADC with thermistor to measure the temperature of AP/Battery/Charger - Maxim MAX77843 Interface PMIC (MUIC/Haptic/Regulator) 3. sound devices - I2S for sound bus - LPASS for sound power control - Wolfson WM5110 for sound codec - Maxim MAX98504 for speaker amplifier - TM2 ASoC Machine device driver node 3. display devices - DECON, DSI and MIC for the panel output 4. USB devices - USB 3.0 DRD (Dual Role Device) - USB 3.0 Host controller 5. storage devices - MSHC (Mobile Storage Host Controller) for eMMC device 6. misc devices - gpio-keys (power, volume up/down, home key) - PWM (Pulse Width Modulation Timer) Signed-off-by: Chanwoo Choi Signed-off-by: Jaehoon Chung Signed-off-by: Seung-Woo Kim Signed-off-by: Joonyoung Shim Signed-off-by: Inki Dae Signed-off-by: Jonghwa Lee Signed-off-by: Beomho Seo Signed-off-by: Jaewon Kim Signed-off-by: Hyungwon Hwang Signed-off-by: Inha Song Signed-off-by: Ingi kim Signed-off-by: Marek Szyprowski Signed-off-by: Andrzej Hajda Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Andi Shyti Signed-off-by: Krzysztof Kozlowski --- .../bindings/arm/samsung/samsung-boards.txt | 1 + arch/arm64/boot/dts/exynos/Makefile | 4 +- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 974 ++++++++++++++++++ 3 files changed, 978 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2.dts diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index 0ea7f14ef294..339af8b9cdc5 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -15,6 +15,7 @@ Required root node properties: - "samsung,xyref5260" - for Exynos5260-based Samsung board. - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. + - "samsung,tm2" - for Exynos5433-based Samsung TM2 board. - "samsung,sd5v1" - for Exynos5440-based Samsung board. - "samsung,ssdk5440" - for Exynos5440-based Samsung board. diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index 50c9b9383cfa..947c750acba1 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -1,4 +1,6 @@ -dtb-$(CONFIG_ARCH_EXYNOS) += exynos7-espresso.dtb +dtb-$(CONFIG_ARCH_EXYNOS) += \ + exynos5433-tm2.dtb \ + exynos7-espresso.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts new file mode 100644 index 000000000000..9ea3f32bae9e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -0,0 +1,974 @@ +/* + * SAMSUNG Exynos5433 TM2 board device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * + * Device tree source file for Samsung's TM2 board which is based on + * Samsung Exynos5433 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include "exynos5433.dtsi" +#include +#include +#include +#include + +/ { + model = "Samsung TM2 board"; + compatible = "samsung,tm2", "samsung,exynos5433"; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_aud; + pinctrl2 = &pinctrl_cpif; + pinctrl3 = &pinctrl_ese; + pinctrl4 = &pinctrl_finger; + pinctrl5 = &pinctrl_fsys; + pinctrl6 = &pinctrl_imem; + pinctrl7 = &pinctrl_nfc; + pinctrl8 = &pinctrl_peric; + pinctrl9 = &pinctrl_touch; + serial0 = &serial_0; + serial1 = &serial_1; + serial2 = &serial_2; + serial3 = &serial_3; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + }; + + chosen { + stdout-path = &serial_1; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x0 0x20000000 0x0 0xc0000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power-key { + gpios = <&gpa2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power key"; + debounce-interval = <10>; + }; + + volume-up-key { + gpios = <&gpa2 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume-up key"; + debounce-interval = <10>; + }; + + volume-down-key { + gpios = <&gpa2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume-down key"; + debounce-interval = <10>; + }; + + homepage-key { + gpios = <&gpa0 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "homepage key"; + debounce-interval = <10>; + }; + }; + + i2c_max98504: i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */ + &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max98504: max98504@31 { + compatible = "maxim,max98504"; + reg = <0x31>; + maxim,rx-path = <1>; + maxim,tx-path = <1>; + maxim,tx-channel-mask = <3>; + maxim,tx-channel-source = <2>; + }; + }; + + sound { + compatible = "samsung,tm2-audio"; + audio-codec = <&wm5110>; + i2s-controller = <&i2s0>; + audio-amplifier = <&max98504>; + mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>; + model = "wm5110"; + samsung,audio-routing = + /* Headphone */ + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + /* Speaker */ + "SPK", "SPKOUT", + "SPKOUT", "HPOUT2L", + "SPKOUT", "HPOUT2R", + + /* Receiver */ + "RCV", "HPOUT3L", + "RCV", "HPOUT3R"; + status = "okay"; + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + status = "okay"; + + thermistor-ap { + compatible = "murata,ncp03wf104"; + pullup-uv = <1800000>; + pullup-ohm = <100000>; + pulldown-ohm = <0>; + io-channels = <&adc 0>; + }; + + thermistor-battery { + compatible = "murata,ncp03wf104"; + pullup-uv = <1800000>; + pullup-ohm = <100000>; + pulldown-ohm = <0>; + io-channels = <&adc 1>; + #thermal-sensor-cells = <0>; + }; + + thermistor-charger { + compatible = "murata,ncp03wf104"; + pullup-uv = <1800000>; + pullup-ohm = <100000>; + pulldown-ohm = <0>; + io-channels = <&adc 2>; + }; +}; + +&cpu0 { + cpu-supply = <&buck3_reg>; +}; + +&cpu4 { + cpu-supply = <&buck2_reg>; +}; + +&decon { + status = "okay"; + + i80-if-timings { + }; +}; + +&dsi { + status = "okay"; + vddcore-supply = <&ldo6_reg>; + vddio-supply = <&ldo7_reg>; + samsung,pll-clock-frequency = <24000000>; + pinctrl-names = "default"; + pinctrl-0 = <&te_irq>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out: endpoint { + samsung,burst-clock-frequency = <512000000>; + samsung,esc-clock-frequency = <16000000>; + }; + }; + }; +}; + +&hsi2c_0 { + status = "okay"; + clock-frequency = <2500000>; + + s2mps13-pmic@66 { + compatible = "samsung,s2mps13-pmic"; + interrupt-parent = <&gpa0>; + interrupts = <7 IRQ_TYPE_NONE>; + reg = <0x66>; + samsung,s2mps11-wrstbi-ground; + + s2mps13_osc: clocks { + compatible = "samsung,s2mps13-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps13_ap", "s2mps13_cp", + "s2mps13_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_0.9V_AP"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDDQ_MMC2_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDD1_E_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD10_MIF_PLL_1.0V_AP"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD10_DPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD10_MIPI2L_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD18_MIPI2L_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD18_LLI_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD18_ABB_ETC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDD33_USB30_3.0V_AP"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_INT_M_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD_KFC_M_1.1V_AP"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDD_G3D_M_0.95V_AP"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDDQ_M1_LDO_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDDQ_M2_LDO_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "VDDQ_EFUSE"; + regulator-min-microvolt = <1400000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "V_TFLASH_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo18_reg: LDO18 { + regulator-name = "V_CODEC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "VDDA_1.8V_COMP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo20_reg: LDO20 { + regulator-name = "VCC_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo22_reg: LDO22 { + regulator-name = "CAM_IO_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "CAM_SEN_CORE_1.2V_AP"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + }; + + ldo24_reg: LDO24 { + regulator-name = "VT_CAM_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "CAM_SEN_A2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "CAM_AF_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo27_reg: LDO27 { + regulator-name = "VCC_3.0V_LCD_AP"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo28_reg: LDO28 { + regulator-name = "VCC_1.8V_LCD_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo29_reg: LDO29 { + regulator-name = "VT_CAM_2.8V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo30_reg: LDO30 { + regulator-name = "TSP_AVDD_3.3V_AP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo31_reg: LDO31 { + regulator-name = "TSP_VDD_1.85V_AP"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + ldo32_reg: LDO32 { + regulator-name = "VTOUCH_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "VTOUCH_LED_3.3V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + }; + + ldo34_reg: LDO34 { + regulator-name = "VCC_1.8V_MHL_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <2100000>; + }; + + ldo35_reg: LDO35 { + regulator-name = "OIS_VM_2.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo36_reg: LDO36 { + regulator-name = "VSIL_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo37_reg: LDO37 { + regulator-name = "VF_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo38_reg: LDO38 { + regulator-name = "VCC_3.0V_MOTOR_AP"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo39_reg: LDO39 { + regulator-name = "V_HRM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo40_reg: LDO40 { + regulator-name = "V_HRM_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF_0.9V_AP"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_EGL_1.0V_AP"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_KFC_1.0V_AP"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_INT_0.95V_AP"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_DISP_CAM0_0.9V_AP"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck6_reg: BUCK6 { + regulator-name = "VDD_G3D_0.9V_AP"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck7_reg: BUCK7 { + regulator-name = "VDD_MEM1_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "VDD_LLDO_1.35V_AP"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "VDD_MLDO_2.0V_AP"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_mem2"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + }; + }; +}; + +&hsi2c_8 { + status = "okay"; + + max77843@66 { + compatible = "maxim,max77843"; + interrupt-parent = <&gpa1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reg = <0x66>; + + muic: max77843-muic { + compatible = "maxim,max77843-muic"; + }; + + regulators { + compatible = "maxim,max77843-regulator"; + safeout1_reg: SAFEOUT1 { + regulator-name = "SAFEOUT1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <4950000>; + }; + + safeout2_reg: SAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <4950000>; + }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <100000>; + regulator-max-microamp = <3150000>; + }; + }; + + haptic: max77843-haptic { + compatible = "maxim,max77843-haptic"; + haptic-supply = <&ldo38_reg>; + pwms = <&pwm 0 33670 0>; + pwm-names = "haptic"; + }; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&mshc_0 { + status = "okay"; + num-slots = <1>; + non-removable; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 3>; + samsung,read-strobe-delay = <90>; + fifo-depth = <0x80>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 + &sd0_bus8 &sd0_rdqs>; + bus-width = <8>; + assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>; + assigned-clock-rates = <800000000>; +}; + +&pinctrl_alive { + pinctrl-names = "default"; + pinctrl-0 = <&initial_alive>; + + initial_alive: initial-state { + PIN(IN, gpa0-0, DOWN, LV1); + PIN(IN, gpa0-1, NONE, LV1); + PIN(IN, gpa0-2, DOWN, LV1); + PIN(IN, gpa0-3, NONE, LV1); + PIN(IN, gpa0-4, NONE, LV1); + PIN(IN, gpa0-5, DOWN, LV1); + PIN(IN, gpa0-6, NONE, LV1); + PIN(IN, gpa0-7, NONE, LV1); + + PIN(IN, gpa1-0, UP, LV1); + PIN(IN, gpa1-1, NONE, LV1); + PIN(IN, gpa1-2, NONE, LV1); + PIN(IN, gpa1-3, DOWN, LV1); + PIN(IN, gpa1-4, DOWN, LV1); + PIN(IN, gpa1-5, NONE, LV1); + PIN(IN, gpa1-6, NONE, LV1); + PIN(IN, gpa1-7, NONE, LV1); + + PIN(IN, gpa2-0, NONE, LV1); + PIN(IN, gpa2-1, NONE, LV1); + PIN(IN, gpa2-2, NONE, LV1); + PIN(IN, gpa2-3, DOWN, LV1); + PIN(IN, gpa2-4, NONE, LV1); + PIN(IN, gpa2-5, DOWN, LV1); + PIN(IN, gpa2-6, DOWN, LV1); + PIN(IN, gpa2-7, NONE, LV1); + + PIN(IN, gpa3-0, DOWN, LV1); + PIN(IN, gpa3-1, DOWN, LV1); + PIN(IN, gpa3-2, NONE, LV1); + PIN(IN, gpa3-3, DOWN, LV1); + PIN(IN, gpa3-4, NONE, LV1); + PIN(IN, gpa3-5, DOWN, LV1); + PIN(IN, gpa3-6, DOWN, LV1); + PIN(IN, gpa3-7, DOWN, LV1); + + PIN(IN, gpf1-0, NONE, LV1); + PIN(IN, gpf1-1, NONE, LV1); + PIN(IN, gpf1-2, DOWN, LV1); + PIN(IN, gpf1-4, UP, LV1); + PIN(OUT, gpf1-5, NONE, LV1); + PIN(IN, gpf1-6, DOWN, LV1); + PIN(IN, gpf1-7, DOWN, LV1); + + PIN(IN, gpf2-0, DOWN, LV1); + PIN(IN, gpf2-1, DOWN, LV1); + PIN(IN, gpf2-2, DOWN, LV1); + PIN(IN, gpf2-3, DOWN, LV1); + + PIN(IN, gpf3-0, DOWN, LV1); + PIN(IN, gpf3-1, DOWN, LV1); + PIN(IN, gpf3-2, NONE, LV1); + PIN(IN, gpf3-3, DOWN, LV1); + + PIN(IN, gpf4-0, DOWN, LV1); + PIN(IN, gpf4-1, DOWN, LV1); + PIN(IN, gpf4-2, DOWN, LV1); + PIN(IN, gpf4-3, DOWN, LV1); + PIN(IN, gpf4-4, DOWN, LV1); + PIN(IN, gpf4-5, DOWN, LV1); + PIN(IN, gpf4-6, DOWN, LV1); + PIN(IN, gpf4-7, DOWN, LV1); + + PIN(IN, gpf5-0, DOWN, LV1); + PIN(IN, gpf5-1, DOWN, LV1); + PIN(IN, gpf5-2, DOWN, LV1); + PIN(IN, gpf5-3, DOWN, LV1); + PIN(OUT, gpf5-4, NONE, LV1); + PIN(IN, gpf5-5, DOWN, LV1); + PIN(IN, gpf5-6, DOWN, LV1); + PIN(IN, gpf5-7, DOWN, LV1); + }; + + te_irq: te_irq { + samsung,pins = "gpf1-3"; + samsung,pin-function = <0xf>; + }; +}; + +&pinctrl_cpif { + pinctrl-names = "default"; + pinctrl-0 = <&initial_cpif>; + + initial_cpif: initial-state { + PIN(IN, gpv6-0, DOWN, LV1); + PIN(IN, gpv6-1, DOWN, LV1); + }; +}; + +&pinctrl_ese { + pinctrl-names = "default"; + pinctrl-0 = <&initial_ese>; + + initial_ese: initial-state { + PIN(IN, gpj2-0, DOWN, LV1); + PIN(IN, gpj2-1, DOWN, LV1); + PIN(IN, gpj2-2, DOWN, LV1); + }; +}; + +&pinctrl_fsys { + pinctrl-names = "default"; + pinctrl-0 = <&initial_fsys>; + + initial_fsys: initial-state { + PIN(IN, gpr3-0, NONE, LV1); + PIN(IN, gpr3-1, DOWN, LV1); + PIN(IN, gpr3-2, DOWN, LV1); + PIN(IN, gpr3-3, DOWN, LV1); + PIN(IN, gpr3-7, NONE, LV1); + }; +}; + +&pinctrl_imem { + pinctrl-names = "default"; + pinctrl-0 = <&initial_imem>; + + initial_imem: initial-state { + PIN(IN, gpf0-0, UP, LV1); + PIN(IN, gpf0-1, UP, LV1); + PIN(IN, gpf0-2, DOWN, LV1); + PIN(IN, gpf0-3, UP, LV1); + PIN(IN, gpf0-4, DOWN, LV1); + PIN(IN, gpf0-5, NONE, LV1); + PIN(IN, gpf0-6, DOWN, LV1); + PIN(IN, gpf0-7, UP, LV1); + }; +}; + +&pinctrl_nfc { + pinctrl-names = "default"; + pinctrl-0 = <&initial_nfc>; + + initial_nfc: initial-state { + PIN(IN, gpj0-2, DOWN, LV1); + }; +}; + +&pinctrl_peric { + pinctrl-names = "default"; + pinctrl-0 = <&initial_peric>; + + initial_peric: initial-state { + PIN(IN, gpv7-0, DOWN, LV1); + PIN(IN, gpv7-1, DOWN, LV1); + PIN(IN, gpv7-2, NONE, LV1); + PIN(IN, gpv7-3, DOWN, LV1); + PIN(IN, gpv7-4, DOWN, LV1); + PIN(IN, gpv7-5, DOWN, LV1); + + PIN(IN, gpb0-4, DOWN, LV1); + + PIN(IN, gpc0-2, DOWN, LV1); + PIN(IN, gpc0-5, DOWN, LV1); + PIN(IN, gpc0-7, DOWN, LV1); + + PIN(IN, gpc1-1, DOWN, LV1); + + PIN(IN, gpc3-4, NONE, LV1); + PIN(IN, gpc3-5, NONE, LV1); + PIN(IN, gpc3-6, NONE, LV1); + PIN(IN, gpc3-7, NONE, LV1); + + PIN(OUT, gpg0-0, NONE, LV1); + PIN(FUNC1, gpg0-1, DOWN, LV1); + + PIN(IN, gpd2-5, DOWN, LV1); + + PIN(IN, gpd4-0, NONE, LV1); + PIN(IN, gpd4-1, DOWN, LV1); + PIN(IN, gpd4-2, DOWN, LV1); + PIN(IN, gpd4-3, DOWN, LV1); + PIN(IN, gpd4-4, DOWN, LV1); + + PIN(IN, gpd6-3, DOWN, LV1); + + PIN(IN, gpd8-1, UP, LV1); + + PIN(IN, gpg1-0, DOWN, LV1); + PIN(IN, gpg1-1, DOWN, LV1); + PIN(IN, gpg1-2, DOWN, LV1); + PIN(IN, gpg1-3, DOWN, LV1); + PIN(IN, gpg1-4, DOWN, LV1); + + PIN(IN, gpg2-0, DOWN, LV1); + PIN(IN, gpg2-1, DOWN, LV1); + + PIN(IN, gpg3-0, DOWN, LV1); + PIN(IN, gpg3-1, DOWN, LV1); + PIN(IN, gpg3-5, DOWN, LV1); + PIN(IN, gpg3-7, DOWN, LV1); + }; +}; + +&pinctrl_touch { + pinctrl-names = "default"; + pinctrl-0 = <&initial_touch>; + + initial_touch: initial-state { + PIN(IN, gpj1-2, DOWN, LV1); + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mic { + status = "okay"; + + i80-if-timings { + }; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_3 { + assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>; + assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>; + status = "okay"; +}; + +&spi_1 { + cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + wm5110: wm5110-codec@0 { + compatible = "wlf,wm5110"; + reg = <0x0>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpa0>; + interrupts = <4 IRQ_TYPE_NONE>; + clocks = <&pmu_system_controller 0>, + <&s2mps13_osc S2MPS11_CLK_BT>; + clock-names = "mclk1", "mclk2"; + + gpio-controller; + #gpio-cells = <2>; + + wlf,micd-detect-debounce = <300>; + wlf,micd-bias-start-time = <0x1>; + wlf,micd-rate = <0x7>; + wlf,micd-dbtime = <0x1>; + wlf,micd-force-micbias; + wlf,micd-configs = <0x0 1 0>; + wlf,hpdet-channel = <1>; + wlf,gpsw = <0x1>; + wlf,inmode = <2 0 2 0>; + + wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>; + wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>; + + /* core supplies */ + AVDD-supply = <&ldo18_reg>; + DBVDD1-supply = <&ldo18_reg>; + CPVDD-supply = <&ldo18_reg>; + DBVDD2-supply = <&ldo18_reg>; + DBVDD3-supply = <&ldo18_reg>; + + controller-data { + samsung,spi-feedback-delay = <0>; + }; + }; +}; + +&timer { + clock-frequency = <24000000>; +}; + +&tmu_atlas0 { + vtmu-supply = <&ldo3_reg>; + status = "okay"; +}; + +&tmu_apollo { + vtmu-supply = <&ldo3_reg>; + status = "okay"; +}; + +&tmu_g3d { + vtmu-supply = <&ldo3_reg>; + status = "okay"; +}; + +&usbdrd30 { + vdd33-supply = <&ldo10_reg>; + vdd10-supply = <&ldo6_reg>; + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; +}; + +&usbdrd30_phy { + vbus-supply = <&safeout1_reg>; + status = "okay"; +}; + +&xxti { + clock-frequency = <24000000>; +}; From 8ac46fc57df82efbc19194dddd335b6c7a960c31 Mon Sep 17 00:00:00 2001 From: Chanwoo Choi Date: Thu, 3 Nov 2016 15:39:09 +0900 Subject: [PATCH 056/168] arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board This patch adds the Device Tree source for Exynos5433-based Samsung TM2E board. TM2E board is very similar to the TM2 board so the exynos5433-tm2e.dts includes the TM2 DTS and overrides the differences. Signed-off-by: Chanwoo Choi Signed-off-by: Jaehoon Chung Signed-off-by: Seung-Woo Kim Signed-off-by: Joonyoung Shim Signed-off-by: Inki Dae Signed-off-by: Jonghwa Lee Signed-off-by: Beomho Seo Signed-off-by: Jaewon Kim Signed-off-by: Hyungwon Hwang Signed-off-by: Inha Song Signed-off-by: Ingi kim Signed-off-by: Marek Szyprowski Signed-off-by: Andrzej Hajda Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Javier Martinez Canillas Tested-by: Andi Shyti Signed-off-by: Krzysztof Kozlowski --- .../bindings/arm/samsung/samsung-boards.txt | 1 + arch/arm64/boot/dts/exynos/Makefile | 1 + .../arm64/boot/dts/exynos/exynos5433-tm2e.dts | 41 +++++++++++++++++++ 3 files changed, 43 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index 339af8b9cdc5..c64c7b515777 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -16,6 +16,7 @@ Required root node properties: - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. - "samsung,tm2" - for Exynos5433-based Samsung TM2 board. + - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board. - "samsung,sd5v1" - for Exynos5440-based Samsung board. - "samsung,ssdk5440" - for Exynos5440-based Samsung board. diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index 947c750acba1..7ddea53769a7 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -1,5 +1,6 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \ exynos5433-tm2.dtb \ + exynos5433-tm2e.dtb \ exynos7-espresso.dtb always := $(dtb-y) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts new file mode 100644 index 000000000000..1db4e7f363a9 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts @@ -0,0 +1,41 @@ +/* + * SAMSUNG Exynos5433 TM2E board device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * + * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on + * Samsung Exynos5433 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "exynos5433-tm2.dts" + +/ { + model = "Samsung TM2E board"; + compatible = "samsung,tm2e", "samsung,exynos5433"; +}; + +&ldo23_reg { + regulator-name = "CAM_SEN_CORE_1.025V_AP"; + regulator-max-microvolt = <1050000>; +}; + +&ldo25_reg { + regulator-name = "UNUSED_LDO25"; + regulator-always-off; +}; + +&ldo31_reg { + regulator-name = "TSP_VDD_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&ldo38_reg { + regulator-name = "VCC_3.3V_MOTOR_AP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; From ef4aea97a70013cecb69adf6a9f0d25ab6f11590 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 16 Sep 2016 22:01:13 +0200 Subject: [PATCH 057/168] arm64: dts: exynos: Fix invalid GIC interrupt flags in exynos7 Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and generates an error: genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68) The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Arbitrarily choose level high everywhere hoping it will work on each platform. Reported-by: Marek Szyprowski Reported-by: Alban Browaeys Cc: Marc Zyngier Signed-off-by: Krzysztof Kozlowski Tested-by: Alim Akhtar Reviewed-by: Alim Akhtar --- .../boot/dts/exynos/exynos7-pinctrl.dtsi | 20 ++++-- arch/arm64/boot/dts/exynos/exynos7.dtsi | 69 ++++++++++--------- 2 files changed, 51 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi index f77ddaf21d04..20f10e0f7c77 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi @@ -20,8 +20,14 @@ gpa0: gpa0 { interrupt-controller; interrupt-parent = <&gic>; #interrupt-cells = <2>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 4 IRQ_TYPE_LEVEL_HIGH>, + <0 5 IRQ_TYPE_LEVEL_HIGH>, + <0 6 IRQ_TYPE_LEVEL_HIGH>, + <0 7 IRQ_TYPE_LEVEL_HIGH>; }; gpa1: gpa1 { @@ -31,8 +37,14 @@ gpa1: gpa1 { interrupt-controller; interrupt-parent = <&gic>; #interrupt-cells = <2>; - interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>; }; gpa2: gpa2 { diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 6328a66ed97e..0a80dabfbe95 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -106,7 +106,7 @@ amba { pdma0: pdma@10E10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10E10000 0x1000>; - interrupts = <0 225 0>; + interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_fsys0 ACLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -117,7 +117,7 @@ pdma0: pdma@10E10000 { pdma1: pdma@10EB0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10EB0000 0x1000>; - interrupts = <0 226 0>; + interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_fsys0 ACLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -220,7 +220,7 @@ clock_fsys1: clock-controller@156e0000 { serial_0: serial@13630000 { compatible = "samsung,exynos4210-uart"; reg = <0x13630000 0x100>; - interrupts = <0 440 0>; + interrupts = <0 440 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peric0 PCLK_UART0>, <&clock_peric0 SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; @@ -230,7 +230,7 @@ serial_0: serial@13630000 { serial_1: serial@14c20000 { compatible = "samsung,exynos4210-uart"; reg = <0x14c20000 0x100>; - interrupts = <0 456 0>; + interrupts = <0 456 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peric1 PCLK_UART1>, <&clock_peric1 SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; @@ -240,7 +240,7 @@ serial_1: serial@14c20000 { serial_2: serial@14c30000 { compatible = "samsung,exynos4210-uart"; reg = <0x14c30000 0x100>; - interrupts = <0 457 0>; + interrupts = <0 457 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peric1 PCLK_UART2>, <&clock_peric1 SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; @@ -250,7 +250,7 @@ serial_2: serial@14c30000 { serial_3: serial@14c40000 { compatible = "samsung,exynos4210-uart"; reg = <0x14c40000 0x100>; - interrupts = <0 458 0>; + interrupts = <0 458 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peric1 PCLK_UART3>, <&clock_peric1 SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; @@ -264,62 +264,62 @@ pinctrl_alive: pinctrl@10580000 { wakeup-interrupt-controller { compatible = "samsung,exynos7-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 16 0>; + interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; }; }; pinctrl_bus0: pinctrl@13470000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x13470000 0x1000>; - interrupts = <0 383 0>; + interrupts = <0 383 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_nfc: pinctrl@14cd0000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x14cd0000 0x1000>; - interrupts = <0 473 0>; + interrupts = <0 473 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_touch: pinctrl@14ce0000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x14ce0000 0x1000>; - interrupts = <0 474 0>; + interrupts = <0 474 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_ff: pinctrl@14c90000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x14c90000 0x1000>; - interrupts = <0 475 0>; + interrupts = <0 475 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_ese: pinctrl@14ca0000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x14ca0000 0x1000>; - interrupts = <0 476 0>; + interrupts = <0 476 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_fsys0: pinctrl@10e60000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x10e60000 0x1000>; - interrupts = <0 221 0>; + interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_fsys1: pinctrl@15690000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x15690000 0x1000>; - interrupts = <0 203 0>; + interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_bus1: pinctrl@14870000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x14870000 0x1000>; - interrupts = <0 384 0>; + interrupts = <0 384 IRQ_TYPE_LEVEL_HIGH>; }; hsi2c_0: hsi2c@13640000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13640000 0x1000>; - interrupts = <0 441 0>; + interrupts = <0 441 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -332,7 +332,7 @@ hsi2c_0: hsi2c@13640000 { hsi2c_1: hsi2c@13650000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13650000 0x1000>; - interrupts = <0 442 0>; + interrupts = <0 442 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -345,7 +345,7 @@ hsi2c_1: hsi2c@13650000 { hsi2c_2: hsi2c@14e60000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e60000 0x1000>; - interrupts = <0 459 0>; + interrupts = <0 459 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -358,7 +358,7 @@ hsi2c_2: hsi2c@14e60000 { hsi2c_3: hsi2c@14e70000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e70000 0x1000>; - interrupts = <0 460 0>; + interrupts = <0 460 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -371,7 +371,7 @@ hsi2c_3: hsi2c@14e70000 { hsi2c_4: hsi2c@13660000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13660000 0x1000>; - interrupts = <0 443 0>; + interrupts = <0 443 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -384,7 +384,7 @@ hsi2c_4: hsi2c@13660000 { hsi2c_5: hsi2c@13670000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13670000 0x1000>; - interrupts = <0 444 0>; + interrupts = <0 444 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -397,7 +397,7 @@ hsi2c_5: hsi2c@13670000 { hsi2c_6: hsi2c@14e00000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e00000 0x1000>; - interrupts = <0 461 0>; + interrupts = <0 461 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -410,7 +410,7 @@ hsi2c_6: hsi2c@14e00000 { hsi2c_7: hsi2c@13e10000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13e10000 0x1000>; - interrupts = <0 462 0>; + interrupts = <0 462 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -423,7 +423,7 @@ hsi2c_7: hsi2c@13e10000 { hsi2c_8: hsi2c@14e20000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e20000 0x1000>; - interrupts = <0 463 0>; + interrupts = <0 463 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -436,7 +436,7 @@ hsi2c_8: hsi2c@14e20000 { hsi2c_9: hsi2c@13680000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13680000 0x1000>; - interrupts = <0 445 0>; + interrupts = <0 445 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -449,7 +449,7 @@ hsi2c_9: hsi2c@13680000 { hsi2c_10: hsi2c@13690000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13690000 0x1000>; - interrupts = <0 446 0>; + interrupts = <0 446 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -462,7 +462,7 @@ hsi2c_10: hsi2c@13690000 { hsi2c_11: hsi2c@136a0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x136a0000 0x1000>; - interrupts = <0 447 0>; + interrupts = <0 447 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -499,7 +499,8 @@ reboot: syscon-reboot { rtc: rtc@10590000 { compatible = "samsung,s3c6410-rtc"; reg = <0x10590000 0x100>; - interrupts = <0 355 0>, <0 356 0>; + interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>, + <0 356 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_ccore PCLK_RTC>; clock-names = "rtc"; status = "disabled"; @@ -508,7 +509,7 @@ rtc: rtc@10590000 { watchdog: watchdog@101d0000 { compatible = "samsung,exynos7-wdt"; reg = <0x101d0000 0x100>; - interrupts = <0 110 0>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peris PCLK_WDT>; clock-names = "watchdog"; samsung,syscon-phandle = <&pmu_system_controller>; @@ -517,7 +518,7 @@ watchdog: watchdog@101d0000 { mmc_0: mmc@15740000 { compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = <0 201 0>; + interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x15740000 0x2000>; @@ -530,7 +531,7 @@ mmc_0: mmc@15740000 { mmc_1: mmc@15750000 { compatible = "samsung,exynos7-dw-mshc"; - interrupts = <0 202 0>; + interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x15750000 0x2000>; @@ -543,7 +544,7 @@ mmc_1: mmc@15750000 { mmc_2: mmc@15560000 { compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = <0 216 0>; + interrupts = <0 216 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; reg = <0x15560000 0x2000>; @@ -557,7 +558,7 @@ mmc_2: mmc@15560000 { adc: adc@13620000 { compatible = "samsung,exynos7-adc"; reg = <0x13620000 0x100>; - interrupts = <0 448 0>; + interrupts = <0 448 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peric0 PCLK_ADCIF>; clock-names = "adc"; #io-channel-cells = <1>; @@ -577,7 +578,7 @@ pwm: pwm@136c0000 { tmuctrl_0: tmu@10060000 { compatible = "samsung,exynos7-tmu"; reg = <0x10060000 0x200>; - interrupts = <0 108 0>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_peris PCLK_TMU>, <&clock_peris SCLK_TMU>; clock-names = "tmu_apbif", "tmu_sclk"; From 86bb573d0b2a8e876a12d1348bd0b6e377c1043e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 16 Sep 2016 23:41:56 +0200 Subject: [PATCH 058/168] arm64: dts: exynos: Use human-friendly symbols for interrupt properties in exynos7 Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/exynos7-pinctrl.dtsi | 32 ++++----- arch/arm64/boot/dts/exynos/exynos7.dtsi | 70 +++++++++---------- 2 files changed, 51 insertions(+), 51 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi index 20f10e0f7c77..82321984e1fb 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi @@ -20,14 +20,14 @@ gpa0: gpa0 { interrupt-controller; interrupt-parent = <&gic>; #interrupt-cells = <2>; - interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, - <0 1 IRQ_TYPE_LEVEL_HIGH>, - <0 2 IRQ_TYPE_LEVEL_HIGH>, - <0 3 IRQ_TYPE_LEVEL_HIGH>, - <0 4 IRQ_TYPE_LEVEL_HIGH>, - <0 5 IRQ_TYPE_LEVEL_HIGH>, - <0 6 IRQ_TYPE_LEVEL_HIGH>, - <0 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + , + , + , + , + ; }; gpa1: gpa1 { @@ -37,14 +37,14 @@ gpa1: gpa1 { interrupt-controller; interrupt-parent = <&gic>; #interrupt-cells = <2>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, - <0 9 IRQ_TYPE_LEVEL_HIGH>, - <0 10 IRQ_TYPE_LEVEL_HIGH>, - <0 11 IRQ_TYPE_LEVEL_HIGH>, - <0 12 IRQ_TYPE_LEVEL_HIGH>, - <0 13 IRQ_TYPE_LEVEL_HIGH>, - <0 14 IRQ_TYPE_LEVEL_HIGH>, - <0 15 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + , + , + , + , + ; }; gpa2: gpa2 { diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 0a80dabfbe95..4b5a1eadffb5 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -106,7 +106,7 @@ amba { pdma0: pdma@10E10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10E10000 0x1000>; - interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock_fsys0 ACLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -117,7 +117,7 @@ pdma0: pdma@10E10000 { pdma1: pdma@10EB0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10EB0000 0x1000>; - interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock_fsys0 ACLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -220,7 +220,7 @@ clock_fsys1: clock-controller@156e0000 { serial_0: serial@13630000 { compatible = "samsung,exynos4210-uart"; reg = <0x13630000 0x100>; - interrupts = <0 440 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock_peric0 PCLK_UART0>, <&clock_peric0 SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; @@ -230,7 +230,7 @@ serial_0: serial@13630000 { serial_1: serial@14c20000 { compatible = "samsung,exynos4210-uart"; reg = <0x14c20000 0x100>; - interrupts = <0 456 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock_peric1 PCLK_UART1>, <&clock_peric1 SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; @@ -240,7 +240,7 @@ serial_1: serial@14c20000 { serial_2: serial@14c30000 { compatible = "samsung,exynos4210-uart"; reg = <0x14c30000 0x100>; - interrupts = <0 457 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock_peric1 PCLK_UART2>, <&clock_peric1 SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; @@ -250,7 +250,7 @@ serial_2: serial@14c30000 { serial_3: serial@14c40000 { compatible = "samsung,exynos4210-uart"; reg = <0x14c40000 0x100>; - interrupts = <0 458 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock_peric1 PCLK_UART3>, <&clock_peric1 SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; @@ -264,62 +264,62 @@ pinctrl_alive: pinctrl@10580000 { wakeup-interrupt-controller { compatible = "samsung,exynos7-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; }; pinctrl_bus0: pinctrl@13470000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x13470000 0x1000>; - interrupts = <0 383 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; pinctrl_nfc: pinctrl@14cd0000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x14cd0000 0x1000>; - interrupts = <0 473 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; pinctrl_touch: pinctrl@14ce0000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x14ce0000 0x1000>; - interrupts = <0 474 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; pinctrl_ff: pinctrl@14c90000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x14c90000 0x1000>; - interrupts = <0 475 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; pinctrl_ese: pinctrl@14ca0000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x14ca0000 0x1000>; - interrupts = <0 476 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; pinctrl_fsys0: pinctrl@10e60000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x10e60000 0x1000>; - interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; pinctrl_fsys1: pinctrl@15690000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x15690000 0x1000>; - interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; pinctrl_bus1: pinctrl@14870000 { compatible = "samsung,exynos7-pinctrl"; reg = <0x14870000 0x1000>; - interrupts = <0 384 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; hsi2c_0: hsi2c@13640000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13640000 0x1000>; - interrupts = <0 441 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -332,7 +332,7 @@ hsi2c_0: hsi2c@13640000 { hsi2c_1: hsi2c@13650000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13650000 0x1000>; - interrupts = <0 442 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -345,7 +345,7 @@ hsi2c_1: hsi2c@13650000 { hsi2c_2: hsi2c@14e60000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e60000 0x1000>; - interrupts = <0 459 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -358,7 +358,7 @@ hsi2c_2: hsi2c@14e60000 { hsi2c_3: hsi2c@14e70000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e70000 0x1000>; - interrupts = <0 460 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -371,7 +371,7 @@ hsi2c_3: hsi2c@14e70000 { hsi2c_4: hsi2c@13660000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13660000 0x1000>; - interrupts = <0 443 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -384,7 +384,7 @@ hsi2c_4: hsi2c@13660000 { hsi2c_5: hsi2c@13670000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13670000 0x1000>; - interrupts = <0 444 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -397,7 +397,7 @@ hsi2c_5: hsi2c@13670000 { hsi2c_6: hsi2c@14e00000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e00000 0x1000>; - interrupts = <0 461 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -410,7 +410,7 @@ hsi2c_6: hsi2c@14e00000 { hsi2c_7: hsi2c@13e10000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13e10000 0x1000>; - interrupts = <0 462 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -423,7 +423,7 @@ hsi2c_7: hsi2c@13e10000 { hsi2c_8: hsi2c@14e20000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e20000 0x1000>; - interrupts = <0 463 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -436,7 +436,7 @@ hsi2c_8: hsi2c@14e20000 { hsi2c_9: hsi2c@13680000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13680000 0x1000>; - interrupts = <0 445 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -449,7 +449,7 @@ hsi2c_9: hsi2c@13680000 { hsi2c_10: hsi2c@13690000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x13690000 0x1000>; - interrupts = <0 446 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -462,7 +462,7 @@ hsi2c_10: hsi2c@13690000 { hsi2c_11: hsi2c@136a0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x136a0000 0x1000>; - interrupts = <0 447 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -499,8 +499,8 @@ reboot: syscon-reboot { rtc: rtc@10590000 { compatible = "samsung,s3c6410-rtc"; reg = <0x10590000 0x100>; - interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>, - <0 356 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; clocks = <&clock_ccore PCLK_RTC>; clock-names = "rtc"; status = "disabled"; @@ -509,7 +509,7 @@ rtc: rtc@10590000 { watchdog: watchdog@101d0000 { compatible = "samsung,exynos7-wdt"; reg = <0x101d0000 0x100>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock_peris PCLK_WDT>; clock-names = "watchdog"; samsung,syscon-phandle = <&pmu_system_controller>; @@ -518,7 +518,7 @@ watchdog: watchdog@101d0000 { mmc_0: mmc@15740000 { compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x15740000 0x2000>; @@ -531,7 +531,7 @@ mmc_0: mmc@15740000 { mmc_1: mmc@15750000 { compatible = "samsung,exynos7-dw-mshc"; - interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x15750000 0x2000>; @@ -544,7 +544,7 @@ mmc_1: mmc@15750000 { mmc_2: mmc@15560000 { compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = <0 216 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x15560000 0x2000>; @@ -558,7 +558,7 @@ mmc_2: mmc@15560000 { adc: adc@13620000 { compatible = "samsung,exynos7-adc"; reg = <0x13620000 0x100>; - interrupts = <0 448 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock_peric0 PCLK_ADCIF>; clock-names = "adc"; #io-channel-cells = <1>; @@ -578,7 +578,7 @@ pwm: pwm@136c0000 { tmuctrl_0: tmu@10060000 { compatible = "samsung,exynos7-tmu"; reg = <0x10060000 0x200>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&clock_peris PCLK_TMU>, <&clock_peris SCLK_TMU>; clock-names = "tmu_apbif", "tmu_sclk"; From e2420b92de4941bdca05d7c93acfddb48f036d0b Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 16 Aug 2016 10:55:04 +0200 Subject: [PATCH 059/168] arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3 Enable the exposed SD card slots in the DT of the r8a7796/salvator-x. Based on work for the r8a7795/salvator-x by Ai Kyuse. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a7796-salvator-x.dts | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index 90e9a76c8b30..c946569accb1 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "r8a7796.dtsi" +#include / { model = "Renesas Salvator-X board based on r8a7796"; @@ -29,6 +30,55 @@ memory@48000000 { /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x78000000>; }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi3: regulator-vcc-sdhi3 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI3 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi3: regulator-vccq-sdhi3 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI3 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + }; &pfc { @@ -43,6 +93,16 @@ scif_clk_pins: scif_clk { groups = "scif_clk_a"; function = "scif_clk"; }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + }; }; &extal_clk { @@ -53,6 +113,30 @@ &extalr_clk { clock-frequency = <32768>; }; +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + status = "okay"; +}; + +&sdhi3 { + pinctrl-0 = <&sdhi3_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi3>; + vqmmc-supply = <&vccq_sdhi3>; + cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + status = "okay"; +}; + &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; From af3cf72f5f4b158d34935d6995908989afbe756c Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 13 Sep 2016 12:57:07 +0200 Subject: [PATCH 060/168] arm64: dts: r8a7796: salvator-x: enable UHS for SDHI 0 & 3 Based on work for the r8a7796 by Wolfram Sang. Signed-off-by: Simon Horman Reviewed-by: Wolfram Sang --- .../boot/dts/renesas/r8a7796-salvator-x.dts | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index c946569accb1..08c335afd970 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -97,11 +97,25 @@ scif_clk_pins: scif_clk { sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; }; sdhi3_pins: sd3 { groups = "sdhi3_data4", "sdhi3_ctrl"; function = "sdhi3"; + power-source = <3300>; + }; + + sdhi3_pins_uhs: sd3_uhs { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <1800>; }; }; @@ -115,25 +129,29 @@ &extalr_clk { &sdhi0 { pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; bus-width = <4>; + sd-uhs-sdr50; status = "okay"; }; &sdhi3 { pinctrl-0 = <&sdhi3_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi3_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi3>; vqmmc-supply = <&vccq_sdhi3>; cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; bus-width = <4>; + sd-uhs-sdr50; status = "okay"; }; From 7c827d1fda99d4a80e317b1fbb1ba359b082bda2 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sun, 16 Oct 2016 10:27:47 +0200 Subject: [PATCH 061/168] arm64: dts: r8a7795: salvator: enable on-board eMMC Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman --- .../boot/dts/renesas/r8a7795-salvator-x.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index c8f6023c4667..da3e996ba121 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -62,6 +62,24 @@ x12_clk: x12_clk { clock-frequency = <24576000>; }; + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; @@ -250,6 +268,18 @@ sdhi0_pins_uhs: sd0_uhs { power-source = <1800>; }; + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + sdhi3_pins: sd3 { groups = "sdhi3_data4", "sdhi3_ctrl"; function = "sdhi3"; @@ -401,6 +431,19 @@ &sdhi0 { status = "okay"; }; +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &sdhi3 { pinctrl-0 = <&sdhi3_pins>; pinctrl-1 = <&sdhi3_pins_uhs>; From 38548328fe3ff931063ce81ed3c3b5867c5fb233 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 6 Sep 2016 10:52:25 +0200 Subject: [PATCH 062/168] arm64: dts: r8a7796: salvator: enable on board eMMC Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman --- .../boot/dts/renesas/r8a7796-salvator-x.dts | 44 ++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index 08c335afd970..a9c296b1e1b7 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -31,6 +31,24 @@ memory@48000000 { reg = <0x0 0x48000000 0x0 0x78000000>; }; + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; @@ -78,7 +96,6 @@ vccq_sdhi3: regulator-vccq-sdhi3 { states = <3300000 1 1800000 0>; }; - }; &pfc { @@ -106,6 +123,18 @@ sdhi0_pins_uhs: sd0_uhs { power-source = <1800>; }; + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + sdhi3_pins: sd3 { groups = "sdhi3_data4", "sdhi3_ctrl"; function = "sdhi3"; @@ -141,6 +170,19 @@ &sdhi0 { status = "okay"; }; +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &sdhi3 { pinctrl-0 = <&sdhi3_pins>; pinctrl-1 = <&sdhi3_pins_uhs>; From 0751e1bd1e9e989df2d5f6a52c28b16093bc9c78 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 27 Oct 2016 19:29:27 +0900 Subject: [PATCH 063/168] arm64: dts: r8a7795: salvator-x: add bias setting for usb1_pins Since this board doesn't mount pull-up/down registers for USB1_{OVC,PWEN} pins, we should enable bias setting to pull these pins up/down. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- .../boot/dts/renesas/r8a7795-salvator-x.dts | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index da3e996ba121..bcaf4008d32d 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -309,8 +309,20 @@ usb0_pins: usb0 { }; usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; + mux { + groups = "usb1"; + function = "usb1"; + }; + + ovc { + pins = "GP_6_27"; + bias-pull-up; + }; + + pwen { + pins = "GP_6_26"; + bias-pull-down; + }; }; usb2_pins: usb2 { From 935085209343a0c507e3d9a3e01883b25c8f743e Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 14 Sep 2016 18:45:48 +0200 Subject: [PATCH 064/168] arm64: renesas: r8a7796: add SYS-DMAC controller nodes Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 99 ++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 6ec988c78ff8..f9cb7796ad49 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -252,6 +252,105 @@ scif2: serial@e6e88000 { status = "disabled"; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <16>; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7796"; reg = <0 0xee100000 0 0x2000>; From 2f81137f034765078399354ef6e9659259a77ae2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 16 Oct 2016 23:59:16 +0900 Subject: [PATCH 065/168] arm64: dts: uniphier: switch over to PSCI enable method At the first system bring-up, I chose to use spin-table because ARM Trusted Firmware was not ready for this platform at that moment. Actually, these SoCs are equipped with EL3 and able to provide PSCI. Now I finished porting the ATF BL31 for the UniPhier platform, so it is ready to migrate to PSCI enable method. Signed-off-by: Masahiro Yamada --- .../boot/dts/socionext/uniphier-ld11.dtsi | 13 ++++++++----- .../boot/dts/socionext/uniphier-ld20.dtsi | 19 ++++++++++--------- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 3eb4c42ce7b9..17bc4b359912 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ +/memreserve/ 0x80000000 0x00080000; / { compatible = "socionext,uniphier-ld11"; @@ -70,19 +70,22 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + clocks { refclk: ref { compatible = "fixed-clock"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 56a1b2e92cf3..c8ebe7e52809 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -43,7 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ +/memreserve/ 0x80000000 0x00080000; / { compatible = "socionext,uniphier-ld20"; @@ -79,35 +79,36 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; + enable-method = "psci"; }; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + clocks { refclk: ref { compatible = "fixed-clock"; From 1ef64af81716c8191c11792a297371277ab86ef2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 17 Oct 2016 00:42:42 +0900 Subject: [PATCH 066/168] arm64: dts: uniphier: increase register region size of sysctrl node The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the registers controlling CPU frequency are located at offset 0x8000. Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 2 +- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 17bc4b359912..73e0acfd4f98 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -323,7 +323,7 @@ gic: interrupt-controller@5fe00000 { sysctrl@61840000 { compatible = "socionext,uniphier-ld11-sysctrl", "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; + reg = <0x61840000 0x10000>; sys_clk: clock { compatible = "socionext,uniphier-ld11-clock"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index c8ebe7e52809..eaf260823084 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -312,7 +312,7 @@ gic: interrupt-controller@5fe00000 { sysctrl@61840000 { compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; + reg = <0x61840000 0x10000>; sys_clk: clock { compatible = "socionext,uniphier-ld20-clock"; From bdb8183681810672dd7344ad14d070a3c8cf7d14 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 20 Oct 2016 13:44:06 +0900 Subject: [PATCH 067/168] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada Acked-by: Viresh Kumar --- .../boot/dts/socionext/uniphier-ld11.dtsi | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 73e0acfd4f98..0e5c58f7624d 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -70,14 +70,52 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x000>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x001>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; + }; + }; + + cluster0_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@245000000 { + opp-hz = /bits/ 64 <245000000>; + clock-latency-ns = <300>; + }; + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@490000000 { + opp-hz = /bits/ 64 <490000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@653334000 { + opp-hz = /bits/ 64 <653334000>; + clock-latency-ns = <300>; + }; + opp@666667000 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@980000000 { + opp-hz = /bits/ 64 <980000000>; + clock-latency-ns = <300>; }; }; From 183ad3669f28e96e820c0fdf495927955b559662 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 20 Oct 2016 13:44:07 +0900 Subject: [PATCH 068/168] arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC Add a CPU clock to every CPU node and CPU OPP tables to use the generic cpufreq driver. All the CPUs in each cluster share the same OPP table. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada Acked-by: Viresh Kumar --- .../boot/dts/socionext/uniphier-ld20.dtsi | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index eaf260823084..c6462563ad88 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -79,28 +79,112 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x000>; + clocks = <&sys_clk 32>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x001>; + clocks = <&sys_clk 32>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x100>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster1_opp>; }; cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x101>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster1_opp>; + }; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@275000000 { + opp-hz = /bits/ 64 <275000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@550000000 { + opp-hz = /bits/ 64 <550000000>; + clock-latency-ns = <300>; + }; + opp@666667000 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@733334000 { + opp-hz = /bits/ 64 <733334000>; + clock-latency-ns = <300>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <300>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <300>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@275000000 { + opp-hz = /bits/ 64 <275000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@550000000 { + opp-hz = /bits/ 64 <550000000>; + clock-latency-ns = <300>; + }; + opp@666667000 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@733334000 { + opp-hz = /bits/ 64 <733334000>; + clock-latency-ns = <300>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <300>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <300>; }; }; From fb28cef06a9065748fbc6949dd7fca3c320c8e0d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 5 Nov 2016 23:30:11 +0900 Subject: [PATCH 069/168] arm64: dts: uniphier: make compatible of syscon nodes SoC-specific These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings. Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 6 +++--- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 0e5c58f7624d..7c7511b9d231 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -274,7 +274,7 @@ smpctrl@59800000 { }; perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", + compatible = "socionext,uniphier-ld11-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; @@ -323,7 +323,7 @@ usb2: usb@5a820100 { }; mioctrl@5b3e0000 { - compatible = "socionext,uniphier-mioctrl", + compatible = "socionext,uniphier-ld11-mioctrl", "simple-mfd", "syscon"; reg = <0x5b3e0000 0x800>; @@ -340,7 +340,7 @@ mio_rst: reset { }; soc-glue@5f800000 { - compatible = "socionext,uniphier-soc-glue", + compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index c6462563ad88..fcaecc6bdeac 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -359,7 +359,7 @@ sd_rst: reset { }; perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", + compatible = "socionext,uniphier-ld20-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; @@ -375,7 +375,7 @@ peri_rst: reset { }; soc-glue@5f800000 { - compatible = "socionext,uniphier-soc-glue", + compatible = "socionext,uniphier-ld20-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -394,7 +394,7 @@ gic: interrupt-controller@5fe00000 { }; sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", + compatible = "socionext,uniphier-ld20-sysctrl", "simple-mfd", "syscon"; reg = <0x61840000 0x10000>; From e79249143f468f8d3365dbbd1642c045bdcc98c5 Mon Sep 17 00:00:00 2001 From: Rob Rice Date: Tue, 24 May 2016 14:07:30 -0400 Subject: [PATCH 070/168] arm64: dts: Add Broadcom Northstar2 device tree entries for PDC driver. Add Broadcom Northstar2 SoC device tree entries for PDC driver. Signed-off-by: Rob Rice Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index f05b28b4856f..cb09981c132c 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -191,6 +191,42 @@ soc: soc { #include "ns2-clock.dtsi" + pdc0: iproc-pdc0@612c0000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x612c0000 0x445>; /* PDC FS0 regs */ + interrupts = ; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + pdc1: iproc-pdc1@612e0000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x612e0000 0x445>; /* PDC FS1 regs */ + interrupts = ; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + pdc2: iproc-pdc2@61300000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x61300000 0x445>; /* PDC FS2 regs */ + interrupts = ; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + pdc3: iproc-pdc3@61320000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x61320000 0x445>; /* PDC FS3 regs */ + interrupts = ; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + dma0: dma@61360000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x61360000 0x1000>; From c49590691f3819bb6be3f77938ef39038eb76643 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Thu, 3 Nov 2016 15:21:34 +0900 Subject: [PATCH 071/168] arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" In drivers/mmc/core/host.c, there is "max-freqeuncy" property. It should be same behavior, So Use the "max-frequency" instead of "clock-freq-min-max". Signed-off-by: Jaehoon Chung Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 6 +++--- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts index 5797933ef80e..0acf8a2bbecf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts @@ -347,7 +347,7 @@ &saradc { &sdmmc { bus-width = <4>; clock-frequency = <50000000>; - clock-freq-min-max = <400000 50000000>; + max-frequency = <50000000>; cap-sd-highspeed; card-detect-delay = <200>; keep-power-in-suspend; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 2f8e19ff65a5..4f2b6bdf87f2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -231,7 +231,7 @@ xin24m: oscillator { sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0c0000 0x0 0x4000>; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -243,7 +243,7 @@ sdmmc: dwmmc@ff0c0000 { sdio0: dwmmc@ff0d0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0d0000 0x0 0x4000>; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; @@ -255,7 +255,7 @@ sdio0: dwmmc@ff0d0000 { emmc: dwmmc@ff0f0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0f0000 0x0 0x4000>; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index cbb7f8bb131c..172e7edd4915 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -235,7 +235,7 @@ sdio0: dwmmc@fe310000 { "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; interrupts = ; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -248,7 +248,7 @@ sdmmc: dwmmc@fe320000 { "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; interrupts = ; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; From 5c99bfdc1fd3d807ee3791e3431954ffe1942582 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Fri, 23 Sep 2016 14:50:30 +0530 Subject: [PATCH 072/168] arm64: dts: apq8016-sbc: Set up LDO2, LDO6 and LDO17 regulator voltage ranges On the APQ8016 SBC, the LDO2 PM8916 regulator feeds 1.2V to the following: - VDDA_1P2_MIPI_DSI and VDDA_MIPI_CSI pins on APQ8016. - VCCCAD pins on the LPDDR3 chip. - VDDPX_1 pins on APQ8016. The LDO6 regulator feeds 1.8V to: - VDAA_MIPI_DSI0_PLL pin on APQ8016. - QFPROM_BLOW_VDD pin on PM8916. - The AVDD, A2VDD and DVDD pins on ADV7533 bridge. The LDO17 regulator feeds 3.3V to: - The V3P3 pin on ADV7533 bridge. Currently, the regulator min/max voltages for all the LDOs are set to the range of what the PMIC supports. Set the ranges for L2, L6 and L17 to what we need, i.e. 1.2V, 1.8V and 3.3V respectively. Signed-off-by: Archit Taneja Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index bb062b547110..1483a959b49e 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -308,8 +308,8 @@ l1 { }; l2 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1525000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; }; l3 { @@ -328,8 +328,8 @@ l5 { }; l6 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; l7 { @@ -388,8 +388,8 @@ l16 { }; l17 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; l18 { From 29ac9652a210fcfaf72ed3a076b38092a2e8d5e4 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 5 Oct 2016 14:41:23 +0530 Subject: [PATCH 073/168] arm64: dts: qcom: Add missing interrupt entry for pm8994 gpios pm8994 has 22 gpios, so add the missing interrupts entry for one of the gpios Signed-off-by: Rajendra Nayak Cc: Stephen Boyd Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pm8994.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 1222d2e904f6..0f1866024ae3 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -29,6 +29,7 @@ pm8994_gpios: gpios@c000 { <0 0xcc 0 IRQ_TYPE_NONE>, <0 0xcd 0 IRQ_TYPE_NONE>, <0 0xce 0 IRQ_TYPE_NONE>, + <0 0xcf 0 IRQ_TYPE_NONE>, <0 0xd0 0 IRQ_TYPE_NONE>, <0 0xd1 0 IRQ_TYPE_NONE>, <0 0xd2 0 IRQ_TYPE_NONE>, From ce2a6ca5c6ec5cb7137ae3fca18c7bc13a3dfb30 Mon Sep 17 00:00:00 2001 From: Martin Sperl Date: Wed, 2 Nov 2016 10:18:24 +0000 Subject: [PATCH 074/168] ARM64: bcm2835: dts: add thermal node to device-tree of bcm2837 Add the node for the thermal sensor of the bcm2837-soc to the device tree. Signed-off-by: Martin Sperl Signed-off-by: Eric Anholt --- arch/arm64/boot/dts/broadcom/bcm2837.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi index c1f719b7097a..19f2fe620a21 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi @@ -74,3 +74,9 @@ &intc { interrupt-parent = <&local_intc>; interrupts = <8>; }; + +/* enable thermal sensor with the correct compatible property set */ +&thermal { + compatible = "brcm,bcm2837-thermal"; + status = "okay"; +}; From 5582fcb3829faf5a942e53845b2cb47406fb4248 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 20 Oct 2016 15:20:49 +0100 Subject: [PATCH 075/168] arm64: dts: apq8016-sbc: add analog audio support with multicodec This patch add support to Analog audio both Playback and Capture via msm8916 WCD muti codec. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 61 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 ++++ arch/arm64/boot/dts/qcom/pm8916.dtsi | 45 ++++++++++++++++- 3 files changed, 114 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 1483a959b49e..08bd5ebafb4e 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -15,6 +15,7 @@ #include "pm8916.dtsi" #include "apq8016-sbc-soc-pins.dtsi" #include "apq8016-sbc-pmic-pins.dtsi" +#include / { aliases { @@ -251,6 +252,60 @@ dsi-phy@1a98300 { vddio-supply = <&pm8916_l6>; }; }; + + lpass_codec: codec{ + status = "okay"; + }; + + /* + Internal Codec + playback - Primary MI2S + capture - Ter MI2S + + External Primary: + playback - secondary MI2S + capture - Quat MI2S + + External Secondary: + playback - Quat MI2S + capture - Quat MI2S + + */ + + sound: sound { + compatible = "qcom,apq8016-sbc-sndcard"; + reg = <0x07702000 0x4>, <0x07702004 0x4>; + reg-names = "mic-iomux", "spkr-iomux"; + + status = "okay"; + pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; + pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; + pinctrl-names = "default", "sleep"; + qcom,model = "DB410c"; + qcom,audio-routing = + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + + internal-codec-playback-dai-link@0 { /* I2S - Internal codec */ + link-name = "WCD"; + cpu { /* PRIMARY */ + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + }; + }; + + internal-codec-capture-dai-link@0 { /* I2S - Internal codec */ + link-name = "WCD-Capture"; + cpu { /* PRIMARY */ + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + }; + }; + }; }; usb2513 { @@ -278,6 +333,12 @@ hdmi_con: endpoint { }; }; +&wcd_codec { + status = "okay"; + clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "mclk"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l5-supply = <&pm8916_s3>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 04cde24f9786..4221b7d2c0ce 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -504,6 +504,15 @@ lpass: lpass@07708000 { reg-names = "lpass-lpaif"; }; + lpass_codec: codec{ + compatible = "qcom,msm8916-wcd-digital-codec"; + reg = <0x0771c000 0x400>; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "ahbix-clk", "mclk"; + #sound-dai-cells = <1>; + }; + sdhc_1: sdhci@07824000 { compatible = "qcom,sdhci-msm-v4"; reg = <0x07824900 0x11c>, <0x07824000 0x800>; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index f71679b15d54..53deebf9f515 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -91,9 +91,52 @@ ref_vdd { }; pm8916_1: pm8916@1 { - compatible = "qcom,spmi-pmic"; + compatible = "qcom,pm8916", "qcom,spmi-pmic"; reg = <0x1 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + wcd_codec: codec@f000 { + compatible = "qcom,pm8916-wcd-analog-codec"; + reg = <0xf000 0x200>; + reg-names = "pmic-codec-core"; + clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "mclk"; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, + <0x1 0xf0 0x1 IRQ_TYPE_NONE>, + <0x1 0xf0 0x2 IRQ_TYPE_NONE>, + <0x1 0xf0 0x3 IRQ_TYPE_NONE>, + <0x1 0xf0 0x4 IRQ_TYPE_NONE>, + <0x1 0xf0 0x5 IRQ_TYPE_NONE>, + <0x1 0xf0 0x6 IRQ_TYPE_NONE>, + <0x1 0xf0 0x7 IRQ_TYPE_NONE>, + <0x1 0xf1 0x0 IRQ_TYPE_NONE>, + <0x1 0xf1 0x1 IRQ_TYPE_NONE>, + <0x1 0xf1 0x2 IRQ_TYPE_NONE>, + <0x1 0xf1 0x3 IRQ_TYPE_NONE>, + <0x1 0xf1 0x4 IRQ_TYPE_NONE>, + <0x1 0xf1 0x5 IRQ_TYPE_NONE>; + interrupt-names = "cdc_spk_cnp_int", + "cdc_spk_clip_int", + "cdc_spk_ocp_int", + "mbhc_ins_rem_det1", + "mbhc_but_rel_det", + "mbhc_but_press_det", + "mbhc_ins_rem_det", + "mbhc_switch_int", + "cdc_ear_ocp_int", + "cdc_hphr_ocp_int", + "cdc_hphl_ocp_det", + "cdc_ear_cnp_int", + "cdc_hphr_cnp_int", + "cdc_hphl_cnp_int"; + vdd-cdc-io-supply = <&pm8916_l5>; + vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; + vdd-micbias-supply = <&pm8916_l13>; + #sound-dai-cells = <1>; + + }; + }; }; From ee17692c20ba3efde25a39e8a1ba7430ecdc18a7 Mon Sep 17 00:00:00 2001 From: "spjoshi@codeaurora.org" Date: Fri, 21 Oct 2016 16:19:16 -0700 Subject: [PATCH 076/168] arm64: dts: msm8996: Add SMEM reserve-memory node Add DT node to carveout memory for shared memory region. Reviewed-by: Bjorn Andersson Signed-off-by: Sarangdhar Joshi Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 338f82a7fdc7..d1af1f3baff2 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -30,6 +30,17 @@ memory { reg = <0 0 0 0>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + smem_mem: smem-mem@86000000 { + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; From 13eb40eb428d9aa92fa5f80d377889ef0b2d422d Mon Sep 17 00:00:00 2001 From: "spjoshi@codeaurora.org" Date: Fri, 21 Oct 2016 16:19:17 -0700 Subject: [PATCH 077/168] arm64: dts: msm8996: Add reserve-memory nodes Add reserve-memory nodes required for Qualcomm Peripheral Image Loaders Acked-by: Bjorn Andersson Signed-off-by: Sarangdhar Joshi Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index d1af1f3baff2..7ba2a5655fde 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -35,6 +35,31 @@ reserved-memory { #size-cells = <2>; ranges; + mba_region: mba@91500000 { + reg = <0x0 0x91500000 0x0 0x200000>; + no-map; + }; + + slpi_region: slpi@90b00000 { + reg = <0x0 0x90b00000 0x0 0xa00000>; + no-map; + }; + + venus_region: venus@90400000 { + reg = <0x0 0x90400000 0x0 0x700000>; + no-map; + }; + + adsp_region: adsp@8ea00000 { + reg = <0x0 0x8ea00000 0x0 0x1a00000>; + no-map; + }; + + mpss_region: mpss@88800000 { + reg = <0x0 0x88800000 0x0 0x6200000>; + no-map; + }; + smem_mem: smem-mem@86000000 { reg = <0x0 0x86000000 0x0 0x200000>; no-map; From da3d658e28b55c864df1cd0b067fc2b8addbe2bc Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 21 Oct 2016 16:19:18 -0700 Subject: [PATCH 078/168] arm64: dts: msm8996: Add SMEM DT nodes Add SMEM and TCSR DT nodes on MSM8996. Signed-off-by: Bjorn Andersson Signed-off-by: Sarangdhar Joshi Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 7ba2a5655fde..2306ecc36ff3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -248,12 +248,29 @@ psci { method = "smc"; }; + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + tcsr_mutex_regs: syscon@740000 { + compatible = "syscon"; + reg = <0x740000 0x20000>; + }; + intc: interrupt-controller@9bc0000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From 2f45d9fcd5317b88837adb6a49405f8e84df10bd Mon Sep 17 00:00:00 2001 From: "spjoshi@codeaurora.org" Date: Fri, 21 Oct 2016 16:19:19 -0700 Subject: [PATCH 079/168] arm64: dts: msm8996: Add SMP2P and APCS nodes Add SMP2P and APCS DT nodes required for Qualcomm ADSP Peripheral Image Loader. Acked-by: Bjorn Andersson Signed-off-by: Sarangdhar Joshi Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 2306ecc36ff3..cde4114bae5a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -282,6 +282,11 @@ intc: interrupt-controller@9bc0000 { interrupts = ; }; + apcs: syscon@9820000 { + compatible = "syscon"; + reg = <0x9820000 0x1000>; + }; + gcc: clock-controller@300000 { compatible = "qcom,gcc-msm8996"; #clock-cells = <1>; @@ -511,5 +516,29 @@ mmcc: clock-controller@8c0000 { <825000000>; }; }; + + adsp-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 16 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "msm8996-pins.dtsi" From 6a6d1978f9c0d818b4370903e1f3eecf1681c932 Mon Sep 17 00:00:00 2001 From: Jeremy McNicoll Date: Fri, 4 Nov 2016 13:56:31 -0700 Subject: [PATCH 080/168] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support Initial device tree support for Qualcomm MSM8992 SoC and LG Bullhead / Google Nexus 5X support. Signed-off-by: Jeremy McNicoll Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/Makefile | 6 +- .../dts/qcom/msm8992-bullhead-rev-101.dts | 41 ++++ arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 ++++ arch/arm64/boot/dts/qcom/msm8992.dtsi | 184 ++++++++++++++++++ 4 files changed, 267 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5dd05de5619b..439e40e15261 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,6 +1,8 @@ -dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts new file mode 100644 index 000000000000..454213391671 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts @@ -0,0 +1,41 @@ +/* Copyright (c) 2015, LGE Inc. All rights reserved. + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "msm8992.dtsi" + +/ { + model = "LG Nexus 5X"; + compatible = "lg,bullhead", "qcom,msm8992"; + /* required for bootloader to select correct board */ + qcom,board-id = <0xb64 0>; + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + serial@f991e000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi new file mode 100644 index 000000000000..d2a26f0f8d73 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&msmgpio { + blsp1_uart2_default: blsp1_uart2_default { + pinmux { + function = "blsp_uart2"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi new file mode 100644 index 000000000000..44b2d37d8c4b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -0,0 +1,184 @@ +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. MSM 8992"; + compatible = "qcom,msm8992"; + // msm-id needed by bootloader for selecting correct blob + qcom,msm-id = <251 0>, <252 0>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = ; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = ; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = ; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = ; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = ; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = ; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + + msmgpio: pinctrl@fd510000 { + compatible = "qcom,msm8994-pinctrl"; + reg = <0xfd510000 0x4000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + blsp1_uart2: serial@f991e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991e000 0x1000>; + interrupts = ; + status = "disabled"; + clock-names = "core", "iface"; + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + }; + + clock_gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8994"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfc400000 0x2000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0 0>; // bootloader will update + }; +}; + + +#include "msm8992-pins.dtsi" From a3da91576618122668900fc83bbb956e6a58509d Mon Sep 17 00:00:00 2001 From: Jeremy McNicoll Date: Fri, 4 Nov 2016 13:56:33 -0700 Subject: [PATCH 081/168] dt-bindings: qcom: Add msm899(2/4) bindings Acked-by: Rob Herring Signed-off-by: Jeremy McNicoll Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/arm/qcom.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt index 3e24518c6678..eb4057e77c23 100644 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ b/Documentation/devicetree/bindings/arm/qcom.txt @@ -21,6 +21,8 @@ The 'SoC' element must be one of the following strings: apq8096 msm8916 msm8974 + msm8992 + msm8994 msm8996 The 'board' element must be one of the following strings: From feeaf56ac78d283efe65ea60ec999d4bf3cf395e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bastian=20K=C3=B6cher?= Date: Fri, 4 Nov 2016 13:56:36 -0700 Subject: [PATCH 082/168] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initial device tree support for Qualcomm MSM8994 SoC and Huawei Angler / Google Nexus 6P support. The device tree is based on the Google 3.10 kernel tree. The device can be booted into the initrd with only one CPU running. Signed-off-by: Bastian Köcher [jeremymc@redhat.com: removed Kconfig, defconfig, move from Huawei to qcom dir] Signed-off-by: Jeremy McNicoll Tested-by: Michael Scott Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8994-angler-rev-101.dts | 40 ++++ arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 +++ arch/arm64/boot/dts/qcom/msm8994.dtsi | 216 ++++++++++++++++++ 4 files changed, 295 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 439e40e15261..cc0f02d9dd02 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb always := $(dtb-y) diff --git a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts new file mode 100644 index 000000000000..dfa08f513dc4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2015, Huawei Inc. All rights reserved. + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "msm8994.dtsi" + +/ { + model = "Huawei Nexus 6P"; + compatible = "huawei,angler", "qcom,msm8994"; + /* required for bootloader to select correct board */ + qcom,board-id = <8026 0>; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + serial@f991e000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi new file mode 100644 index 000000000000..0e4eea0df25d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&msmgpio { + blsp1_uart2_default: blsp1_uart2_default { + pinmux { + function = "blsp_uart2"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi new file mode 100644 index 000000000000..f33c41d01c86 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -0,0 +1,216 @@ +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. MSM 8994"; + compatible = "qcom,msm8994"; + // msm-id and pmic-id are required by bootloader for + // proper selection of dt blob + qcom,msm-id = <207 0x20000>; + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 2 0xff08>, + <1 3 0xff08>, + <1 4 0xff08>, + <1 1 0xff08>; + }; + + soc: soc { + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = ; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = ; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = ; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = ; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = ; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = ; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + + msmgpio: pinctrl@fd510000 { + compatible = "qcom,msm8994-pinctrl"; + reg = <0xfd510000 0x4000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + blsp1_uart2: serial@f991e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991e000 0x1000>; + interrupts = ; + status = "disabled"; + clock-names = "core", "iface"; + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + }; + + tcsr_mutex_regs: syscon@fd484000 { + compatible = "syscon"; + reg = <0xfd484000 0x2000>; + }; + + clock_gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8994"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfc400000 0x2000>; + }; + }; + + memory { + device_type = "memory"; + // We expect the bootloader to fill in the reg + reg = <0 0 0 0>; + }; + + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + smem_mem: smem_region@6a00000 { + reg = <0x0 0x6a00000 0x0 0x200000>; + no-map; + }; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x80>; + #hwlock-cells = <1>; + }; + + qcom,smem@6a00000 { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; +}; + + +#include "msm8994-pins.dtsi" From 2afc1db0c5bad5da75556889ebc3e75661be9028 Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Mon, 14 Nov 2016 12:36:39 +0800 Subject: [PATCH 083/168] arm64: dts: rockchip: add gmac needed pclk for rk3399 pd This patch fixes that sometimes hang at start-up time of the system. As the below log: ... [ 11.136543] calling pm_genpd_debug_init+0x0/0x60 @ 1 [ 11.141602] initcall pm_genpd_debug_init+0x0/0x60 returned 0 after 11 usecs [ 11.148558] calling genpd_poweroff_unused+0x0/0x84 @ 1 In some cases, the rk3399 should turn off the gmac power domain to save power if some boards didn't register the gmac device node for rk3399. Then, rk3399 need to make sure the gmac's pclk enabled if we need operate the gmac power domain. (Due to the NOC had enabled always) Signed-off-by: Jeffy Chen Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 172e7edd4915..e8b9df965182 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -825,7 +825,8 @@ pd_gpu@RK3399_PD_GPU { /* These power domains are grouped by VD_LOGIC */ pd_gmac@RK3399_PD_GMAC { reg = ; - clocks = <&cru ACLK_GMAC>; + clocks = <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; }; pd_vio@RK3399_PD_VIO { From 578c0e7e8363d4182c4c361250c7dbbf65ce20b5 Mon Sep 17 00:00:00 2001 From: Yakir Yang Date: Wed, 9 Nov 2016 21:21:57 +0800 Subject: [PATCH 084/168] arm64: dts: rockchip: add backlight support for rk3399 evb board Add backlight node for evb board, perpare for panel device node. Signed-off-by: Yakir Yang Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts index 8e82497925fe..3040a989d699 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts @@ -49,6 +49,46 @@ / { compatible = "rockchip,rk3399-evb", "rockchip,rk3399", "google,rk3399evb-rev2"; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + pwms = <&pwm0 0 25000 0>; + }; + clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; From a1907df27e22e695c8e89bd3133eac1c2ee965c2 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 9 Nov 2016 21:21:53 +0800 Subject: [PATCH 085/168] arm64: dts: rockchip: add eMMC's power domain support for rk3399 Control power domain for eMMC via genpd to reduce power consumption. Signed-off-by: Elaine Zhang Signed-off-by: Caesar Wang Tested-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e8b9df965182..cc4930a3e90a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -269,6 +269,7 @@ sdhci: sdhci@fe330000 { #clock-cells = <0>; phys = <&emmc_phy>; phy-names = "phy_arasan"; + power-domains = <&power RK3399_PD_EMMC>; status = "disabled"; }; @@ -690,6 +691,11 @@ tsadc: tsadc@ff260000 { status = "disabled"; }; + qos_emmc: qos@ffa58000 { + compatible = "syscon"; + reg = <0x0 0xffa58000 0x0 0x20>; + }; + qos_gmac: qos@ffa5c000 { compatible = "syscon"; reg = <0x0 0xffa5c000 0x0 0x20>; @@ -823,6 +829,11 @@ pd_gpu@RK3399_PD_GPU { }; /* These power domains are grouped by VD_LOGIC */ + pd_emmc@RK3399_PD_EMMC { + reg = ; + clocks = <&cru ACLK_EMMC>; + pm_qos = <&qos_emmc>; + }; pd_gmac@RK3399_PD_GMAC { reg = ; clocks = <&cru ACLK_GMAC>, From 1bc60beec02d3b3ce87209bda69c2d94630beb6e Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 9 Nov 2016 21:21:54 +0800 Subject: [PATCH 086/168] arm64: dts: rockchip: add pd_sd power-domain node for rk3399 Add the sd power-domain, its qos area and assign it to the sdmmc device node. Signed-off-by: Elaine Zhang Signed-off-by: Caesar Wang Tested-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index cc4930a3e90a..fc30b57ac557 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -253,6 +253,7 @@ sdmmc: dwmmc@fe320000 { <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; + power-domains = <&power RK3399_PD_SD>; status = "disabled"; }; @@ -691,6 +692,11 @@ tsadc: tsadc@ff260000 { status = "disabled"; }; + qos_sd: qos@ffa74000 { + compatible = "syscon"; + reg = <0x0 0xffa74000 0x0 0x20>; + }; + qos_emmc: qos@ffa58000 { compatible = "syscon"; reg = <0x0 0xffa58000 0x0 0x20>; @@ -840,6 +846,12 @@ pd_gmac@RK3399_PD_GMAC { <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; }; + pd_sd@RK3399_PD_SD { + reg = ; + clocks = <&cru HCLK_SDMMC>, + <&cru SCLK_SDMMC>; + pm_qos = <&qos_sd>; + }; pd_vio@RK3399_PD_VIO { reg = ; #address-cells = <1>; From 18486552b752e7540f346059aa404bfd4a302b00 Mon Sep 17 00:00:00 2001 From: Hongtao Jia Date: Sun, 9 Oct 2016 14:47:05 +0800 Subject: [PATCH 087/168] arm64: dts: ls1043a: Add TMU device tree support for LS1043A Also add nodes and properties for thermal management support. Signed-off-by: Jia Hongtao Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1043a-qds.dts | 2 +- .../boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 +- .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 78 +++++++++++++++++++ 3 files changed, 80 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts index dd9e91941df4..0989d635b558 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts @@ -45,7 +45,7 @@ */ /dts-v1/; -/include/ "fsl-ls1043a.dtsi" +#include "fsl-ls1043a.dtsi" / { model = "LS1043A QDS Board"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts index d2313e05fd22..c37110bc1506 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts @@ -45,7 +45,7 @@ */ /dts-v1/; -/include/ "fsl-ls1043a.dtsi" +#include "fsl-ls1043a.dtsi" / { model = "LS1043A RDB Board"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 220ac7057d12..41e5dc1dbd79 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -44,6 +44,8 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include + / { compatible = "fsl,ls1043a"; interrupt-parent = <&gic>; @@ -66,6 +68,7 @@ cpu0: cpu@0 { reg = <0x0>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -254,6 +257,81 @@ ddr: memory-controller@1080000 { big-endian; }; + tmu: tmu@1f00000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f00000 0x0 0x10000>; + interrupts = <0 33 0x4>; + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; + fsl,tmu-calibration = <0x00000000 0x00000026 + 0x00000001 0x0000002d + 0x00000002 0x00000032 + 0x00000003 0x00000039 + 0x00000004 0x0000003f + 0x00000005 0x00000046 + 0x00000006 0x0000004d + 0x00000007 0x00000054 + 0x00000008 0x0000005a + 0x00000009 0x00000061 + 0x0000000a 0x0000006a + 0x0000000b 0x00000071 + + 0x00010000 0x00000025 + 0x00010001 0x0000002c + 0x00010002 0x00000035 + 0x00010003 0x0000003d + 0x00010004 0x00000045 + 0x00010005 0x0000004e + 0x00010006 0x00000057 + 0x00010007 0x00000061 + 0x00010008 0x0000006b + 0x00010009 0x00000076 + + 0x00020000 0x00000029 + 0x00020001 0x00000033 + 0x00020002 0x0000003d + 0x00020003 0x00000049 + 0x00020004 0x00000056 + 0x00020005 0x00000061 + 0x00020006 0x0000006d + + 0x00030000 0x00000021 + 0x00030001 0x0000002a + 0x00030002 0x0000003c + 0x00030003 0x0000004e>; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + + thermal-sensors = <&tmu 3>; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; + dspi0: dspi@2100000 { compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; From 236f794e4463a6b53139702c1b609091f61a17ab Mon Sep 17 00:00:00 2001 From: Hongtao Jia Date: Sun, 9 Oct 2016 14:47:06 +0800 Subject: [PATCH 088/168] arm64: dts: ls2080a: Add TMU device tree support for LS2080A Also add nodes and properties for thermal management support. Signed-off-by: Jia Hongtao Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls2080a-qds.dts | 2 +- .../boot/dts/freescale/fsl-ls2080a-rdb.dts | 2 +- .../boot/dts/freescale/fsl-ls2080a-simu.dts | 2 +- .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 116 ++++++++++++++++-- 4 files changed, 111 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts index b0dd010979e7..8bc1f8f6fcfc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts @@ -46,7 +46,7 @@ /dts-v1/; -/include/ "fsl-ls2080a.dtsi" +#include "fsl-ls2080a.dtsi" / { model = "Freescale Layerscape 2080a QDS Board"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts index ad0ebb8a1949..265e0a8b107b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts @@ -46,7 +46,7 @@ /dts-v1/; -/include/ "fsl-ls2080a.dtsi" +#include "fsl-ls2080a.dtsi" / { model = "Freescale Layerscape 2080a RDB Board"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts index 505d038078a3..290604b0a603 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts @@ -46,7 +46,7 @@ /dts-v1/; -/include/ "fsl-ls2080a.dtsi" +#include "fsl-ls2080a.dtsi" / { model = "Freescale Layerscape 2080a software Simulator model"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 337da90bd7da..723185e85d6f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -44,6 +44,8 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include + / { compatible = "fsl,ls2080a"; interrupt-parent = <&gic>; @@ -62,15 +64,16 @@ cpus { */ /* We have 4 clusters having 2 Cortex-A57 cores each */ - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x0>; clocks = <&clockgen 1 0>; next-level-cache = <&cluster0_l2>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x1>; @@ -78,15 +81,16 @@ cpu@1 { next-level-cache = <&cluster0_l2>; }; - cpu@100 { + cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x100>; clocks = <&clockgen 1 1>; next-level-cache = <&cluster1_l2>; + #cooling-cells = <2>; }; - cpu@101 { + cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x101>; @@ -94,15 +98,16 @@ cpu@101 { next-level-cache = <&cluster1_l2>; }; - cpu@200 { + cpu4: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x200>; clocks = <&clockgen 1 2>; next-level-cache = <&cluster2_l2>; + #cooling-cells = <2>; }; - cpu@201 { + cpu5: cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x201>; @@ -110,15 +115,16 @@ cpu@201 { next-level-cache = <&cluster2_l2>; }; - cpu@300 { + cpu6: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x300>; clocks = <&clockgen 1 3>; next-level-cache = <&cluster3_l2>; + #cooling-cells = <2>; }; - cpu@301 { + cpu7: cpu@301 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0x301>; @@ -215,6 +221,100 @@ clockgen: clocking@1300000 { clocks = <&sysclk>; }; + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = <0 23 0x4>; + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; + fsl,tmu-calibration = <0x00000000 0x00000026 + 0x00000001 0x0000002d + 0x00000002 0x00000032 + 0x00000003 0x00000039 + 0x00000004 0x0000003f + 0x00000005 0x00000046 + 0x00000006 0x0000004d + 0x00000007 0x00000054 + 0x00000008 0x0000005a + 0x00000009 0x00000061 + 0x0000000a 0x0000006a + 0x0000000b 0x00000071 + + 0x00010000 0x00000025 + 0x00010001 0x0000002c + 0x00010002 0x00000035 + 0x00010003 0x0000003d + 0x00010004 0x00000045 + 0x00010005 0x0000004e + 0x00010006 0x00000057 + 0x00010007 0x00000061 + 0x00010008 0x0000006b + 0x00010009 0x00000076 + + 0x00020000 0x00000029 + 0x00020001 0x00000033 + 0x00020002 0x0000003d + 0x00020003 0x00000049 + 0x00020004 0x00000056 + 0x00020005 0x00000061 + 0x00020006 0x0000006d + + 0x00030000 0x00000021 + 0x00030001 0x0000002a + 0x00030002 0x0000003c + 0x00030003 0x0000004e>; + little-endian; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + + thermal-sensors = <&tmu 4>; + + trips { + cpu_alert: cpu-alert { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert>; + cooling-device = + <&cpu2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + map2 { + trip = <&cpu_alert>; + cooling-device = + <&cpu4 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + map3 { + trip = <&cpu_alert>; + cooling-device = + <&cpu6 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; + serial0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; From 4d75a171b67ffc3f4dadbd654c9d281091300eb2 Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Sat, 24 Sep 2016 17:14:21 +0800 Subject: [PATCH 089/168] arm64: dts: hip06: Correct hardware pin number of usb node The ohci/ehci hardware pin number should be 640/641, correct them. Fixes: commit aa8d3e74f54d ("arm64: dts: Add initial dts for Hisilicon Hip06 D03 board") Signed-off-by: Kefeng Wang Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index b548763366dd..af450413b9dd 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -322,7 +322,7 @@ usb_ohci: ohci@a7030000 { compatible = "generic-ohci"; reg = <0x0 0xa7030000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; - interrupts = <64 4>; + interrupts = <640 4>; dma-coherent; status = "disabled"; }; @@ -331,7 +331,7 @@ usb_ehci: ehci@a7020000 { compatible = "generic-ehci"; reg = <0x0 0xa7020000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; - interrupts = <65 4>; + interrupts = <641 4>; dma-coherent; status = "disabled"; }; From 2c6aa008b84ca451800295f1698faa8106ce2882 Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Sat, 24 Sep 2016 17:14:22 +0800 Subject: [PATCH 090/168] Documentation: arm64: Add Hisilicon Hip07 D05 dts binding This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon Hip07 D05 board. Signed-off-by: Kefeng Wang Signed-off-by: Wei Xu --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 3f81575aa6be..7df79a715611 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -28,6 +28,10 @@ HiP06 D03 Board Required root node properties: - compatible = "hisilicon,hip06-d03"; +HiP07 D05 Board +Required root node properties: + - compatible = "hisilicon,hip07-d05"; + Hisilicon system controller Required properties: From 4f357f94e13d92e514be291fc71ddf154c3b6c62 Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Sat, 24 Sep 2016 17:14:23 +0800 Subject: [PATCH 091/168] arm64: dts: hisilicon: Add initial dts for Hip07 D05 board Adding initial dt file for Hip07 D05 board, it is with dual socket and each socket has two SCCLs(supper cpu cluster), one SCCL contains four clusters and each cluster has quard Cortex-A72. Since each SCCL has their own DDR controller, it could be treated as a separate numa node. Thus, there are four numa nodes(one node with sixteen core) on Hip07 SoC. Signed-off-by: Kefeng Wang Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/Makefile | 1 + arch/arm64/boot/dts/hisilicon/hip07-d05.dts | 66 ++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 1059 +++++++++++++++++++ 3 files changed, 1126 insertions(+) create mode 100644 arch/arm64/boot/dts/hisilicon/hip07-d05.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hip07.dtsi diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile index d5f43a06b1c1..c8b8f803cf90 100644 --- a/arch/arm64/boot/dts/hisilicon/Makefile +++ b/arch/arm64/boot/dts/hisilicon/Makefile @@ -1,6 +1,7 @@ dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb +dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts new file mode 100644 index 000000000000..e05844230583 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts @@ -0,0 +1,66 @@ +/** + * dts file for Hisilicon D05 Development Board + * + * Copyright (C) 2016 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +/dts-v1/; + +#include "hip07.dtsi" + +/ { + model = "Hisilicon Hip07 D05 Development Board"; + compatible = "hisilicon,hip07-d05"; + + /* the mem node will be updated by UEFI. */ + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x40000000>; + numa-node-id = <0>; + }; + + distance-map { + compatible = "numa-distance-map-v1"; + distance-matrix = <0 0 10>, + <0 1 15>, + <0 2 20>, + <0 3 25>, + <1 0 15>, + <1 1 10>, + <1 2 25>, + <1 3 30>, + <2 0 20>, + <2 1 25>, + <2 2 10>, + <2 3 15>, + <3 0 25>, + <3 1 30>, + <3 2 15>, + <3 3 10>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "ok"; +}; + +&usb_ohci { + status = "ok"; +}; + +&usb_ehci { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi new file mode 100644 index 000000000000..5144eb1c179d --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -0,0 +1,1059 @@ +/** + * dts file for Hisilicon D05 Development Board + * + * Copyright (C) 2016 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +#include + +/ { + compatible = "hisilicon,hip07-d05"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu8>; + }; + core1 { + cpu = <&cpu9>; + }; + core2 { + cpu = <&cpu10>; + }; + core3 { + cpu = <&cpu11>; + }; + }; + + cluster3 { + core0 { + cpu = <&cpu12>; + }; + core1 { + cpu = <&cpu13>; + }; + core2 { + cpu = <&cpu14>; + }; + core3 { + cpu = <&cpu15>; + }; + }; + + cluster4 { + core0 { + cpu = <&cpu16>; + }; + core1 { + cpu = <&cpu17>; + }; + core2 { + cpu = <&cpu18>; + }; + core3 { + cpu = <&cpu19>; + }; + }; + + cluster5 { + core0 { + cpu = <&cpu20>; + }; + core1 { + cpu = <&cpu21>; + }; + core2 { + cpu = <&cpu22>; + }; + core3 { + cpu = <&cpu23>; + }; + }; + + cluster6 { + core0 { + cpu = <&cpu24>; + }; + core1 { + cpu = <&cpu25>; + }; + core2 { + cpu = <&cpu26>; + }; + core3 { + cpu = <&cpu27>; + }; + }; + + cluster7 { + core0 { + cpu = <&cpu28>; + }; + core1 { + cpu = <&cpu29>; + }; + core2 { + cpu = <&cpu30>; + }; + core3 { + cpu = <&cpu31>; + }; + }; + + cluster8 { + core0 { + cpu = <&cpu32>; + }; + core1 { + cpu = <&cpu33>; + }; + core2 { + cpu = <&cpu34>; + }; + core3 { + cpu = <&cpu35>; + }; + }; + + cluster9 { + core0 { + cpu = <&cpu36>; + }; + core1 { + cpu = <&cpu37>; + }; + core2 { + cpu = <&cpu38>; + }; + core3 { + cpu = <&cpu39>; + }; + }; + + cluster10 { + core0 { + cpu = <&cpu40>; + }; + core1 { + cpu = <&cpu41>; + }; + core2 { + cpu = <&cpu42>; + }; + core3 { + cpu = <&cpu43>; + }; + }; + + cluster11 { + core0 { + cpu = <&cpu44>; + }; + core1 { + cpu = <&cpu45>; + }; + core2 { + cpu = <&cpu46>; + }; + core3 { + cpu = <&cpu47>; + }; + }; + + cluster12 { + core0 { + cpu = <&cpu48>; + }; + core1 { + cpu = <&cpu49>; + }; + core2 { + cpu = <&cpu50>; + }; + core3 { + cpu = <&cpu51>; + }; + }; + + cluster13 { + core0 { + cpu = <&cpu52>; + }; + core1 { + cpu = <&cpu53>; + }; + core2 { + cpu = <&cpu54>; + }; + core3 { + cpu = <&cpu55>; + }; + }; + + cluster14 { + core0 { + cpu = <&cpu56>; + }; + core1 { + cpu = <&cpu57>; + }; + core2 { + cpu = <&cpu58>; + }; + core3 { + cpu = <&cpu59>; + }; + }; + + cluster15 { + core0 { + cpu = <&cpu60>; + }; + core1 { + cpu = <&cpu61>; + }; + core2 { + cpu = <&cpu62>; + }; + core3 { + cpu = <&cpu63>; + }; + }; + }; + + cpu0: cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10000>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + numa-node-id = <0>; + }; + + cpu1: cpu@10001 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10001>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + numa-node-id = <0>; + }; + + cpu2: cpu@10002 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10002>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + numa-node-id = <0>; + }; + + cpu3: cpu@10003 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10003>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + numa-node-id = <0>; + }; + + cpu4: cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10100>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + numa-node-id = <0>; + }; + + cpu5: cpu@10101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10101>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + numa-node-id = <0>; + }; + + cpu6: cpu@10102 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10102>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + numa-node-id = <0>; + }; + + cpu7: cpu@10103 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10103>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + numa-node-id = <0>; + }; + + cpu8: cpu@10200 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10200>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + numa-node-id = <0>; + }; + + cpu9: cpu@10201 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10201>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + numa-node-id = <0>; + }; + + cpu10: cpu@10202 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10202>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + numa-node-id = <0>; + }; + + cpu11: cpu@10203 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10203>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + numa-node-id = <0>; + }; + + cpu12: cpu@10300 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10300>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + numa-node-id = <0>; + }; + + cpu13: cpu@10301 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10301>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + numa-node-id = <0>; + }; + + cpu14: cpu@10302 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10302>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + numa-node-id = <0>; + }; + + cpu15: cpu@10303 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10303>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + numa-node-id = <0>; + }; + + cpu16: cpu@30000 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30000>; + enable-method = "psci"; + next-level-cache = <&cluster4_l2>; + numa-node-id = <1>; + }; + + cpu17: cpu@30001 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30001>; + enable-method = "psci"; + next-level-cache = <&cluster4_l2>; + numa-node-id = <1>; + }; + + cpu18: cpu@30002 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30002>; + enable-method = "psci"; + next-level-cache = <&cluster4_l2>; + numa-node-id = <1>; + }; + + cpu19: cpu@30003 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30003>; + enable-method = "psci"; + next-level-cache = <&cluster4_l2>; + numa-node-id = <1>; + }; + + cpu20: cpu@30100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30100>; + enable-method = "psci"; + next-level-cache = <&cluster5_l2>; + numa-node-id = <1>; + }; + + cpu21: cpu@30101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30101>; + enable-method = "psci"; + next-level-cache = <&cluster5_l2>; + numa-node-id = <1>; + }; + + cpu22: cpu@30102 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30102>; + enable-method = "psci"; + next-level-cache = <&cluster5_l2>; + numa-node-id = <1>; + }; + + cpu23: cpu@30103 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30103>; + enable-method = "psci"; + next-level-cache = <&cluster5_l2>; + numa-node-id = <1>; + }; + + cpu24: cpu@30200 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30200>; + enable-method = "psci"; + next-level-cache = <&cluster6_l2>; + numa-node-id = <1>; + }; + + cpu25: cpu@30201 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30201>; + enable-method = "psci"; + next-level-cache = <&cluster6_l2>; + numa-node-id = <1>; + }; + + cpu26: cpu@30202 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30202>; + enable-method = "psci"; + next-level-cache = <&cluster6_l2>; + numa-node-id = <1>; + }; + + cpu27: cpu@30203 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30203>; + enable-method = "psci"; + next-level-cache = <&cluster6_l2>; + numa-node-id = <1>; + }; + + cpu28: cpu@30300 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30300>; + enable-method = "psci"; + next-level-cache = <&cluster7_l2>; + numa-node-id = <1>; + }; + + cpu29: cpu@30301 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30301>; + enable-method = "psci"; + next-level-cache = <&cluster7_l2>; + numa-node-id = <1>; + }; + + cpu30: cpu@30302 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30302>; + enable-method = "psci"; + next-level-cache = <&cluster7_l2>; + numa-node-id = <1>; + }; + + cpu31: cpu@30303 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30303>; + enable-method = "psci"; + next-level-cache = <&cluster7_l2>; + numa-node-id = <1>; + }; + + cpu32: cpu@50000 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50000>; + enable-method = "psci"; + next-level-cache = <&cluster8_l2>; + numa-node-id = <2>; + }; + + cpu33: cpu@50001 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50001>; + enable-method = "psci"; + next-level-cache = <&cluster8_l2>; + numa-node-id = <2>; + }; + + cpu34: cpu@50002 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50002>; + enable-method = "psci"; + next-level-cache = <&cluster8_l2>; + numa-node-id = <2>; + }; + + cpu35: cpu@50003 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50003>; + enable-method = "psci"; + next-level-cache = <&cluster8_l2>; + numa-node-id = <2>; + }; + + cpu36: cpu@50100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50100>; + enable-method = "psci"; + next-level-cache = <&cluster9_l2>; + numa-node-id = <2>; + }; + + cpu37: cpu@50101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50101>; + enable-method = "psci"; + next-level-cache = <&cluster9_l2>; + numa-node-id = <2>; + }; + + cpu38: cpu@50102 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50102>; + enable-method = "psci"; + next-level-cache = <&cluster9_l2>; + numa-node-id = <2>; + }; + + cpu39: cpu@50103 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50103>; + enable-method = "psci"; + next-level-cache = <&cluster9_l2>; + numa-node-id = <2>; + }; + + cpu40: cpu@50200 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50200>; + enable-method = "psci"; + next-level-cache = <&cluster10_l2>; + numa-node-id = <2>; + }; + + cpu41: cpu@50201 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50201>; + enable-method = "psci"; + next-level-cache = <&cluster10_l2>; + numa-node-id = <2>; + }; + + cpu42: cpu@50202 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50202>; + enable-method = "psci"; + next-level-cache = <&cluster10_l2>; + numa-node-id = <2>; + }; + + cpu43: cpu@50203 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50203>; + enable-method = "psci"; + next-level-cache = <&cluster10_l2>; + numa-node-id = <2>; + }; + + cpu44: cpu@50300 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50300>; + enable-method = "psci"; + next-level-cache = <&cluster11_l2>; + numa-node-id = <2>; + }; + + cpu45: cpu@50301 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50301>; + enable-method = "psci"; + next-level-cache = <&cluster11_l2>; + numa-node-id = <2>; + }; + + cpu46: cpu@50302 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50302>; + enable-method = "psci"; + next-level-cache = <&cluster11_l2>; + numa-node-id = <2>; + }; + + cpu47: cpu@50303 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50303>; + enable-method = "psci"; + next-level-cache = <&cluster11_l2>; + numa-node-id = <2>; + }; + + cpu48: cpu@70000 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70000>; + enable-method = "psci"; + next-level-cache = <&cluster12_l2>; + numa-node-id = <3>; + }; + + cpu49: cpu@70001 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70001>; + enable-method = "psci"; + next-level-cache = <&cluster12_l2>; + numa-node-id = <3>; + }; + + cpu50: cpu@70002 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70002>; + enable-method = "psci"; + next-level-cache = <&cluster12_l2>; + numa-node-id = <3>; + }; + + cpu51: cpu@70003 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70003>; + enable-method = "psci"; + next-level-cache = <&cluster12_l2>; + numa-node-id = <3>; + }; + + cpu52: cpu@70100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70100>; + enable-method = "psci"; + next-level-cache = <&cluster13_l2>; + numa-node-id = <3>; + }; + + cpu53: cpu@70101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70101>; + enable-method = "psci"; + next-level-cache = <&cluster13_l2>; + numa-node-id = <3>; + }; + + cpu54: cpu@70102 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70102>; + enable-method = "psci"; + next-level-cache = <&cluster13_l2>; + numa-node-id = <3>; + }; + + cpu55: cpu@70103 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70103>; + enable-method = "psci"; + next-level-cache = <&cluster13_l2>; + numa-node-id = <3>; + }; + + cpu56: cpu@70200 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70200>; + enable-method = "psci"; + next-level-cache = <&cluster14_l2>; + numa-node-id = <3>; + }; + + cpu57: cpu@70201 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70201>; + enable-method = "psci"; + next-level-cache = <&cluster14_l2>; + numa-node-id = <3>; + }; + + cpu58: cpu@70202 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70202>; + enable-method = "psci"; + next-level-cache = <&cluster14_l2>; + numa-node-id = <3>; + }; + + cpu59: cpu@70203 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70203>; + enable-method = "psci"; + next-level-cache = <&cluster14_l2>; + numa-node-id = <3>; + }; + + cpu60: cpu@70300 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70300>; + enable-method = "psci"; + next-level-cache = <&cluster15_l2>; + numa-node-id = <3>; + }; + + cpu61: cpu@70301 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70301>; + enable-method = "psci"; + next-level-cache = <&cluster15_l2>; + numa-node-id = <3>; + }; + + cpu62: cpu@70302 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70302>; + enable-method = "psci"; + next-level-cache = <&cluster15_l2>; + numa-node-id = <3>; + }; + + cpu63: cpu@70303 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70303>; + enable-method = "psci"; + next-level-cache = <&cluster15_l2>; + numa-node-id = <3>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; + }; + + cluster4_l2: l2-cache4 { + compatible = "cache"; + }; + + cluster5_l2: l2-cache5 { + compatible = "cache"; + }; + + cluster6_l2: l2-cache6 { + compatible = "cache"; + }; + + cluster7_l2: l2-cache7 { + compatible = "cache"; + }; + + cluster8_l2: l2-cache8 { + compatible = "cache"; + }; + + cluster9_l2: l2-cache9 { + compatible = "cache"; + }; + + cluster10_l2: l2-cache10 { + compatible = "cache"; + }; + + cluster11_l2: l2-cache11 { + compatible = "cache"; + }; + + cluster12_l2: l2-cache12 { + compatible = "cache"; + }; + + cluster13_l2: l2-cache13 { + compatible = "cache"; + }; + + cluster14_l2: l2-cache14 { + compatible = "cache"; + }; + + cluster15_l2: l2-cache15 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@4d000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <4>; + redistributor-stride = <0x0 0x40000>; + reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */ + <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */ + <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */ + <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */ + <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */ + <0x0 0xfe000000 0x0 0x10000>, /* GICC */ + <0x0 0xfe010000 0x0 0x10000>, /* GICH */ + <0x0 0xfe020000 0x0 0x10000>; /* GICV */ + interrupts = ; + + p0_its_peri_a: interrupt-controller@4c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x4c000000 0x0 0x40000>; + }; + + p0_its_peri_b: interrupt-controller@6c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x6c000000 0x0 0x40000>; + }; + + p0_its_dsa_a: interrupt-controller@c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xc6000000 0x0 0x40000>; + }; + + p0_its_dsa_b: interrupt-controller@8,c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x8 0xc6000000 0x0 0x40000>; + }; + + p1_its_peri_a: interrupt-controller@400,4c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x400 0x4c000000 0x0 0x40000>; + }; + + p1_its_peri_b: interrupt-controller@400,6c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x400 0x6c000000 0x0 0x40000>; + }; + + p1_its_dsa_a: interrupt-controller@400,c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x400 0xc6000000 0x0 0x40000>; + }; + + p1_its_dsa_b: interrupt-controller@408,c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x408 0xc6000000 0x0 0x40000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + p0_mbigen_peri_b: interrupt-controller@60080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0x60080000 0x0 0x10000>; + + mbigen_uart: uart_intc { + msi-parent = <&p0_its_peri_b 0x120c7>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <1>; + }; + }; + + p0_mbigen_pcie_a: interrupt-controller@a0080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xa0080000 0x0 0x10000>; + + mbigen_usb: intc_usb { + msi-parent = <&p0_its_dsa_a 0x40080>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <2>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: uart@602b0000 { + compatible = "arm,sbsa-uart"; + reg = <0x0 0x602b0000 0x0 0x1000>; + interrupt-parent = <&mbigen_uart>; + interrupts = <807 4>; + current-speed = <115200>; + reg-io-width = <4>; + status = "disabled"; + }; + + usb_ohci: ohci@a7030000 { + compatible = "generic-ohci"; + reg = <0x0 0xa7030000 0x0 0x10000>; + interrupt-parent = <&mbigen_usb>; + interrupts = <640 4>; + dma-coherent; + status = "disabled"; + }; + + usb_ehci: ehci@a7020000 { + compatible = "generic-ehci"; + reg = <0x0 0xa7020000 0x0 0x10000>; + interrupt-parent = <&mbigen_usb>; + interrupts = <641 4>; + dma-coherent; + status = "disabled"; + }; + }; +}; From 06b29676555d9c0ccc26a1fa45f9b4ca0bdc4a37 Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Mon, 24 Oct 2016 11:40:28 +0800 Subject: [PATCH 092/168] arm64: dts: hip06: Fix no reg property warning Warning (unit_address_vs_reg): Node /soc/ethernet@4 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/ethernet@5 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/ethernet@0 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/ethernet@1 has a unit name, but no reg property Fix warning when build with W=1. Cc: Kejian Yan Cc: Yisen Zhuang Signed-off-by: Kefeng Wang Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index af450413b9dd..da61e4384eeb 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -508,7 +508,7 @@ port@5 { }; }; - eth0: ethernet@4{ + eth0: ethernet-4{ compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <4>; @@ -517,7 +517,7 @@ eth0: ethernet@4{ dma-coherent; }; - eth1: ethernet@5{ + eth1: ethernet-5{ compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <5>; @@ -526,7 +526,7 @@ eth1: ethernet@5{ dma-coherent; }; - eth2: ethernet@0{ + eth2: ethernet-0{ compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <0>; @@ -535,7 +535,7 @@ eth2: ethernet@0{ dma-coherent; }; - eth3: ethernet@1{ + eth3: ethernet-1{ compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <1>; From f65e786604b34d0b599b8c01ecca28be2d746290 Mon Sep 17 00:00:00 2001 From: John Garry Date: Tue, 8 Nov 2016 00:44:23 +0800 Subject: [PATCH 093/168] arm64: dts: hisi: fix hip06 sas am-max-trans quirk The string for the am max transmissions quirk property is not correct -> fix it. Signed-off-by: John Garry Reviewed-by: Xiang Chen Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index da61e4384eeb..a05ad046cb9a 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -590,7 +590,7 @@ sas1: sas@a2000000 { reg = <0 0xa2000000 0 0x10000>; sas-addr = [50 01 88 20 16 00 00 00]; hisilicon,sas-syscon = <&pcie_subctl>; - am-max-trans; + hip06-sas-v2-quirk-amt; ctrl-reset-reg = <0xa18>; ctrl-reset-sts-reg = <0x5a0c>; ctrl-clock-ena-reg = <0x318>; From 84ad1f54095b563b1d97b52de01e85cdf589830f Mon Sep 17 00:00:00 2001 From: John Garry Date: Tue, 8 Nov 2016 00:44:24 +0800 Subject: [PATCH 094/168] arm64: dts: hisi: disable sas0 and sas2 for d03 The SAS nodes sas0 and sas2 are not available on d03, so disable them. Signed-off-by: John Garry Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts index f54b28359607..7c4114a67753 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts +++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts @@ -41,18 +41,10 @@ ð3 { status = "ok"; }; -&sas0 { - status = "ok"; -}; - &sas1 { status = "ok"; }; -&sas2 { - status = "ok"; -}; - &usb_ohci { status = "ok"; }; From 85f5bd9e771349833602ccdd39b65613ecd11fd1 Mon Sep 17 00:00:00 2001 From: John Garry Date: Tue, 8 Nov 2016 00:44:25 +0800 Subject: [PATCH 095/168] arm64: dts: hisi: add refclk node to hip06 dts files for SAS We will only maintain 1 dts for D03 and there are 50MHz and 66MHz versions of D03: so we expect UEFI to update refclk rate in the fdt at boot time. Signed-off-by: John Garry Reviewed-by: Xiang Chen Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index a05ad046cb9a..a049b64f2101 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -318,6 +318,12 @@ soc { #size-cells = <2>; ranges; + refclk: refclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + usb_ohci: ohci@a7030000 { compatible = "generic-ohci"; reg = <0x0 0xa7030000 0x0 0x10000>; @@ -552,6 +558,7 @@ sas0: sas@c3000000 { ctrl-reset-reg = <0xa60>; ctrl-reset-sts-reg = <0x5a30>; ctrl-clock-ena-reg = <0x338>; + clocks = <&refclk 0>; queue-count = <16>; phy-count = <8>; dma-coherent; @@ -594,6 +601,7 @@ sas1: sas@a2000000 { ctrl-reset-reg = <0xa18>; ctrl-reset-sts-reg = <0x5a0c>; ctrl-clock-ena-reg = <0x318>; + clocks = <&refclk 0>; queue-count = <16>; phy-count = <8>; dma-coherent; @@ -635,6 +643,7 @@ sas2: sas@a3000000 { ctrl-reset-reg = <0xae0>; ctrl-reset-sts-reg = <0x5a70>; ctrl-clock-ena-reg = <0x3a8>; + clocks = <&refclk 0>; queue-count = <16>; phy-count = <9>; dma-coherent; From fe7f2de1c6ca27548559f75e34682506dea6bd07 Mon Sep 17 00:00:00 2001 From: William Wu Date: Mon, 7 Nov 2016 20:08:49 +0800 Subject: [PATCH 096/168] arm64: dts: rockchip: add usb2-phy otg-port support for rk3399 Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can be used for USB2.0 part of USB3.0 OTG controller. Signed-off-by: William Wu Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index fc30b57ac557..0ee4220ddf08 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1128,6 +1128,16 @@ u2phy0_host: host-port { interrupt-names = "linestate"; status = "disabled"; }; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; }; u2phy1: usb2-phy@e460 { @@ -1145,6 +1155,16 @@ u2phy1_host: host-port { interrupt-names = "linestate"; status = "disabled"; }; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; }; emmc_phy: phy@f780 { From eb708b0ff972bfe0e51c38fad6d517fae605ffa8 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Sat, 12 Nov 2016 15:47:12 +0530 Subject: [PATCH 097/168] arm64: dts: Add ARM PMU node for exynos7 This patch adds ARM Performance Monitor Unit dt node for exynos7. PMU provides various statistics on the operation of the CPU and memory system at runtime, which are very useful when debugging or profiling code. This enables the same. Signed-off-by: Alim Akhtar Reviewed-by: Javier Martinez Canillas [krzk: Squashed with "Add level for cpu dt node for exynos7"] Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 6328a66ed97e..d46ac94900f3 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -35,28 +35,28 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu_atlas0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; enable-method = "psci"; }; - cpu@1 { + cpu_atlas1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x1>; enable-method = "psci"; }; - cpu@2 { + cpu_atlas2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x2>; enable-method = "psci"; }; - cpu@3 { + cpu_atlas3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x3>; @@ -472,6 +472,16 @@ hsi2c_11: hsi2c@136a0000 { status = "disabled"; }; + arm-pmu { + compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, + <&cpu_atlas2>, <&cpu_atlas3>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = Date: Wed, 19 Oct 2016 14:51:12 +0200 Subject: [PATCH 098/168] ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 48 +++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index f6b68b046b0a..2d69a3b68de4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -74,6 +74,28 @@ bid: bid@46 { }; }; + scpi { + compatible = "amlogic,meson-gxbb-scpi"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + soc { usb0_phy: phy@c0000000 { compatible = "amlogic,meson-gxbb-usb2-phy"; @@ -101,6 +123,16 @@ sram: sram@c8000000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0xc8000000 0x14000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "amlogic,meson-gxbb-scp-shmem"; + reg = <0x13000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "amlogic,meson-gxbb-scp-shmem"; + reg = <0x13400 0x400>; + }; }; usb0: usb@c9000000 { @@ -143,6 +175,22 @@ ethmac: ethernet@c9410000 { }; }; +&cpu0 { + clocks = <&scpi_dvfs 0>; +}; + +&cpu1 { + clocks = <&scpi_dvfs 0>; +}; + +&cpu2 { + clocks = <&scpi_dvfs 0>; +}; + +&cpu3 { + clocks = <&scpi_dvfs 0>; +}; + &cbus { reset: reset-controller@4404 { compatible = "amlogic,meson-gxbb-reset"; From 998a9c8aa8fdff31e0de33c1c8fe090f9552f4b9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 31 Oct 2016 17:44:39 +0100 Subject: [PATCH 099/168] ARM64: dts: meson-gxbb: Move common nodes to meson-gx Move common nodes between GXBB and GXL in to the common GX dtsi. Leave the clock attributes in the GXBB dtsi for now. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 131 +++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 153 +++----------------- 2 files changed, 148 insertions(+), 136 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index fd1d0deef889..91be4f23f1ac 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -129,6 +129,30 @@ xtal: xtal-clk { #clock-cells = <0>; }; + firmware { + sm: secure-monitor { + compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; + }; + }; + + efuse: efuse { + compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; + #address-cells = <1>; + #size-cells = <1>; + + sn: sn@14 { + reg = <0x14 0x10>; + }; + + eth_mac: eth_mac@34 { + reg = <0x34 0x10>; + }; + + bid: bid@46 { + reg = <0x46 0x30>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -142,6 +166,12 @@ cbus: cbus@c1100000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; + reset: reset-controller@4404 { + compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; + reg = <0x0 0x04404 0x0 0x20>; + #reset-cells = <1>; + }; + uart_A: serial@84c0 { compatible = "amlogic,meson-uart"; reg = <0x0 0x84c0 0x0 0x14>; @@ -149,6 +179,76 @@ uart_A: serial@84c0 { clocks = <&xtal>; status = "disabled"; }; + + uart_B: serial@84dc { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x84dc 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; + status = "disabled"; + }; + + i2c_A: i2c@8500 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x08500 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm_ab: pwm@8550 { + compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x08550 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@8650 { + compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x08650 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@86c0 { + compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x086c0 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + uart_C: serial@8700 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x8700 0x0 0x14>; + interrupts = ; + clocks = <&xtal>; + status = "disabled"; + }; + + i2c_B: i2c@87c0 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x087c0 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_C: i2c@87e0 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x087e0 0x0 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + watchdog@98d0 { + compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt"; + reg = <0x0 0x098d0 0x0 0x10>; + clocks = <&xtal>; + }; }; gic: interrupt-controller@c4301000 { @@ -178,6 +278,13 @@ uart_AO: serial@4c0 { clocks = <&xtal>; status = "disabled"; }; + + ir: ir@580 { + compatible = "amlogic,meson-gxbb-ir"; + reg = <0x0 0x00580 0x0 0x40>; + interrupts = ; + status = "disabled"; + }; }; periphs: periphs@c8834000 { @@ -186,6 +293,11 @@ periphs: periphs@c8834000 { #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; + + rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x0 0x0 0x4>; + }; }; @@ -195,6 +307,25 @@ hiubus: hiubus@c883c000 { #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; + + mailbox: mailbox@404 { + compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; + interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, + <0 209 IRQ_TYPE_EDGE_RISING>, + <0 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; + }; + + ethmac: ethernet@c9410000 { + compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; + reg = <0x0 0xc9410000 0x0 0x10000 + 0x0 0xc8834540 0x0 0x4>; + interrupts = <0 8 1>; + interrupt-names = "macirq"; + phy-mode = "rgmii"; + status = "disabled"; }; apb: apb@d0000000 { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 2d69a3b68de4..160664fd8d63 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -50,30 +50,6 @@ / { compatible = "amlogic,meson-gxbb"; - firmware { - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - }; - - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - #address-cells = <1>; - #size-cells = <1>; - - sn: sn@14 { - reg = <0x14 0x10>; - }; - - eth_mac: eth_mac@34 { - reg = <0x34 0x10>; - }; - - bid: bid@46 { - reg = <0x46 0x30>; - }; - }; - scpi { compatible = "amlogic,meson-gxbb-scpi"; mboxes = <&mailbox 1 &mailbox 2>; @@ -158,20 +134,6 @@ usb1: usb@c9100000 { dr_mode = "host"; status = "disabled"; }; - - ethmac: ethernet@c9410000 { - compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; - reg = <0x0 0xc9410000 0x0 0x10000 - 0x0 0xc8834540 0x0 0x4>; - interrupts = <0 8 1>; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; - phy-mode = "rgmii"; - status = "disabled"; - }; }; }; @@ -192,55 +154,6 @@ &cpu3 { }; &cbus { - reset: reset-controller@4404 { - compatible = "amlogic,meson-gxbb-reset"; - reg = <0x0 0x04404 0x0 0x20>; - #reset-cells = <1>; - }; - - uart_B: serial@84dc { - compatible = "amlogic,meson-uart"; - reg = <0x0 0x84dc 0x0 0x14>; - interrupts = ; - clocks = <&xtal>; - status = "disabled"; - }; - - pwm_ab: pwm@8550 { - compatible = "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08550 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@8650 { - compatible = "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08650 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x086c0 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_C: serial@8700 { - compatible = "amlogic,meson-uart"; - reg = <0x0 0x8700 0x0 0x14>; - interrupts = ; - clocks = <&xtal>; - status = "disabled"; - }; - - watchdog@98d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0x098d0 0x0 0x10>; - clocks = <&xtal>; - }; - spifc: spi@8c80 { compatible = "amlogic,meson-gxbb-spifc"; reg = <0x0 0x08c80 0x0 0x80>; @@ -249,36 +162,13 @@ spifc: spi@8c80 { clocks = <&clkc CLKID_SPI>; status = "disabled"; }; +}; - i2c_A: i2c@8500 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x08500 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_B: i2c@87c0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087c0 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_C: i2c@87e0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087e0 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; +ðmac { + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; }; &aobus { @@ -355,13 +245,6 @@ clkc_AO: clock-controller@040 { #reset-cells = <1>; }; - ir: ir@580 { - compatible = "amlogic,meson-gxbb-ir"; - reg = <0x0 0x00580 0x0 0x40>; - interrupts = ; - status = "disabled"; - }; - pwm_ab_AO: pwm@550 { compatible = "amlogic,meson-gxbb-pwm"; reg = <0x0 0x0550 0x0 0x10>; @@ -381,11 +264,6 @@ i2c_AO: i2c@500 { }; &periphs { - rng { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x0 0x0 0x4>; - }; - pinctrl_periphs: pinctrl@4b0 { compatible = "amlogic,meson-gxbb-periphs-pinctrl"; #address-cells = <2>; @@ -593,15 +471,18 @@ clkc: clock-controller@0 { #clock-cells = <1>; reg = <0x0 0x0 0x0 0x3db>; }; +}; - mailbox: mailbox@404 { - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0x404 0 0x4c>; - interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, - <0 209 IRQ_TYPE_EDGE_RISING>, - <0 210 IRQ_TYPE_EDGE_RISING>; - #mbox-cells = <1>; - }; +&i2c_A { + clocks = <&clkc CLKID_I2C>; +}; + +&i2c_B { + clocks = <&clkc CLKID_I2C>; +}; + +&i2c_C { + clocks = <&clkc CLKID_I2C>; }; &sd_emmc_a { From fb0fe92294a944e7f7dad5ab7751ceaf76e7ba54 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 31 Oct 2016 17:44:40 +0100 Subject: [PATCH 100/168] ARM64: dts: meson-gxl: Add pinctrl nodes Add pinctrl nodes and pin definitions for Amlogic Meson GXL. Signed-off-by: Neil Armstrong [khilman: use GXBB include until GXL pinctrl support merged] Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 168 +++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 13b10eeb80b2..8ddb6868ea1d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -42,7 +42,175 @@ */ #include "meson-gx.dtsi" +#include / { compatible = "amlogic,meson-gxl"; }; + +&aobus { + pinctrl_aobus: pinctrl@14 { + compatible = "amlogic,meson-gxl-aobus-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_ao: bank@14 { + reg = <0x0 0x00014 0x0 0x8>, + <0x0 0x0002c 0x0 0x4>, + <0x0 0x00024 0x0 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; + }; + + remote_input_ao_pins: remote_input_ao { + mux { + groups = "remote_input_ao"; + function = "remote_input_ao"; + }; + }; + }; +}; + +&periphs { + pinctrl_periphs: pinctrl@4b0 { + compatible = "amlogic,meson-gxl-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4b0 { + reg = <0x0 0x004b0 0x0 0x28>, + <0x0 0x004e8 0x0 0x14>, + <0x0 0x00120 0x0 0x14>, + <0x0 0x00430 0x0 0x40>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d07", + "emmc_cmd", + "emmc_clk", + "emmc_ds"; + function = "emmc"; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + }; + }; + + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_cmd", + "sdio_clk"; + function = "sdio"; + }; + }; + + sdio_irq_pins: sdio_irq { + mux { + groups = "sdio_irq"; + function = "sdio"; + }; + }; + + uart_a_pins: uart_a { + mux { + groups = "uart_tx_a", + "uart_rx_a"; + function = "uart_a"; + }; + }; + + uart_b_pins: uart_b { + mux { + groups = "uart_tx_b", + "uart_rx_b"; + function = "uart_b"; + }; + }; + + uart_c_pins: uart_c { + mux { + groups = "uart_tx_c", + "uart_rx_c"; + function = "uart_c"; + }; + }; + + i2c_a_pins: i2c_a { + mux { + groups = "i2c_sck_a", + "i2c_sda_a"; + function = "i2c_a"; + }; + }; + + i2c_b_pins: i2c_b { + mux { + groups = "i2c_sck_b", + "i2c_sda_b"; + function = "i2c_b"; + }; + }; + + i2c_c_pins: i2c_c { + mux { + groups = "i2c_sck_c", + "i2c_sda_c"; + function = "i2c_c"; + }; + }; + + eth_pins: eth_c { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_clk_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2", + "eth_rxd3", + "eth_rgmii_tx_clk", + "eth_tx_en", + "eth_txd0", + "eth_txd1", + "eth_txd2", + "eth_txd3"; + function = "eth"; + }; + }; + + pwm_e_pins: pwm_e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + }; +}; From 973fbd55b53c3e6bd7e2286a809cb3780e08b95f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 31 Oct 2016 17:44:41 +0100 Subject: [PATCH 101/168] ARM64: dts: meson-gxl: Add clock nodes Add clock node for Amlogic Meson GXL. The GXBB compatible is retained since the GXBB clock tree is used for now. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 8ddb6868ea1d..79587c24d433 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -42,6 +42,7 @@ */ #include "meson-gx.dtsi" +#include #include / { @@ -214,3 +215,11 @@ mux { }; }; }; + +&hiubus { + clkc: clock-controller@0 { + compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc"; + #clock-cells = <1>; + reg = <0x0 0x0 0x0 0x3db>; + }; +}; From 5d28bb016cfb0271718628492c833ba61de3d0b1 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 31 Oct 2016 17:44:42 +0100 Subject: [PATCH 102/168] ARM64: dts: meson-gxl: Add i2c nodes Add i2c nodes clock attributes for Amlogic Meson GXL. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 79587c24d433..5aed31937f64 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -223,3 +223,15 @@ clkc: clock-controller@0 { reg = <0x0 0x0 0x0 0x3db>; }; }; + +&i2c_A { + clocks = <&clkc CLKID_I2C>; +}; + +&i2c_B { + clocks = <&clkc CLKID_I2C>; +}; + +&i2c_C { + clocks = <&clkc CLKID_I2C>; +}; From 6d489dc846733ec1f157e827df291c4b4774a207 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 31 Oct 2016 17:44:43 +0100 Subject: [PATCH 103/168] ARM64: dts: meson-gxl: Add MMC/SD/SDIO nodes Add MMC/SD/SDIO nodes clock attributes for Amlogic Meson GXL. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 5aed31937f64..73887fe91d42 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -235,3 +235,24 @@ &i2c_B { &i2c_C { clocks = <&clkc CLKID_I2C>; }; + +&sd_emmc_a { + clocks = <&clkc CLKID_SD_EMMC_A>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +}; + +&sd_emmc_b { + clocks = <&clkc CLKID_SD_EMMC_B>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +}; + +&sd_emmc_c { + clocks = <&clkc CLKID_SD_EMMC_C>, + <&xtal>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; +}; From c67fe414059ddb551db6258d838554f12207f0c2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 31 Oct 2016 17:44:44 +0100 Subject: [PATCH 104/168] ARM64: dts: meson-gxl-p23x: Add uart pinctrl Add pinctrl attribute to p23x uart node. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi index bf08e874eadf..666fe2b5ee86 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi @@ -58,6 +58,9 @@ memory@0 { }; }; +/* This UART is brought out to the DB9 connector */ &uart_AO { status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; }; From 1d92bc896e2ba8ef60f5788735ae2fead66a7149 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 31 Oct 2016 17:44:45 +0100 Subject: [PATCH 105/168] ARM64: dts: meson-gxl-p23x: Add SD/SDIO/MMC and PWM nodes Add SD/SDIO/MMC nodes and PWM 32768Hz clock configuration to provide storage and WiFi functionality on the p23x boards. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- .../dts/amlogic/meson-gxl-s905d-p23x.dtsi | 112 ++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi index 666fe2b5ee86..783080958fce 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi @@ -56,6 +56,46 @@ memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; }; /* This UART is brought out to the DB9 connector */ @@ -64,3 +104,75 @@ &uart_AO { pinctrl-0 = <&uart_ao_a_pins>; pinctrl-names = "default"; }; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; From 72093fac811fcfb29ccd1429c4df945d3852fc1a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 31 Oct 2016 17:44:46 +0100 Subject: [PATCH 106/168] ARM64: dts: meson-gxl-p23x: Enable IR receiver Enable the Infraread Receiver on the p23x board. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi index 783080958fce..bbe46a2b7f14 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi @@ -105,6 +105,12 @@ &uart_AO { pinctrl-names = "default"; }; +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + /* Wireless SDIO Module */ &sd_emmc_a { status = "okay"; From 0e26f26ff3dff94a7f87d67cd2bfa1219fb9368b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 6 Nov 2016 20:25:34 +0100 Subject: [PATCH 107/168] ARM64: dts: amlogic: Reorder copyrights for meson-gx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit meson-gx.dtsi was directly derived from meson-gxbb.dtsi, so keep the copyrights in chronological order to not give a wrong impression. Fixes: c328666d58aa ("ARM64: dts: amlogic: Add Meson GX dtsi from GXBB") Cc: Neil Armstrong Cc: Kevin Hilman Signed-off-by: Andreas Färber Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 91be4f23f1ac..fc033c0d2a0f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -1,12 +1,12 @@ /* + * Copyright (c) 2016 Andreas Färber + * * Copyright (c) 2016 BayLibre, SAS. * Author: Neil Armstrong * * Copyright (c) 2016 Endless Computers, Inc. * Author: Carlo Caione * - * Copyright (c) 2016 Andreas Färber - * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a From e9e27c647cb063b3b0e58d40414852bb00980171 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 7 Nov 2016 11:43:55 +0100 Subject: [PATCH 108/168] ARM64: dts: meson-gxl: Add ethernet nodes with internal PHY Add Ethernet node with Internal PHY selection for the Amlogic GXL SoCs Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 73887fe91d42..9f89b99c4806 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -49,6 +49,22 @@ / { compatible = "amlogic,meson-gxl"; }; +ðmac { + reg = <0x0 0xc9410000 0x0 0x10000 + 0x0 0xc8834540 0x0 0x4>; + + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + &aobus { pinctrl_aobus: pinctrl@14 { compatible = "amlogic,meson-gxl-aobus-pinctrl"; @@ -214,6 +230,33 @@ mux { }; }; }; + + eth-phy-mux { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x55c 0x0 0x4>; + mux-mask = <0xffffffff>; + mdio-parent-bus = <&mdio0>; + + internal_mdio: mdio@e40908ff { + reg = <0xe40908ff>; + #address-cells = <1>; + #size-cells = <0>; + + internal_phy: ethernet-phy@8 { + compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; + reg = <8>; + max-speed = <100>; + }; + }; + + external_mdio: mdio@2009087f { + reg = <0x2009087f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; &hiubus { From 73a5d99febe634ee5fd9f644600246b4262bac2c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 7 Nov 2016 11:43:56 +0100 Subject: [PATCH 109/168] ARM64: dts: meson-gxl-p23x: Enable ethernet Enable Ethernet on the p23x board, pinctrl attribute is only added for the p230 board since the p231 only uses the Internal PHY. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 25 +++++++++++++++++++ .../boot/dts/amlogic/meson-gxl-s905d-p231.dts | 6 +++++ .../dts/amlogic/meson-gxl-s905d-p23x.dtsi | 4 +++ 3 files changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts index 3dfaa37f78f4..4d082a7fdf51 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts @@ -49,3 +49,28 @@ / { compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl"; model = "Amlogic Meson GXL (S905D) P230 Development Board"; }; + +/* P230 has exclusive choice between internal or external PHY */ +ðmac { + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; + + /* Select external PHY by default */ + phy-handle = <&external_phy>; + + /* External PHY reset is shared with internal PHY Led signals */ + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + /* External PHY is in RGMII */ + phy-mode = "rgmii"; +}; + +&external_mdio { + external_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + max-speed = <1000>; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts index ade8d29e5477..1cc8d49d85e4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts @@ -49,3 +49,9 @@ / { compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl"; model = "Amlogic Meson GXL (S905D) P231 Development Board"; }; + +/* P231 has only internal PHY port */ +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi index bbe46a2b7f14..622ffbeba336 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi @@ -182,3 +182,7 @@ &pwm_ef { clocks = <&clkc CLKID_FCLK_DIV4>; clock-names = "clkin0"; }; + +ðmac { + status = "okay"; +}; From 0fbab1516b35f511bf00e603c75d36f9f5f47a59 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 7 Nov 2016 11:43:57 +0100 Subject: [PATCH 110/168] ARM64: dts: meson-gxl-s905x: Enable internal ethernet PHY Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi index 07f0e0bdb363..08237ee1e362 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi @@ -46,3 +46,9 @@ / { compatible = "amlogic,s905x", "amlogic,meson-gxl"; }; + +/* S905X Only has access to its internal PHY */ +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; From ab5b24fdd2d551ea729e8e19e47811a646260331 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 12 Nov 2016 14:07:19 +0100 Subject: [PATCH 111/168] ARM64: dts: meson-gxbb-vega-s95: Add SD/SDIO/MMC and PWM nodes All boards from the Tronsmart Vega S95 series are sharing similar MMC based hardware. sd_emmc_a is used to connect a Broadcom based SDIO wifi card (supported by the brcmfmac driver). The 32.768KHz LPO clock for the wifi chip is generated by PWM_E. sd_emmc_b is routed to the SD-card. Unlike p20x there is no GPIO regulator, meaning it only supports 3.3V (which seems to be hard-wired). The eMMC chip is connected to sd_emmc_c and is implemented similar to the meson-gxbb-p20x boards (meaning that hard-wired fixed regulators are used). Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 104 ++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index e93221af390d..e59ad308192f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -65,6 +65,39 @@ usb_vbus: regulator-usb0-vbus { enable-active-high; }; + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_1v8: regulator-vcc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>, + <&gpio GPIOX_20 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; }; &uart_AO { @@ -102,3 +135,74 @@ &usb0 { &usb1 { status = "okay"; }; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins &sdio_irq_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vcc_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vmmcq-sumpply = <&vcc_1v8>; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; From a5b1ef3c50aa90214bfd10ede5e3806a9720ccf4 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 12 Nov 2016 14:13:05 +0100 Subject: [PATCH 112/168] ARM64: dts: meson-gxbb: add the USB reset also to the second USB PHY When the USB PHY driver was introduced the reset framework did not have support for triggering a reset pulse for shared resets. On GXBB however there is only one reset line for both PHYs (meaning we have a shared reset line). With the latest changes to the reset framework and the corresponding updates to the phy-meson8b-usb2 driver we can now pass the reset to the second PHY as well. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 160664fd8d63..ac5ad3bf1bd6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -87,6 +87,7 @@ usb1_phy: phy@c0000020 { compatible = "amlogic,meson-gxbb-usb2-phy"; #phy-cells = <0>; reg = <0x0 0xc0000020 0x0 0x20>; + resets = <&reset RESET_USB_OTG>; clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; clock-names = "usb_general", "usb"; status = "disabled"; From a44e87b47148c6ee6b78509f47e6a15c0fae890a Mon Sep 17 00:00:00 2001 From: Andrea Merello Date: Fri, 11 Nov 2016 09:38:21 -0800 Subject: [PATCH 113/168] ARM64: dts: bcm2837-rpi-3-b: remove incorrect pwr LED We are incorrectly defining the pwr LED, attaching it to a gpio line that is wired to the Wi-Fi SDIO module (which fails due to this). The actual power LED is connected to the GPIO expander, which we don't expose currently. Fixes: 9d56c22a7861 ("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.") Thanks-to: Eric Anholt [for clarifying we can't control the LED] Signed-off-by: Andrea Merello Signed-off-by: Eric Anholt --- arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts index 7625e57a64b5..c309633a1e87 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts @@ -16,13 +16,6 @@ leds { act { gpios = <&gpio 47 0>; }; - - pwr { - label = "PWR"; - gpios = <&gpio 35 0>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; }; }; From cebef6be66f1654ea64234c07ccc340ac3170f89 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 17 Nov 2016 15:27:29 +0100 Subject: [PATCH 114/168] arm64: dts: exynos: Fix IRQ type flags for Exynos5433 SoC Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts. The GIC requires shared interrupts to be edge rising or level high. Platform declares support for both. Set all interrupts type to level high, as this works fine - tested on Exynos5433-based TM2 board. Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/exynos5433-pinctrl.dtsi | 22 ++- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 129 ++++++++++-------- 2 files changed, 85 insertions(+), 66 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi index 796881310bf6..ad71247b074f 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -40,9 +40,14 @@ gpa0: gpa0 { interrupt-controller; interrupt-parent = <&gic>; - interrupts = , , , - , , , - , ; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; @@ -52,9 +57,14 @@ gpa1: gpa1 { interrupt-controller; interrupt-parent = <&gic>; - interrupts = , , , - , , , - , ; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 1188630823a7..0a70fadfada8 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -526,7 +526,7 @@ cmu_cam1: clock-controller@145d0000 { tmu_atlas0: tmu@10060000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10060000 0x200>; - interrupts = ; + interrupts = ; clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, <&cmu_peris CLK_SCLK_TMU0>; clock-names = "tmu_apbif", "tmu_sclk"; @@ -537,7 +537,7 @@ tmu_atlas0: tmu@10060000 { tmu_atlas1: tmu@10068000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10068000 0x200>; - interrupts = ; + interrupts = ; clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, <&cmu_peris CLK_SCLK_TMU0>; clock-names = "tmu_apbif", "tmu_sclk"; @@ -548,7 +548,7 @@ tmu_atlas1: tmu@10068000 { tmu_g3d: tmu@10070000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10070000 0x200>; - interrupts = ; + interrupts = ; clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; @@ -559,7 +559,7 @@ tmu_g3d: tmu@10070000 { tmu_apollo: tmu@10078000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10078000 0x200>; - interrupts = ; + interrupts = ; clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; @@ -570,7 +570,7 @@ tmu_apollo: tmu@10078000 { tmu_isp: tmu@1007c000 { compatible = "samsung,exynos5433-tmu"; reg = <0x1007c000 0x200>; - interrupts = ; + interrupts = ; clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; @@ -581,12 +581,18 @@ tmu_isp: tmu@1007c000 { mct@101c0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101c0000 0x800>; - interrupts = , , - , , - , , - , , - , , - , ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>; clock-names = "fin_pll", "mct"; }; @@ -597,62 +603,62 @@ pinctrl_alive: pinctrl@10580000 { wakeup-interrupt-controller { compatible = "samsung,exynos7-wakeup-eint"; - interrupts = ; + interrupts = ; }; }; pinctrl_aud: pinctrl@114b0000 { compatible = "samsung,exynos5433-pinctrl"; reg = <0x114b0000 0x1000>; - interrupts = ; + interrupts = ; }; pinctrl_cpif: pinctrl@10fe0000 { compatible = "samsung,exynos5433-pinctrl"; reg = <0x10fe0000 0x1000>; - interrupts = ; + interrupts = ; }; pinctrl_ese: pinctrl@14ca0000 { compatible = "samsung,exynos5433-pinctrl"; reg = <0x14ca0000 0x1000>; - interrupts = ; + interrupts = ; }; pinctrl_finger: pinctrl@14cb0000 { compatible = "samsung,exynos5433-pinctrl"; reg = <0x14cb0000 0x1000>; - interrupts = ; + interrupts = ; }; pinctrl_fsys: pinctrl@15690000 { compatible = "samsung,exynos5433-pinctrl"; reg = <0x15690000 0x1000>; - interrupts = ; + interrupts = ; }; pinctrl_imem: pinctrl@11090000 { compatible = "samsung,exynos5433-pinctrl"; reg = <0x11090000 0x1000>; - interrupts = ; + interrupts = ; }; pinctrl_nfc: pinctrl@14cd0000 { compatible = "samsung,exynos5433-pinctrl"; reg = <0x14cd0000 0x1000>; - interrupts = ; + interrupts = ; }; pinctrl_peric: pinctrl@14cc0000 { compatible = "samsung,exynos5433-pinctrl"; reg = <0x14cc0000 0x1100>; - interrupts = ; + interrupts = ; }; pinctrl_touch: pinctrl@14ce0000 { compatible = "samsung,exynos5433-pinctrl"; reg = <0x14ce0000 0x1100>; - interrupts = ; + interrupts = ; }; pmu_system_controller: system-controller@105c0000 { @@ -697,8 +703,9 @@ decon: decon@13800000 { "aclk_xiu_decon0x", "pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk"; interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = , , - ; + interrupts = , + , + ; samsung,disp-sysreg = <&syscon_disp>; status = "disabled"; iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; @@ -721,7 +728,7 @@ decon_to_mic: endpoint { dsi: dsi@13900000 { compatible = "samsung,exynos5433-mipi-dsi"; reg = <0x13900000 0xC0>; - interrupts = ; + interrupts = ; phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&cmu_disp CLK_PCLK_DSIM0>, @@ -799,7 +806,7 @@ syscon_cam1: syscon@145f0000 { sysmmu_decon0x: sysmmu@0x13a00000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a00000 0x1000>; - interrupts = ; + interrupts = ; clock-names = "pclk", "aclk"; clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>; @@ -809,7 +816,7 @@ sysmmu_decon0x: sysmmu@0x13a00000 { sysmmu_decon1x: sysmmu@0x13a10000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a10000 0x1000>; - interrupts = ; + interrupts = ; clock-names = "pclk", "aclk"; clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>, <&cmu_disp CLK_ACLK_SMMU_DECON1X>; @@ -819,7 +826,7 @@ sysmmu_decon1x: sysmmu@0x13a10000 { serial_0: serial@14c10000 { compatible = "samsung,exynos5433-uart"; reg = <0x14c10000 0x100>; - interrupts = ; + interrupts = ; clocks = <&cmu_peric CLK_PCLK_UART0>, <&cmu_peric CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; @@ -831,7 +838,7 @@ serial_0: serial@14c10000 { serial_1: serial@14c20000 { compatible = "samsung,exynos5433-uart"; reg = <0x14c20000 0x100>; - interrupts = ; + interrupts = ; clocks = <&cmu_peric CLK_PCLK_UART1>, <&cmu_peric CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; @@ -843,7 +850,7 @@ serial_1: serial@14c20000 { serial_2: serial@14c30000 { compatible = "samsung,exynos5433-uart"; reg = <0x14c30000 0x100>; - interrupts = ; + interrupts = ; clocks = <&cmu_peric CLK_PCLK_UART2>, <&cmu_peric CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; @@ -855,7 +862,7 @@ serial_2: serial@14c30000 { spi_0: spi@14d20000 { compatible = "samsung,exynos5433-spi"; reg = <0x14d20000 0x100>; - interrupts = ; + interrupts = ; dmas = <&pdma0 9>, <&pdma0 8>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -874,7 +881,7 @@ spi_0: spi@14d20000 { spi_1: spi@14d30000 { compatible = "samsung,exynos5433-spi"; reg = <0x14d30000 0x100>; - interrupts = ; + interrupts = ; dmas = <&pdma0 11>, <&pdma0 10>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -893,7 +900,7 @@ spi_1: spi@14d30000 { spi_2: spi@14d40000 { compatible = "samsung,exynos5433-spi"; reg = <0x14d40000 0x100>; - interrupts = ; + interrupts = ; dmas = <&pdma0 13>, <&pdma0 12>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -912,7 +919,7 @@ spi_2: spi@14d40000 { spi_3: spi@14d50000 { compatible = "samsung,exynos5433-spi"; reg = <0x14d50000 0x100>; - interrupts = ; + interrupts = ; dmas = <&pdma0 23>, <&pdma0 22>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -931,7 +938,7 @@ spi_3: spi@14d50000 { spi_4: spi@14d00000 { compatible = "samsung,exynos5433-spi"; reg = <0x14d00000 0x100>; - interrupts = ; + interrupts = ; dmas = <&pdma0 25>, <&pdma0 24>; dma-names = "tx", "rx"; #address-cells = <1>; @@ -950,7 +957,7 @@ spi_4: spi@14d00000 { adc: adc@14d10000 { compatible = "samsung,exynos7-adc"; reg = <0x14d10000 0x100>; - interrupts = ; + interrupts = ; clock-names = "adc"; clocks = <&cmu_peric CLK_PCLK_ADCIF>; #io-channel-cells = <1>; @@ -961,9 +968,11 @@ adc: adc@14d10000 { pwm: pwm@14dd0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x14dd0000 0x100>; - interrupts = , , - , , - ; + interrupts = , + , + , + , + ; samsung,pwm-outputs = <0>, <1>, <2>, <3>; clocks = <&cmu_peric CLK_PCLK_PWM>; clock-names = "timers"; @@ -974,7 +983,7 @@ pwm: pwm@14dd0000 { hsi2c_0: hsi2c@14e40000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e40000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -987,7 +996,7 @@ hsi2c_0: hsi2c@14e40000 { hsi2c_1: hsi2c@14e50000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e50000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -1000,7 +1009,7 @@ hsi2c_1: hsi2c@14e50000 { hsi2c_2: hsi2c@14e60000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e60000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -1013,7 +1022,7 @@ hsi2c_2: hsi2c@14e60000 { hsi2c_3: hsi2c@14e70000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e70000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -1026,7 +1035,7 @@ hsi2c_3: hsi2c@14e70000 { hsi2c_4: hsi2c@14ec0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ec0000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -1039,7 +1048,7 @@ hsi2c_4: hsi2c@14ec0000 { hsi2c_5: hsi2c@14ed0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ed0000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -1052,7 +1061,7 @@ hsi2c_5: hsi2c@14ed0000 { hsi2c_6: hsi2c@14ee0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ee0000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -1065,7 +1074,7 @@ hsi2c_6: hsi2c@14ee0000 { hsi2c_7: hsi2c@14ef0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14ef0000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -1078,7 +1087,7 @@ hsi2c_7: hsi2c@14ef0000 { hsi2c_8: hsi2c@14d90000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14d90000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -1091,7 +1100,7 @@ hsi2c_8: hsi2c@14d90000 { hsi2c_9: hsi2c@14da0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14da0000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -1104,7 +1113,7 @@ hsi2c_9: hsi2c@14da0000 { hsi2c_10: hsi2c@14de0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14de0000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -1117,7 +1126,7 @@ hsi2c_10: hsi2c@14de0000 { hsi2c_11: hsi2c@14df0000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14df0000 0x1000>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; @@ -1148,7 +1157,7 @@ usbdrd30: usb@15400000 { dwc3@15400000 { compatible = "snps,dwc3"; reg = <0x15400000 0x10000>; - interrupts = ; + interrupts = ; phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>; phy-names = "usb2-phy", "usb3-phy"; }; @@ -1215,7 +1224,7 @@ usbhost30: usb@15a00000 { usbdrd_dwc3_0: dwc3@15a00000 { compatible = "snps,dwc3"; reg = <0x15a00000 0x10000>; - interrupts = ; + interrupts = ; phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>; phy-names = "usb2-phy", "usb3-phy"; }; @@ -1223,7 +1232,7 @@ usbdrd_dwc3_0: dwc3@15a00000 { mshc_0: mshc@15540000 { compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x15540000 0x2000>; @@ -1236,7 +1245,7 @@ mshc_0: mshc@15540000 { mshc_1: mshc@15550000 { compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x15550000 0x2000>; @@ -1249,7 +1258,7 @@ mshc_1: mshc@15550000 { mshc_2: mshc@15560000 { compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; reg = <0x15560000 0x2000>; @@ -1269,7 +1278,7 @@ amba { pdma0: pdma@15610000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x15610000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&cmu_fsys CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -1280,7 +1289,7 @@ pdma0: pdma@15610000 { pdma1: pdma@15600000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x15600000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&cmu_fsys CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -1300,7 +1309,7 @@ audio-subsystem@11400000 { adma: adma@11420000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11420000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&cmu_aud CLK_ACLK_DMAC>; clock-names = "apb_pclk"; #dma-cells = <1>; @@ -1313,7 +1322,7 @@ i2s0: i2s0@11440000 { reg = <0x11440000 0x100>; dmas = <&adma 0 &adma 2>; dma-names = "tx", "rx"; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, @@ -1328,7 +1337,7 @@ i2s0: i2s0@11440000 { serial_3: serial@11460000 { compatible = "samsung,exynos5433-uart"; reg = <0x11460000 0x100>; - interrupts = ; + interrupts = ; clocks = <&cmu_aud CLK_PCLK_AUD_UART>, <&cmu_aud CLK_SCLK_AUD_UART>; clock-names = "uart", "clk_uart_baud0"; From e206f85cfb4303b55edbf54b1284120c68f0da95 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 17 Nov 2016 09:57:57 +0100 Subject: [PATCH 115/168] arm64: dts: exynos: Fix FSYS CMU parent clocks in Exynos5433 SoC This patch corrects FSYS CMU parent clocks specified in clock controller node to let improved Exynos5433 clocks driver to control proper clocks on FSYS<->TOP CMU boundary. Signed-off-by: Marek Szyprowski Reviewed-by: Sylwester Nawrocki Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0a70fadfada8..f5dab754d61f 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -312,7 +312,7 @@ cmu_fsys: clock-controller@156e0000 { clock-names = "oscclk", "sclk_ufs_mphy", - "div_aclk_fsys_200", + "aclk_fsys_200", "sclk_pcie_100_fsys", "sclk_ufsunipro_fsys", "sclk_mmc2_fsys", @@ -322,7 +322,7 @@ cmu_fsys: clock-controller@156e0000 { "sclk_usbdrd30_fsys"; clocks = <&xxti>, <&cmu_cpif CLK_SCLK_UFS_MPHY>, - <&cmu_top CLK_DIV_ACLK_FSYS_200>, + <&cmu_top CLK_ACLK_FSYS_200>, <&cmu_top CLK_SCLK_PCIE_100_FSYS>, <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, <&cmu_top CLK_SCLK_MMC2_FSYS>, From e681376e6231321f0930154581f4f8afa3c6b20c Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 17 Nov 2016 09:57:58 +0100 Subject: [PATCH 116/168] arm64: dts: exynos: Add missing parent clocks to audio block in Exynos5433 SoC Audio PLL and oscillator clocks are proper parent clocks for AUD CMU. They are not visible as such on first glance on Exynos5433 SoC docs, but they are needed for this CMU to operate properly. Signed-off-by: Marek Szyprowski Reviewed-by: Sylwester Nawrocki Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index f5dab754d61f..71e2313b74cd 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -374,6 +374,8 @@ cmu_aud: clock-controller@114c0000 { compatible = "samsung,exynos5433-cmu-aud"; reg = <0x114c0000 0x1000>; #clock-cells = <1>; + clock-names = "oscclk", "fout_aud_pll"; + clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; }; cmu_bus0: clock-controller@13600000 { From 4c9eec94a556b11af1ce268d6a25aafbb20f48ce Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 17 Nov 2016 09:57:59 +0100 Subject: [PATCH 117/168] arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi to TM2 dts Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is a board specific item. Signed-off-by: Marek Szyprowski Reviewed-by: Sylwester Nawrocki Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 23 +++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 28 ------------------- 2 files changed, 23 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index 9ea3f32bae9e..3f6d069c8f7e 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -158,6 +158,29 @@ thermistor-charger { }; }; +&cmu_fsys { + assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, + <&cmu_top CLK_MOUT_SCLK_USBHOST30>, + <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, + <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>, + <&cmu_top CLK_DIV_SCLK_USBDRD30>, + <&cmu_top CLK_DIV_SCLK_USBHOST30>; + assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>, + <&cmu_top CLK_MOUT_BUS_PLL_USER>, + <&cmu_top CLK_SCLK_USBDRD30_FSYS>, + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; + assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, + <66700000>, <66700000>; +}; + &cpu0 { cpu-supply = <&buck3_reg>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 71e2313b74cd..7d718272caf6 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1143,14 +1143,6 @@ usbdrd30: usb@15400000 { clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&cmu_fsys CLK_SCLK_USBDRD30>; clock-names = "usbdrd30", "usbdrd30_susp_clk"; - assigned-clocks = - <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, - <&cmu_top CLK_MOUT_SCLK_USBDRD30>, - <&cmu_top CLK_DIV_SCLK_USBDRD30>; - assigned-clock-parents = - <&cmu_top CLK_SCLK_USBDRD30_FSYS>, - <&cmu_top CLK_MOUT_BUS_PLL_USER>; - assigned-clock-rates = <0>, <0>, <66700000>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -1174,12 +1166,6 @@ usbdrd30_phy: phy@15500000 { <&cmu_fsys CLK_SCLK_USBDRD30>; clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; - assigned-clocks = - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>; - assigned-clock-parents = - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>; #phy-cells = <1>; samsung,pmu-syscon = <&pmu_system_controller>; status = "disabled"; @@ -1194,12 +1180,6 @@ usbhost30_phy: phy@15580000 { <&cmu_fsys CLK_SCLK_USBHOST30>; clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; - assigned-clocks = - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>; - assigned-clock-parents = - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; #phy-cells = <1>; samsung,pmu-syscon = <&pmu_system_controller>; status = "disabled"; @@ -1210,14 +1190,6 @@ usbhost30: usb@15a00000 { clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&cmu_fsys CLK_SCLK_USBHOST30>; clock-names = "usbdrd30", "usbdrd30_susp_clk"; - assigned-clocks = - <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, - <&cmu_top CLK_MOUT_SCLK_USBHOST30>, - <&cmu_top CLK_DIV_SCLK_USBHOST30>; - assigned-clock-parents = - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_top CLK_MOUT_BUS_PLL_USER>; - assigned-clock-rates = <0>, <0>, <66700000>; #address-cells = <1>; #size-cells = <1>; ranges; From d41fa3f0281217f750c3d1cd9c7852f8aed4107f Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Thu, 17 Nov 2016 09:58:00 +0100 Subject: [PATCH 118/168] arm64: dts: exynos: Assign parent clock of the clkout clock for TM2 board Without this patch the clkout clock is orphaned and sound doesn't work properly. Signed-off-by: Sylwester Nawrocki Signed-off-by: Marek Szyprowski Reviewed-by: Sylwester Nawrocki Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index 3f6d069c8f7e..f8526cee54c1 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -905,6 +905,11 @@ i80-if-timings { }; }; +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&xxti>; +}; + &serial_1 { status = "okay"; }; From 4eb74a7c24d76c2f741ab745ea0fce4ea2beb0e1 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 17 Nov 2016 09:58:01 +0100 Subject: [PATCH 119/168] arm64: dts: exynos: TM2 - remove unused UART3 and set clocks directly on CMU UART3 device is not really needed for enabling audio block on TM2. Enabling it made it working by enabling some common parent clocks, what is now handled by improved exynos5433 clocks driver. Thus the UART3 device node can be safely disabled. The assigned-clocks entries are however still needed, so move them under the respective CMU node. Signed-off-by: Marek Szyprowski Reviewed-by: Sylwester Nawrocki Reviewed-by: Chanwoo Choi Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index f8526cee54c1..2569e4ab6f7e 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -158,6 +158,11 @@ thermistor-charger { }; }; +&cmu_aud { + assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>; + assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>; +}; + &cmu_fsys { assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, <&cmu_top CLK_MOUT_SCLK_USBHOST30>, @@ -914,12 +919,6 @@ &serial_1 { status = "okay"; }; -&serial_3 { - assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>; - assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>; - status = "okay"; -}; - &spi_1 { cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>; status = "okay"; From 88b9ca09c5ce9988760a2b2f6f55fece0ffd4301 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 18 Nov 2016 13:23:11 +0100 Subject: [PATCH 120/168] arm64: dts: exynos: TM2 - add support for GScaler devices This patch adds device nodes for GScaler devices to Exynos5433 SoC dtsi and proper initial clock configuration to TM2 dts. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 10 +++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 69 +++++++++++++++++++ 2 files changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index 2569e4ab6f7e..8eb59adc2bc4 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -23,6 +23,9 @@ / { compatible = "samsung,tm2", "samsung,exynos5433"; aliases { + gsc0 = &gsc_0; + gsc1 = &gsc_1; + gsc2 = &gsc_2; pinctrl0 = &pinctrl_alive; pinctrl1 = &pinctrl_aud; pinctrl2 = &pinctrl_cpif; @@ -186,6 +189,13 @@ &cmu_fsys { <66700000>, <66700000>; }; +&cmu_gscl { + assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>, + <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>; + assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>, + <&cmu_top CLK_ACLK_GSCL_333>; +}; + &cpu0 { cpu-supply = <&buck3_reg>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 7d718272caf6..945b2502a4ca 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -805,6 +805,45 @@ syscon_cam1: syscon@145f0000 { reg = <0x145f0000 0x1038>; }; + gsc_0: video-scaler@13C00000 { + compatible = "samsung,exynos5433-gsc"; + reg = <0x13c00000 0x1000>; + interrupts = ; + clock-names = "pclk", "aclk", "aclk_xiu", + "aclk_gsclbend"; + clocks = <&cmu_gscl CLK_PCLK_GSCL0>, + <&cmu_gscl CLK_ACLK_GSCL0>, + <&cmu_gscl CLK_ACLK_XIU_GSCLX>, + <&cmu_gscl CLK_ACLK_GSCLBEND_333>; + iommus = <&sysmmu_gscl0>; + }; + + gsc_1: video-scaler@13C10000 { + compatible = "samsung,exynos5433-gsc"; + reg = <0x13c10000 0x1000>; + interrupts = ; + clock-names = "pclk", "aclk", "aclk_xiu", + "aclk_gsclbend"; + clocks = <&cmu_gscl CLK_PCLK_GSCL1>, + <&cmu_gscl CLK_ACLK_GSCL1>, + <&cmu_gscl CLK_ACLK_XIU_GSCLX>, + <&cmu_gscl CLK_ACLK_GSCLBEND_333>; + iommus = <&sysmmu_gscl1>; + }; + + gsc_2: video-scaler@13C20000 { + compatible = "samsung,exynos5433-gsc"; + reg = <0x13c20000 0x1000>; + interrupts = ; + clock-names = "pclk", "aclk", "aclk_xiu", + "aclk_gsclbend"; + clocks = <&cmu_gscl CLK_PCLK_GSCL2>, + <&cmu_gscl CLK_ACLK_GSCL2>, + <&cmu_gscl CLK_ACLK_XIU_GSCLX>, + <&cmu_gscl CLK_ACLK_GSCLBEND_333>; + iommus = <&sysmmu_gscl2>; + }; + sysmmu_decon0x: sysmmu@0x13a00000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a00000 0x1000>; @@ -825,6 +864,36 @@ sysmmu_decon1x: sysmmu@0x13a10000 { #iommu-cells = <0>; }; + sysmmu_gscl0: sysmmu@0x13C80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13C80000 0x1000>; + interrupts = ; + clock-names = "aclk", "pclk"; + clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>, + <&cmu_gscl CLK_PCLK_SMMU_GSCL0>; + #iommu-cells = <0>; + }; + + sysmmu_gscl1: sysmmu@0x13C90000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13C90000 0x1000>; + interrupts = ; + clock-names = "aclk", "pclk"; + clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>, + <&cmu_gscl CLK_PCLK_SMMU_GSCL1>; + #iommu-cells = <0>; + }; + + sysmmu_gscl2: sysmmu@0x13CA0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13CA0000 0x1000>; + interrupts = ; + clock-names = "aclk", "pclk"; + clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>, + <&cmu_gscl CLK_PCLK_SMMU_GSCL2>; + #iommu-cells = <0>; + }; + serial_0: serial@14c10000 { compatible = "samsung,exynos5433-uart"; reg = <0x14c10000 0x100>; From e036c75ae2fabc89a95fd09943e2a9d4a45e47e3 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 18 Nov 2016 13:23:12 +0100 Subject: [PATCH 121/168] arm64: dts: exynos: TM2 - add support for JPEG codec device This patch adds device nodes for JPEG codec device to Exynos5433 SoC dtsi and proper initial clock configuration to TM2 dts. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 11 ++++++++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 22 +++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index 8eb59adc2bc4..6f506dd11714 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -196,6 +196,17 @@ &cmu_gscl { <&cmu_top CLK_ACLK_GSCL_333>; }; +&cmu_mscl { + assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>, + <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, + <&cmu_mscl CLK_MOUT_SCLK_JPEG>, + <&cmu_top CLK_MOUT_SCLK_JPEG_A>; + assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>, + <&cmu_top CLK_SCLK_JPEG_MSCL>, + <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, + <&cmu_top CLK_MOUT_BUS_PLL_USER>; +}; + &cpu0 { cpu-supply = <&buck3_reg>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 945b2502a4ca..1d47480f4104 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -844,6 +844,18 @@ gsc_2: video-scaler@13C20000 { iommus = <&sysmmu_gscl2>; }; + jpeg: codec@15020000 { + compatible = "samsung,exynos5433-jpeg"; + reg = <0x15020000 0x10000>; + interrupts = ; + clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; + clocks = <&cmu_mscl CLK_PCLK_JPEG>, + <&cmu_mscl CLK_ACLK_JPEG>, + <&cmu_mscl CLK_ACLK_XIU_MSCLX>, + <&cmu_mscl CLK_SCLK_JPEG>; + iommus = <&sysmmu_jpeg>; + }; + sysmmu_decon0x: sysmmu@0x13a00000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a00000 0x1000>; @@ -894,6 +906,16 @@ sysmmu_gscl2: sysmmu@0x13CA0000 { #iommu-cells = <0>; }; + sysmmu_jpeg: sysmmu@0x15060000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x15060000 0x1000>; + interrupts = ; + clock-names = "pclk", "aclk"; + clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>, + <&cmu_mscl CLK_ACLK_SMMU_JPEG>; + #iommu-cells = <0>; + }; + serial_0: serial@14c10000 { compatible = "samsung,exynos5433-uart"; reg = <0x14c10000 0x100>; From 74c78036d5b5970266fa2075a17c9b89cabf873e Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 18 Nov 2016 13:23:13 +0100 Subject: [PATCH 122/168] arm64: dts: exynos: TM2 - add support for MFC video codec device This patch adds device nodes for MFC video codec device to Exynos5433 SoC dtsi and proper initial clock configuration to TM2 dts. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 5 +++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 32 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index 6f506dd11714..ce4178126272 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -196,6 +196,11 @@ &cmu_gscl { <&cmu_top CLK_ACLK_GSCL_333>; }; +&cmu_mfc { + assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>; + assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>; +}; + &cmu_mscl { assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>, <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 1d47480f4104..64226d5ae471 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -856,6 +856,18 @@ jpeg: codec@15020000 { iommus = <&sysmmu_jpeg>; }; + mfc: codec@152E0000 { + compatible = "samsung,exynos5433-mfc"; + reg = <0x152E0000 0x10000>; + interrupts = ; + clock-names = "pclk", "aclk", "aclk_xiu"; + clocks = <&cmu_mfc CLK_PCLK_MFC>, + <&cmu_mfc CLK_ACLK_MFC>, + <&cmu_mfc CLK_ACLK_XIU_MFCX>; + iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; + iommu-names = "left", "right"; + }; + sysmmu_decon0x: sysmmu@0x13a00000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a00000 0x1000>; @@ -916,6 +928,26 @@ sysmmu_jpeg: sysmmu@0x15060000 { #iommu-cells = <0>; }; + sysmmu_mfc_0: sysmmu@0x15200000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x15200000 0x1000>; + interrupts = ; + clock-names = "pclk", "aclk"; + clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>, + <&cmu_mfc CLK_ACLK_SMMU_MFC_0>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_1: sysmmu@0x15210000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x15210000 0x1000>; + interrupts = ; + clock-names = "pclk", "aclk"; + clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>, + <&cmu_mfc CLK_ACLK_SMMU_MFC_1>; + #iommu-cells = <0>; + }; + serial_0: serial@14c10000 { compatible = "samsung,exynos5433-uart"; reg = <0x14c10000 0x100>; From ee5d561963886d2c9b98d1891f9bb485deec091e Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 7 Nov 2016 15:00:15 +0100 Subject: [PATCH 123/168] arm64: dts: marvell: Fixup internal-regs DT warning for Armada 37xx internal-regs has a ranges property so the unit name should contain an address. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index c4762538ec01..f1596daa2bc7 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -91,7 +91,7 @@ soc { #size-cells = <2>; ranges; - internal-regs { + internal-regs@d0000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; From 70347888dca1978cd52c322fc5ce778c9825966c Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 7 Nov 2016 15:02:06 +0100 Subject: [PATCH 124/168] arm64: dts: marvell: Fixup config-space DT warning For Armada 7K/8K config-space has a ranges property so the unit name should contain an address. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 7b6136182ad0..a749ba2edec4 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -71,7 +71,7 @@ ap806 { interrupt-parent = <&gic>; ranges; - config-space { + config-space@f0000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index e5e3ed678b6f..607e9a3ef834 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -52,7 +52,7 @@ cp110-master { interrupt-parent = <&gic>; ranges; - config-space { + config-space@f2000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 842fb333285c..88e74069c666 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -52,7 +52,7 @@ cp110-slave { interrupt-parent = <&gic>; ranges; - config-space { + config-space@f4000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; From 3684534548d4cbba7d3724b3d79152eff38dc82f Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 7 Nov 2016 15:03:51 +0100 Subject: [PATCH 125/168] ARM64: dts: marvell: Fixup memory DT warning for Armada 37xx memory has a reg property so the unit name should contain an address. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 2 +- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index 1372e9a6aaa4..a260ae25b658 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -56,7 +56,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x20000000>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index eadd5993c7bd..83178d909fc2 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -55,7 +55,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x20000000>; }; From fcb008a75702c9932f54e5425e7c12b0ea5cf487 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 26 Oct 2016 16:14:07 +0200 Subject: [PATCH 126/168] arm64: dts: r8a7796: add I2C support Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 94 ++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index f9cb7796ad49..2e940ff61378 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -17,6 +17,16 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -239,6 +249,90 @@ sysc: system-controller@e6180000 { #power-domain-cells = <1>; }; + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a7796", "renesas,rcar-gen3-scif", "renesas,scif"; From c758f4e333ee7473056484f7ea2294cb1e58c9d5 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 26 Oct 2016 16:14:08 +0200 Subject: [PATCH 127/168] arm64: dts: r8a7796: Enable I2C DMA Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 2e940ff61378..9599f5691099 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -257,6 +257,9 @@ i2c0: i2c@e6500000 { interrupts = ; clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -269,6 +272,9 @@ i2c1: i2c@e6508000 { interrupts = ; clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -281,6 +287,9 @@ i2c2: i2c@e6510000 { interrupts = ; clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -293,6 +302,8 @@ i2c3: i2c@e66d0000 { interrupts = ; clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -305,6 +316,8 @@ i2c4: i2c@e66d8000 { interrupts = ; clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -317,6 +330,8 @@ i2c5: i2c@e66e0000 { interrupts = ; clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -329,6 +344,8 @@ i2c6: i2c@e66e8000 { interrupts = ; clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; From 20b93fbb08bd38f094186f604e4e5bdafe23f817 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 26 Oct 2016 16:14:09 +0200 Subject: [PATCH 128/168] arm64: dts: r8a7796: salvator-x: enable I2C Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index a9c296b1e1b7..f35e96ca7d60 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -111,6 +111,11 @@ scif_clk_pins: scif_clk { function = "scif_clk"; }; + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -208,6 +213,13 @@ &scif_clk { status = "okay"; }; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; From d65e3e4a7b31328522642882fd8bb9bde11e77d8 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 3 Nov 2016 21:04:44 +0300 Subject: [PATCH 129/168] arm64: dts: h3ulcb: update documentation with official board name This updates H3ULCB Device tree bindings Documentation with official board name Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 2f0b7169f132..1c2499ca1bee 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -49,7 +49,7 @@ Boards: compatible = "renesas,genmai", "renesas,r7s72100" - Gose compatible = "renesas,gose", "renesas,r8a7793" - - H3ULCB (RTP0RC7795SKB00010S) + - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKB00010S) compatible = "renesas,h3ulcb", "renesas,r8a7795"; - Henninger compatible = "renesas,henninger", "renesas,r8a7791" From c77c97557614f07c72393eafa09ef826e0924293 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 3 Nov 2016 21:04:54 +0300 Subject: [PATCH 130/168] arm64: dts: h3ulcb: update header This updates H3ULCB device tree header with official board name Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index bcb11a868343..f178fe1730de 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for the H3ULCB board + * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Cogent Embedded, Inc. From 76b5bba9855e4cd572e3cb44cd7c95b2043f7aee Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 3 Nov 2016 21:06:57 +0300 Subject: [PATCH 131/168] arm64: dts: m3ulcb: add M3ULCB board DT bindings Add M3ULCB Device tree bindings Documentation, listing it as a supported board. Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 1c2499ca1bee..29bf24ca0b7b 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -61,6 +61,8 @@ Boards: compatible = "renesas,kzm9g", "renesas,sh73a0" - Lager (RTP0RC7790SEB00010S) compatible = "renesas,lager", "renesas,r8a7790" + - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKB00010S) + compatible = "renesas,m3ulcb", "renesas,r8a7796"; - Marzen compatible = "renesas,marzen", "renesas,r8a7779" - Porter (M2-LCDP) From d9b1c753878310c90e8be178f6a8e119fd0aa25d Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 3 Nov 2016 21:07:09 +0300 Subject: [PATCH 132/168] arm64: dts: m3ulcb: initial device tree Add the initial device tree for the R8A7796 SoC based M3ULCB low cost board (R-Car Starter Kit Pro) This commit supports the following peripherals: - SCIF (console) Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/Makefile | 2 +- .../arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 51 +++++++++++++++++++ 2 files changed, 52 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index eb72830ec9eb..1618e0a3c81d 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -1,5 +1,5 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb -dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb +dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb always := $(dtb-y) clean-files := *.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts new file mode 100644 index 000000000000..1ae0708bb495 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -0,0 +1,51 @@ +/* + * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7796.dtsi" +#include + +/ { + model = "Renesas M3ULCB board based on r8a7796"; + compatible = "renesas,m3ulcb", "renesas,r8a7796"; + + aliases { + serial0 = &scif2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&pfc { + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; From d92ce1a57480e17aff1fb8693cc919bb46a6e0fd Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 3 Nov 2016 21:07:20 +0300 Subject: [PATCH 133/168] arm64: dts: m3ulcb: enable SCIF clk and pins This enables the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index 1ae0708bb495..96cda59c2698 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -37,10 +37,18 @@ &extal_clk { }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; }; &scif2 { @@ -49,3 +57,8 @@ &scif2 { status = "okay"; }; + +&scif_clk { + clock-frequency = <14745600>; + status = "okay"; +}; From 811a0d07e68ed3bb576e2f193f2c9831bb25c04e Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 3 Nov 2016 21:07:31 +0300 Subject: [PATCH 134/168] arm64: dts: m3ulcb: enable GPIO leds This supports GPIO leds on M3ULCB board Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index 96cda59c2698..49162bd488f8 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -30,6 +30,17 @@ memory@48000000 { /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + leds { + compatible = "gpio-leds"; + + led5 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + }; + led6 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + }; + }; }; &extal_clk { From 96cc1e177c1260e53ac39a0fb109f5d9e7300b09 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 3 Nov 2016 21:07:43 +0300 Subject: [PATCH 135/168] arm64: dts: m3ulcb: enable GPIO keys This supports GPIO keys on M3ULCB board Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index 49162bd488f8..2f8f183ea0cd 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -12,6 +12,7 @@ /dts-v1/; #include "r8a7796.dtsi" #include +#include / { model = "Renesas M3ULCB board based on r8a7796"; @@ -41,6 +42,18 @@ led6 { gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; }; }; + + keyboard { + compatible = "gpio-keys"; + + key-1 { + linux,code = ; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + }; + }; }; &extal_clk { From 7be98b473d407583d29baad10df50639fd63b213 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 3 Nov 2016 21:08:02 +0300 Subject: [PATCH 136/168] arm64: dts: m3ulcb: enable EXTALR clk This enables EXTALR clock that can be used for the watchdog. Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index 2f8f183ea0cd..5567c46f3753 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -60,6 +60,10 @@ &extal_clk { clock-frequency = <16666666>; }; +&extalr_clk { + clock-frequency = <32768>; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; From 31e12cb663b0392c9dda1c6edf0c4b22bf15232d Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 3 Nov 2016 21:08:12 +0300 Subject: [PATCH 137/168] arm64: dts: m3ulcb: enable WDT This supports watchdog timer for M3ULCB board Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index 5567c46f3753..593d0b4ab31a 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -90,3 +90,8 @@ &scif_clk { clock-frequency = <14745600>; status = "okay"; }; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; From 5be54db85872fddf060ccec962a50b40d3b24625 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Tue, 8 Nov 2016 17:14:21 +0300 Subject: [PATCH 138/168] arm64: dts: m3ulcb: enable SDHI0 This supports SDHI0 on M3ULCB board SD card slot Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- .../arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index 593d0b4ab31a..d209e5480ff6 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -54,6 +54,30 @@ key-1 { gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; }; }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; }; &extal_clk { @@ -77,6 +101,31 @@ scif_clk_pins: scif_clk { groups = "scif_clk_a"; function = "scif_clk"; }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; }; &scif2 { From fd51baee7abc388916b3e3b58dc062ef9c534150 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Tue, 8 Nov 2016 17:14:42 +0300 Subject: [PATCH 139/168] arm64: dts: m3ulcb: enable SDHI2 This supports SDHI2 for M3ULCB onboard eMMC Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- .../arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index d209e5480ff6..c3f064ac2cb4 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -55,6 +55,24 @@ key-1 { }; }; + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; @@ -113,6 +131,18 @@ sdhi0_pins_uhs: sd0_uhs { function = "sdhi0"; power-source = <1800>; }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; }; &sdhi0 { @@ -128,6 +158,19 @@ &sdhi0 { status = "okay"; }; +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; From 274dc8916d4b4b2f6a2636e670771c806a7e6a96 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Tue, 8 Nov 2016 17:16:19 +0300 Subject: [PATCH 140/168] arm64: dts: h3ulcb: enable SDHI2 This supports SDHI2 for H3ULCB onboard eMMC Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- .../arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index f178fe1730de..8d0ac076d8e2 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -62,6 +62,24 @@ x12_clk: x12 { clock-frequency = <24576000>; }; + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; @@ -157,6 +175,18 @@ sdhi0_pins_1v8: sd0_1v8 { power-source = <1800>; }; + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + sound_pins: sound { groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; function = "ssi"; @@ -273,6 +303,19 @@ &sdhi0 { status = "okay"; }; +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &ssi1 { shared-pin; }; From 93373c309a703b57690216db4106a4a534929c15 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Tue, 8 Nov 2016 17:16:29 +0300 Subject: [PATCH 141/168] arm64: dts: h3ulcb: rename SDHI0 pins This changes SDHI0 pin names for H3ULCB board Signed-off-by: Vladimir Barinov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index 8d0ac076d8e2..6ffb0517421a 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -163,13 +163,13 @@ avb_pins: avb { function = "avb"; }; - sdhi0_pins_3v3: sd0_3v3 { + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; power-source = <3300>; }; - sdhi0_pins_1v8: sd0_1v8 { + sdhi0_pins_uhs: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; power-source = <1800>; @@ -291,8 +291,8 @@ dai0 { }; &sdhi0 { - pinctrl-0 = <&sdhi0_pins_3v3>; - pinctrl-1 = <&sdhi0_pins_1v8>; + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi0>; From bd6777f8b4cdb53dafb12229410acf2ab85d7c28 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Nov 2016 19:37:16 +0100 Subject: [PATCH 142/168] arm64: dts: r8a7795: Add device node for PRR Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 681f54422375..a39a702b904d 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -321,6 +321,11 @@ cpg: clock-controller@e6150000 { #power-domain-cells = <0>; }; + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7795-sysc"; reg = <0 0xe6180000 0 0x0400>; From 5de68961cf5618c1ce5bb15848b36121247f23d5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Nov 2016 19:37:17 +0100 Subject: [PATCH 143/168] arm64: dts: r8a7796: Add device node for PRR Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 9599f5691099..41a050d2f192 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -243,6 +243,11 @@ cpg: clock-controller@e6150000 { #power-domain-cells = <0>; }; + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + sysc: system-controller@e6180000 { compatible = "renesas,r8a7796-sysc"; reg = <0 0xe6180000 0 0x0400>; From 39cb62cb897388d54002e6d4b7ae1b4d88330f23 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Tue, 5 Jul 2016 17:04:29 +0800 Subject: [PATCH 144/168] arm64: tegra: Add Tegra186 support This adds the initial support of Tegra186 SoC. It provides enough to enable the serial console and boot from an initial ramdisk. Signed-off-by: Joseph Lo [treding@nvidia.com: remove leading 0 from unit-addresses] [treding@nvidia.com: remove unused nvidia,bpmp property] Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 87 ++++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra186.dtsi diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi new file mode 100644 index 000000000000..ff0c9e182598 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -0,0 +1,87 @@ +#include + +/ { + compatible = "nvidia,tegra186"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + uarta: serial@3100000 { + compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x03100000 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + status = "disabled"; + }; + + gic: interrupt-controller@3881000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x03881000 0x0 0x1000>, + <0x0 0x03882000 0x0 0x2000>; + interrupts = ; + interrupt-parent = <&gic>; + }; + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x0 0x03c00000 0x0 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + status = "disabled"; + }; + + sysram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x0 0x30000000 0x0 0x50000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; + + cpu_bpmp_tx: shmem@4e000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4e000 0x0 0x1000>; + label = "cpu-bpmp-tx"; + pool; + }; + + cpu_bpmp_rx: shmem@4f000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4f000 0x0 0x1000>; + label = "cpu-bpmp-rx"; + pool; + }; + }; + + bpmp: bpmp { + compatible = "nvidia,tegra186-bpmp"; + mboxes = <&hsp_top0 0 19>; + shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + #clock-cells = <1>; + #reset-cells = <1>; + + bpmp_i2c: i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; +}; From cd6fe32e34fa5cc04693a714755f61e3cc62937e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 15 Nov 2016 13:01:08 +0100 Subject: [PATCH 145/168] arm64: tegra: Add CPU nodes for Tegra186 Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that support ARMv8 and four CPUs are Cortex-A57 CPUs. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index ff0c9e182598..cbedef4fa9a8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -56,6 +56,47 @@ cpu_bpmp_rx: shmem@4f000 { }; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "nvidia,tegra186-denver", "arm,armv8"; + device_type = "cpu"; + reg = <0x000>; + }; + + cpu@1 { + compatible = "nvidia,tegra186-denver", "arm,armv8"; + device_type = "cpu"; + reg = <0x001>; + }; + + cpu@2 { + compatible = "arm,cortex-a57", "arm,armv8"; + device_type = "cpu"; + reg = <0x100>; + }; + + cpu@3 { + compatible = "arm,cortex-a57", "arm,armv8"; + device_type = "cpu"; + reg = <0x101>; + }; + + cpu@4 { + compatible = "arm,cortex-a57", "arm,armv8"; + device_type = "cpu"; + reg = <0x102>; + }; + + cpu@5 { + compatible = "arm,cortex-a57", "arm,armv8"; + device_type = "cpu"; + reg = <0x103>; + }; + }; + bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; mboxes = <&hsp_top0 0 19>; From a7a77e2e83dda6da54f6de19881390c568335cea Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Nov 2016 16:29:32 +0100 Subject: [PATCH 146/168] arm64: tegra: Add serial ports on Tegra186 The initial patch only added UARTA, but there's no reason we shouldn't be adding all of them. While at it, also specify the missing clocks and resets for UARTA. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 76 ++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index cbedef4fa9a8..f3d60cb6a36c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -11,6 +11,58 @@ uarta: serial@3100000 { reg = <0x0 0x03100000 0x0 0x40>; reg-shift = <2>; interrupts = ; + clocks = <&bpmp 55>; + clock-names = "serial"; + resets = <&bpmp 47>; + reset-names = "serial"; + status = "disabled"; + }; + + uartb: serial@3110000 { + compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x03110000 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&bpmp 56>; + clock-names = "serial"; + resets = <&bpmp 48>; + reset-names = "serial"; + status = "disabled"; + }; + + uartd: serial@3130000 { + compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x03130000 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&bpmp 77>; + clock-names = "serial"; + resets = <&bpmp 50>; + reset-names = "serial"; + status = "disabled"; + }; + + uarte: serial@3140000 { + compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x03140000 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&bpmp 194>; + clock-names = "serial"; + resets = <&bpmp 132>; + reset-names = "serial"; + status = "disabled"; + }; + + uartf: serial@3150000 { + compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x03150000 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&bpmp 195>; + clock-names = "serial"; + resets = <&bpmp 111>; + reset-names = "serial"; status = "disabled"; }; @@ -34,6 +86,30 @@ hsp_top0: hsp@3c00000 { status = "disabled"; }; + uartc: serial@c280000 { + compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x0c280000 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&bpmp 215>; + clock-names = "serial"; + resets = <&bpmp 49>; + reset-names = "serial"; + status = "disabled"; + }; + + uartg: serial@c290000 { + compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x0c290000 0x0 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&bpmp 216>; + clock-names = "serial"; + resets = <&bpmp 112>; + reset-names = "serial"; + status = "disabled"; + }; + sysram@30000000 { compatible = "nvidia,tegra186-sysram", "mmio-sram"; reg = <0x0 0x30000000 0x0 0x50000>; From 40cc83b34cb81aa40656f944563f3cc7d6466b2b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Aug 2016 16:07:15 +0200 Subject: [PATCH 147/168] arm64: tegra: Add I2C controllers on Tegra186 Tegra186 has a total of nine I2C controllers that are compatible with the I2C controllers introduced in Tegra114. Two of these controllers share pads with two DPAUX controllers (for AUX transactions). Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 120 +++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index f3d60cb6a36c..65d6b97647cf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -66,6 +66,100 @@ uartf: serial@3150000 { status = "disabled"; }; + gen1_i2c: i2c@3160000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x03160000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp 47>; + clock-names = "div-clk"; + resets = <&bpmp 19>; + reset-names = "i2c"; + status = "disabled"; + }; + + cam_i2c: i2c@3180000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x03180000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp 75>; + clock-names = "div-clk"; + resets = <&bpmp 21>; + reset-names = "i2c"; + status = "disabled"; + }; + + /* shares pads with dpaux1 */ + dp_aux_ch1_i2c: i2c@3190000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x03190000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp 86>; + clock-names = "div-clk"; + resets = <&bpmp 22>; + reset-names = "i2c"; + status = "disabled"; + }; + + /* controlled by BPMP, should not be enabled */ + pwr_i2c: i2c@31a0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x031a0000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp 48>; + clock-names = "div-clk"; + resets = <&bpmp 23>; + reset-names = "i2c"; + status = "disabled"; + }; + + /* shares pads with dpaux0 */ + dp_aux_ch0_i2c: i2c@31b0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x031b0000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp 125>; + clock-names = "div-clk"; + resets = <&bpmp 24>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen7_i2c: i2c@31c0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x031c0000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp 182>; + clock-names = "div-clk"; + resets = <&bpmp 81>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen9_i2c: i2c@31e0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x031e0000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp 183>; + clock-names = "div-clk"; + resets = <&bpmp 83>; + reset-names = "i2c"; + status = "disabled"; + }; + gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -86,6 +180,32 @@ hsp_top0: hsp@3c00000 { status = "disabled"; }; + gen2_i2c: i2c@c240000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x0c240000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp 218>; + clock-names = "div-clk"; + resets = <&bpmp 20>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen8_i2c: i2c@c250000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x0c250000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp 219>; + clock-names = "div-clk"; + resets = <&bpmp 82>; + reset-names = "i2c"; + status = "disabled"; + }; + uartc: serial@c280000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x0c280000 0x0 0x40>; From 99425dfd6b49119c1f99651e9518ebb6c6156da2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Aug 2016 16:23:19 +0200 Subject: [PATCH 148/168] arm64: tegra: Add SDHCI controllers on Tegra186 Tegra186 has a total of four SDHCI controllers that each support SD 4.2 (up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and SDHOST 4.1 (up to UHS-I speed). Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 65d6b97647cf..9577359dedc8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -160,6 +160,50 @@ gen9_i2c: i2c@31e0000 { status = "disabled"; }; + sdmmc1: sdhci@3400000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x0 0x03400000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp 52>; + clock-names = "sdhci"; + resets = <&bpmp 33>; + reset-names = "sdhci"; + status = "disabled"; + }; + + sdmmc2: sdhci@3420000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x0 0x03420000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp 53>; + clock-names = "sdhci"; + resets = <&bpmp 34>; + reset-names = "sdhci"; + status = "disabled"; + }; + + sdmmc3: sdhci@3440000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x0 0x03440000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp 76>; + clock-names = "sdhci"; + resets = <&bpmp 35>; + reset-names = "sdhci"; + status = "disabled"; + }; + + sdmmc4: sdhci@3460000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x0 0x03460000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp 54>; + clock-names = "sdhci"; + resets = <&bpmp 36>; + reset-names = "sdhci"; + status = "disabled"; + }; + gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; From fc4bb754c81ce0f6d2d5f4c5d6ae5b49165ca3c3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Aug 2016 16:31:53 +0200 Subject: [PATCH 149/168] arm64: tegra: Add GPIO controllers on Tegra186 Tegra186 has two GPIO controllers that are no longer compatible with the controller found on earlier generations. One of these controllers exists in an always-on partition of the SoC whereas the other can be clock- and powergated. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 9577359dedc8..a918e10240fd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1,3 +1,4 @@ +#include #include / { @@ -6,6 +7,23 @@ / { #address-cells = <2>; #size-cells = <2>; + gpio: gpio@2200000 { + compatible = "nvidia,tegra186-gpio"; + reg-names = "security", "gpio"; + reg = <0x0 0x2200000 0x0 0x10000>, + <0x0 0x2210000 0x0 0x10000>; + interrupts = , + , + , + , + , + ; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x40>; @@ -274,6 +292,18 @@ uartg: serial@c290000 { status = "disabled"; }; + gpio_aon: gpio@c2f0000 { + compatible = "nvidia,tegra186-gpio-aon"; + reg-names = "security", "gpio"; + reg = <0x0 0xc2f0000 0x0 0x1000>, + <0x0 0xc2f1000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + sysram@30000000 { compatible = "nvidia,tegra186-sysram", "mmio-sram"; reg = <0x0 0x30000000 0x0 0x50000>; From df205de62b805fee73c2794c088cfb1eed5d7e5e Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Tue, 5 Jul 2016 17:04:30 +0800 Subject: [PATCH 150/168] arm64: tegra: Add NVIDIA P3310 processor module support The NVIDIA P3310 is a processor module used in several reference designs that features a Tegra186 SoC, 8 GiB of LPDDR4 RAM, 32 GiB eMMC and other essentials such as ethernet, WiFi and a PMIC. It is typically connected to an I/O board (such as the P2597) that provides the connecters needed to hook it up to the outside world. Signed-off-by: Joseph Lo Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi new file mode 100644 index 000000000000..807af7b68761 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -0,0 +1,32 @@ +#include "tegra186.dtsi" + +/ { + model = "NVIDIA Tegra186 P3310 Processor Module"; + compatible = "nvidia,p3310", "nvidia,tegra186"; + + aliases { + serial0 = &uarta; + }; + + chosen { + bootargs = "earlycon console=ttyS0,115200n8"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + serial@3100000 { + status = "okay"; + }; + + hsp@3c00000 { + status = "okay"; + }; + + bpmp { + status = "okay"; + }; +}; From 0dfde1332509e4f130da646f712757bc419fa1b7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Nov 2016 17:36:56 +0100 Subject: [PATCH 151/168] arm64: tegra: Enable PSCI on P3310 The P3310 processor module comes ships with a firmware that implements PSCI 1.0. Enable and use it to bring up all CPUs. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 807af7b68761..1abe2eceb3d1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -26,7 +26,39 @@ hsp@3c00000 { status = "okay"; }; + cpus { + cpu@0 { + enable-method = "psci"; + }; + + cpu@1 { + enable-method = "psci"; + }; + + cpu@2 { + enable-method = "psci"; + }; + + cpu@3 { + enable-method = "psci"; + }; + + cpu@4 { + enable-method = "psci"; + }; + + cpu@5 { + enable-method = "psci"; + }; + }; + bpmp { status = "okay"; }; + + psci { + compatible = "arm,psci-1.0"; + status = "okay"; + method = "smc"; + }; }; From 99575bceebd60b572f0ccf9a900fdb970922ca49 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Tue, 5 Jul 2016 17:04:31 +0800 Subject: [PATCH 152/168] arm64: tegra: Add NVIDIA P2771 board support The NVIDIA P2771 is composed of a P3310 processor module that connects to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel that is connected via the P2597's display connector and has several connectors such as HDMI, USB 3.0, PCIe and ethernet. Signed-off-by: Joseph Lo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 1 + arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 8 ++++++++ 2 files changed, 9 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 0f7cdf3e05c1..18941458cb4d 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb +dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb always := $(dtb-y) clean-files := *.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts new file mode 100644 index 000000000000..0d3c0996d832 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "tegra186-p3310.dtsi" + +/ { + model = "NVIDIA Tegra186 P2771-0000 Development Board"; + compatible = "nvidia,p2771-0000", "nvidia,tegra186"; +}; From 34d05111226b5fd168e5763455639c91e45d71a8 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Mon, 21 Nov 2016 13:58:39 +0900 Subject: [PATCH 153/168] arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash Add the mshc_2 node for supporting T-Flash. Also add the "mshc*" aliases. dwmmc driver should be assigned to "ctrl_id" after parsing to "mshc". If there are no aliases for mshc, then it might be set to the wrong capabilities. Signed-off-by: Jaehoon Chung Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index ce4178126272..88cb6c109e21 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -45,6 +45,8 @@ aliases { spi2 = &spi_2; spi3 = &spi_3; spi4 = &spi_4; + mshc0 = &mshc_0; + mshc2 = &mshc_2; }; chosen { @@ -715,6 +717,23 @@ &mshc_0 { assigned-clock-rates = <800000000>; }; +&mshc_2 { + status = "okay"; + num-slots = <1>; + cap-sd-highspeed; + disable-wp; + cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>; + cd-inverted; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + fifo-depth = <0x80>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; +}; + &pinctrl_alive { pinctrl-names = "default"; pinctrl-0 = <&initial_alive>; From ebcc47ab81d85de33e1cb8d719a3f359c68415bc Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Thu, 17 Nov 2016 18:25:02 -0500 Subject: [PATCH 154/168] arm64: dts: NS2: enable sdio1 Enable sdio1 in the Northstar2 SVK device tree file Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2-svk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index c719bb5e2921..34619079a6c6 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -157,6 +157,10 @@ &sdio0 { status = "ok"; }; +&sdio1 { + status = "ok"; +}; + &nand { nandcs@0 { compatible = "brcm,nandcs"; From 7af371a70139d2e18350365d8685d4fc1cc67973 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Thu, 17 Nov 2016 18:25:03 -0500 Subject: [PATCH 155/168] arm64: dts: NS2: Add PCI PHYs PCI PHYs are missing from the Northstar2 DT entries for the 2 PCI buses. Add them so that PCI devices can be discovered. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index cb09981c132c..863503d78f57 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -133,6 +133,9 @@ pcie0: pcie@20020000 { status = "disabled"; + phys = <&pci_phy0>; + phy-names = "pcie-phy"; + msi-parent = <&msi0>; msi0: msi@20020000 { compatible = "brcm,iproc-msi"; @@ -171,6 +174,9 @@ pcie4: pcie@50020000 { status = "disabled"; + phys = <&pci_phy1>; + phy-names = "pcie-phy"; + msi-parent = <&msi4>; msi4: msi@50020000 { compatible = "brcm,iproc-msi"; From c6f049db0a783a35685104e83214c9cc02fb74b6 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Mon, 14 Nov 2016 20:17:43 +0800 Subject: [PATCH 156/168] dt-bindings: add rockchip RK1108 Evaluation board RK1108 EVB is designed by Rockchip for CVR field. Signed-off-by: Andy Yan Acked-by: Rob Herring [split off from dts patch and to prevent conflicts with px5 addition] Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index dfd605fd6848..5b960d739262 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -107,6 +107,10 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; +- Rockchip RK1108 Evaluation board + Required root node properties: + - compatible = "rockchip,rk1108-evb", "rockchip,rk1108"; + - Rockchip RK3368 evb: Required root node properties: - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; From bb51b5350d2fe38f30f8e416541f32dde195d7d8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 22 Nov 2016 11:00:45 +0100 Subject: [PATCH 157/168] ARM64: dts: Add support for Meson GXM Following the Amlogic Linux kernel, it seem the only differences between the GXL and GXM SoCs are the CPU Clusters. This commit renames the gxl-s905d-p23x DTSI in a common file for S905D p23x and S912 q20x boards. Then adds a meson-gxm dtsi and reproduce the P23x to Q20x boards dts files since the S905D and S912 SoCs shares the same pinout and the P23x and Q20x boards are identical. Signed-off-by: Neil Armstrong Tested-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- .../devicetree/bindings/arm/amlogic.txt | 6 + arch/arm64/boot/dts/amlogic/Makefile | 2 + ...905d-p23x.dtsi => meson-gx-p23x-q20x.dtsi} | 4 +- .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 3 +- .../boot/dts/amlogic/meson-gxl-s905d-p231.dts | 3 +- .../boot/dts/amlogic/meson-gxm-s912-q200.dts | 77 ++++++++++++ .../boot/dts/amlogic/meson-gxm-s912-q201.dts | 58 +++++++++ arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 114 ++++++++++++++++++ 8 files changed, 264 insertions(+), 3 deletions(-) rename arch/arm64/boot/dts/amlogic/{meson-gxl-s905d-p23x.dtsi => meson-gx-p23x-q20x.dtsi} (97%) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm.dtsi diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index fffc17992510..1144214c51bb 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -25,6 +25,10 @@ Boards with the Amlogic Meson GXL S905D SoC shall have the following properties: Required root node property: compatible: "amlogic,s905d", "amlogic,meson-gxl"; +Boards with the Amlogic Meson GXM S912 SoC shall have the following properties: + Required root node property: + compatible: "amlogic,s912", "amlogic,meson-gxm"; + Board compatible values: - "geniatech,atv1200" (Meson6) - "minix,neo-x8" (Meson8) @@ -39,3 +43,5 @@ Board compatible values: - "amlogic,p212" (Meson gxl s905x) - "amlogic,p230" (Meson gxl s905d) - "amlogic,p231" (Meson gxl s905d) + - "amlogic,q200" (Meson gxm s912) + - "amlogic,q201" (Meson gxm s912) diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 5a640504a127..7752a1647661 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi similarity index 97% rename from arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi rename to arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi index 622ffbeba336..7a078bef04cd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi @@ -41,7 +41,9 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "meson-gxl-s905d.dtsi" +/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either + * the pin-compatible S912 (GXM) or S905D (GXL) SoCs. + */ / { aliases { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts index 4d082a7fdf51..f66939cacd37 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts @@ -43,7 +43,8 @@ /dts-v1/; -#include "meson-gxl-s905d-p23x.dtsi" +#include "meson-gxl-s905d.dtsi" +#include "meson-gx-p23x-q20x.dtsi" / { compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts index 1cc8d49d85e4..95992cf1fe61 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts @@ -43,7 +43,8 @@ /dts-v1/; -#include "meson-gxl-s905d-p23x.dtsi" +#include "meson-gxl-s905d.dtsi" +#include "meson-gx-p23x-q20x.dtsi" / { compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts new file mode 100644 index 000000000000..5dbc66088355 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-gxm.dtsi" +#include "meson-gx-p23x-q20x.dtsi" + +/ { + compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm"; + model = "Amlogic Meson GXM (S912) Q200 Development Board"; +}; + +/* Q200 has exclusive choice between internal or external PHY */ +ðmac { + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; + + /* Select external PHY by default */ + phy-handle = <&external_phy>; + + /* External PHY reset is shared with internal PHY Led signals */ + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + /* External PHY is in RGMII */ + phy-mode = "rgmii"; +}; + +&external_mdio { + external_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + max-speed = <1000>; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts new file mode 100644 index 000000000000..95e11d7faab8 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-gxm.dtsi" +#include "meson-gx-p23x-q20x.dtsi" + +/ { + compatible = "amlogic,q201", "amlogic,s912", "amlogic,meson-gxm"; + model = "Amlogic Meson GXM (S912) Q201 Development Board"; +}; + +/* Q201 has only internal PHY port */ +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi new file mode 100644 index 000000000000..c1974bbbddea --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-gxl.dtsi" + +/ { + compatible = "amlogic,meson-gxm"; + + cpus { + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; +}; From dfce0738256e4cca93ad3a3069698a44c95489a6 Mon Sep 17 00:00:00 2001 From: Ritesh Harjani Date: Mon, 21 Nov 2016 12:07:14 +0530 Subject: [PATCH 158/168] ARM: dts: Add xo to sdhc clock node on qcom platforms Add xo entry to sdhc clock node on all qcom platforms. Signed-off-by: Ritesh Harjani Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 10 ++++++---- arch/arm64/boot/dts/qcom/msm8996.dtsi | 9 +++++---- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 4221b7d2c0ce..1353f0e10f47 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -521,8 +521,9 @@ sdhc_1: sdhci@07824000 { interrupts = <0 123 0>, <0 138 0>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; bus-width = <8>; non-removable; status = "disabled"; @@ -536,8 +537,9 @@ sdhc_2: sdhci@07864000 { interrupts = <0 125 0>, <0 221 0>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; bus-width = <4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index cde4114bae5a..9d1d7ad9b075 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -228,14 +228,14 @@ timer { }; clocks { - xo_board { + xo_board: xo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; clock-output-names = "xo_board"; }; - sleep_clk { + sleep_clk: sleep_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32764>; @@ -405,9 +405,10 @@ sdhc2: sdhci@74a4900 { interrupts = <0 125 0>, <0 221 0>; interrupt-names = "hc_irq", "pwr_irq"; - clock-names = "iface", "core"; + clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>; + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; bus-width = <4>; }; From 2a4c744fcb1549023478e4b9e724d268d8202158 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Wed, 23 Nov 2016 16:43:34 +0900 Subject: [PATCH 159/168] arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 TM2 can support the HS400 mode, but eMMC is working in the lowest mode. This patch adds the properties for HS400 and other modes. Signed-off-by: Jaehoon Chung Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index 88cb6c109e21..f21bdc2ff834 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -701,6 +701,9 @@ &i2s0 { &mshc_0 { status = "okay"; num-slots = <1>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; non-removable; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; From c987775aa4af1034186ba17f67c21636451dc6d4 Mon Sep 17 00:00:00 2001 From: Ritesh Harjani Date: Mon, 21 Nov 2016 12:07:22 +0530 Subject: [PATCH 160/168] arm64: dts: qcom: msm8916: Add ddr support to sdhc1 This adds mmc-ddr-1_8v support to DT for sdhc1 of msm8916. Signed-off-by: Ritesh Harjani Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 1353f0e10f47..f8ff327667c5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -524,6 +524,7 @@ sdhc_1: sdhci@07824000 { <&gcc GCC_SDCC1_AHB_CLK>, <&xo_board>; clock-names = "core", "iface", "xo"; + mmc-ddr-1_8v; bus-width = <8>; non-removable; status = "disabled"; From 47d56462fce4a4f1ac8370897982e9d22453cab9 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 6 Sep 2016 16:44:59 +0800 Subject: [PATCH 161/168] arm64: dts: berlin4ct: add missing unit name to /soc node This patch fixes the following DTC warning with W=1: "Node /soc has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang --- arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi index 85c23facb9fe..d6b800fd26d0 100644 --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi @@ -142,7 +142,7 @@ timer { ; }; - soc { + soc@f7000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From c71aa0e200204cd389c7c93921fbe2146a1ef2fd Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 6 Sep 2016 16:49:17 +0800 Subject: [PATCH 162/168] arm64: dts: berlin4ct-stb: add missing unit name to /memory node This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang --- arch/arm64/boot/dts/marvell/berlin4ct-stb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts b/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts index 348c37ecf069..d47edad13e68 100644 --- a/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts +++ b/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts @@ -54,7 +54,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - memory { + memory@1000000 { device_type = "memory"; /* the first 16MB is for firmwares' usage */ reg = <0 0x01000000 0 0x7f000000>; From 40fdc6b0d2b96cac46be51eb41042a715047b791 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 6 Sep 2016 16:51:23 +0800 Subject: [PATCH 163/168] arm64: dts: berlin4ct-dmp: add missing unit name to /memory node This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang --- arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts index 0d70d39fa8d2..fae6c6924705 100644 --- a/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts +++ b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts @@ -54,7 +54,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - memory { + memory@1000000 { device_type = "memory"; /* the first 16MB is for firmwares' usage */ reg = <0 0x01000000 0 0x7f000000>; From afafe375df51043bf236c996a7d4a1b9c3fc70ef Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Fri, 14 Oct 2016 15:09:13 +0200 Subject: [PATCH 164/168] ARM: dts: artpec: add pcie support Add PCIe support to the ARTPEC-6 SoC. This uses the existing pcie-artpec6 driver. So, all that is needed is device tree entries in the DTS. Signed-off-by: Niklas Cassel Signed-off-by: Jesper Nilsson --- arch/arm/boot/dts/artpec6-devboard.dts | 4 ++++ arch/arm/boot/dts/artpec6.dtsi | 29 +++++++++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts index f823ed382ac7..9dfe845694cf 100644 --- a/arch/arm/boot/dts/artpec6-devboard.dts +++ b/arch/arm/boot/dts/artpec6-devboard.dts @@ -46,6 +46,10 @@ &uart3 { status = "okay"; }; +&pcie { + status = "okay"; +}; + ðernet { status = "okay"; diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index 3489019cc0dc..767cbe8d8557 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -67,7 +67,7 @@ cpu1: cpu@1 { }; }; - syscon { + syscon: syscon@f8000000 { compatible = "axis,artpec6-syscon", "syscon"; reg = <0xf8000000 0x48>; }; @@ -154,6 +154,33 @@ pmu { interrupt-parent = <&intc>; }; + pcie: pcie@f8050000 { + compatible = "axis,artpec6-pcie", "snps,dw-pcie"; + reg = <0xf8050000 0x2000 + 0xf8040000 0x1000 + 0xc0000000 0x2000>; + reg-names = "dbi", "phy", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* downstream I/O */ + ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; + num-lanes = <2>; + bus-range = <0x00 0xff>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + axis,syscon-pcie = <&syscon>; + status = "disabled"; + }; + amba@0 { compatible = "simple-bus"; #address-cells = <0x1>; From f51b454549b81258c1e0bb4aec199c810a3ec5a0 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 22 Nov 2016 11:00:46 +0100 Subject: [PATCH 165/168] ARM64: dts: meson-gxm: Add support for the Nexbox A1 Add support for the Nexbox A1 board based on the Amlogic S912 SoC. Signed-off-by: Neil Armstrong [khilman: replace '_' in node-names with '-'] Acked-by: Rob Herring Signed-off-by: Kevin Hilman --- .../devicetree/bindings/arm/amlogic.txt | 1 + arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 169 ++++++++++++++++++ 3 files changed, 171 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 1144214c51bb..6ef7c52e794f 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -45,3 +45,4 @@ Board compatible values: - "amlogic,p231" (Meson gxl s905d) - "amlogic,q200" (Meson gxm s912) - "amlogic,q201" (Meson gxm s912) + - "nexbox,a1" (Meson gxm s912) diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 7752a1647661..2fbb8e39bba4 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts new file mode 100644 index 000000000000..f859d75db8bd --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-gxm.dtsi" + +/ { + compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm"; + model = "NEXBOX A1"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio-boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; + + /* Select external PHY by default */ + phy-handle = <&external_phy>; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + /* External PHY is in RGMII */ + phy-mode = "rgmii"; +}; + +&external_mdio { + external_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + max-speed = <1000>; + }; +}; From 8441add12b9e13d99d853afbaa484f3939986a14 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 22 Nov 2016 12:41:54 +0100 Subject: [PATCH 166/168] ARM64: dts: meson-gxl: Add support for Nexbox A95X The Nexbox A95X exists with a Meson GXBB (S905) Soc or a Meson GXL SoC (S905X). Add the S905X variant which uses the internal PHY instead of an external PHY. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- .../devicetree/bindings/arm/amlogic.txt | 1 + arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/meson-gxl-nexbox-a95x.dts | 205 ++++++++++++++++++ 3 files changed, 207 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-nexbox-a95x.dts diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 6ef7c52e794f..9b2b41ab6817 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -45,4 +45,5 @@ Board compatible values: - "amlogic,p231" (Meson gxl s905d) - "amlogic,q200" (Meson gxm s912) - "amlogic,q201" (Meson gxm s912) + - "nexbox,a95x" (Meson gxbb or Meson gxl s905x) - "nexbox,a1" (Meson gxm s912) diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 2fbb8e39bba4..0d7bfbf7d922 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-nexbox-a95x.dts new file mode 100644 index 000000000000..e99101ae9664 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-nexbox-a95x.dts @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2016 Andreas Färber + * Copyright (c) 2016 BayLibre, Inc. + * Author: Neil Armstrong + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-gxl-s905x.dtsi" + +/ { + compatible = "nexbox,a95x", "amlogic,s905x", "amlogic,meson-gxl"; + model = "NEXBOX A95X (S905X)"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_card: gpio-regulator { + compatible = "regulator-gpio"; + + regulator-name = "VDDIO_CARD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + + /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ + states = <1800000 0 + 3300000 1>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +ðmac { + status = "okay"; + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_card>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; From c681ca42bfb74f74ac3187ca5289df25cb67b67f Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 28 Nov 2016 10:20:04 -0800 Subject: [PATCH 167/168] ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible The SCPI driver has an updated compatible to indicate the pre-released (pre v1.0) status of the driver. Since Amlogic used a pre-1.0 version, add that compatible as well. Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index ac5ad3bf1bd6..51edd5b5c460 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -51,7 +51,7 @@ / { compatible = "amlogic,meson-gxbb"; scpi { - compatible = "amlogic,meson-gxbb-scpi"; + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; mboxes = <&mailbox 1 &mailbox 2>; shmem = <&cpu_scp_lpri &cpu_scp_hpri>; From f98121f3ef3d36f4d040b11ab38f15387f6eefa2 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 30 Nov 2016 15:08:55 +0100 Subject: [PATCH 168/168] arm64: dts: fix build errors from missing dependencies Two branches were incorrectly sent without having the necessary header file changes. Rather than back those out now, I'm replacing the symbolic names for the clks and resets with the numeric values to get 'make allmodconfig dtbs' back to work. After the header file changes are merged, we can revert this patch. Fixes: 6bc37fa ("arm64: dts: add Allwinner A64 SoC .dtsi") Fixes: 50784e6 ("dts: arm64: db820c: add pmic pins specific dts file") Acked-by: Andre Przywara Acked-by: Maxime Ripard Acked-by: Srinivas Kandagatla Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 36 +++++++++---------- .../dts/qcom/apq8096-db820c-pmic-pins.dtsi | 2 +- 2 files changed, 18 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 3d70be3a0049..e0dcab8eb035 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -42,10 +42,8 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include #include #include -#include / { interrupt-parent = <&gic>; @@ -137,7 +135,7 @@ pio: pinctrl@1c20800 { interrupts = , , ; - clocks = <&ccu CLK_BUS_PIO>; + clocks = <&ccu 58>; gpio-controller; #gpio-cells = <3>; interrupt-controller; @@ -160,8 +158,8 @@ uart0: serial@1c28000 { interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; + clocks = <&ccu 67>; + resets = <&ccu 46>; status = "disabled"; }; @@ -171,8 +169,8 @@ uart1: serial@1c28400 { interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; + clocks = <&ccu 68>; + resets = <&ccu 47>; status = "disabled"; }; @@ -182,8 +180,8 @@ uart2: serial@1c28800 { interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; + clocks = <&ccu 69>; + resets = <&ccu 48>; status = "disabled"; }; @@ -193,8 +191,8 @@ uart3: serial@1c28c00 { interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; + clocks = <&ccu 70>; + resets = <&ccu 49>; status = "disabled"; }; @@ -204,8 +202,8 @@ uart4: serial@1c29000 { interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; + clocks = <&ccu 71>; + resets = <&ccu 50>; status = "disabled"; }; @@ -213,8 +211,8 @@ i2c0: i2c@1c2ac00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; + clocks = <&ccu 63>; + resets = <&ccu 42>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -224,8 +222,8 @@ i2c1: i2c@1c2b000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; + clocks = <&ccu 64>; + resets = <&ccu 43>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -235,8 +233,8 @@ i2c2: i2c@1c2b400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; + clocks = <&ccu 65>; + resets = <&ccu 44>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi index 0938191c012f..0de95171d6d0 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi @@ -9,7 +9,7 @@ ls_exp_gpio_f: pm8916_mpp4 { pinconf { pins = "gpio5"; output-low; - power-source = ; // 1.8V + power-source = <2>; // PM8994_GPIO_S4, 1.8V }; }; };