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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86
Allowing CONFIG_DRM_AMD_DC_DCN1_0 to be disabled on X86 was an opportunity for display with Raven Ridge accidentally not working. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
1ce0688f3f
commit
4841203102
26 changed files with 56 additions and 64 deletions
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@ -2200,7 +2200,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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case CHIP_VEGA20:
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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case CHIP_RAVEN:
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#endif
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return amdgpu_dc != 0;
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@ -9,14 +9,6 @@ config DRM_AMD_DC
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support for AMDGPU. This adds required support for Vega and
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Raven ASICs.
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config DRM_AMD_DC_DCN1_0
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bool "DCN 1.0 Raven family"
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depends on DRM_AMD_DC && X86
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default y
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help
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Choose this option if you want to have
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RV family for display engine
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config DEBUG_KERNEL_DC
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bool "Enable kgdb break in DC"
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depends on DRM_AMD_DC
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@ -60,7 +60,7 @@
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#include "modules/inc/mod_freesync.h"
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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#include "ivsrcid/irqsrcs_dcn_1_0.h"
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#include "dcn/dcn_1_0_offset.h"
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@ -1192,7 +1192,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
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return 0;
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}
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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/* Register IRQ sources and initialize IRQ callbacks */
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static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
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{
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@ -1526,7 +1526,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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goto fail;
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}
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break;
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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case CHIP_RAVEN:
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if (dcn10_register_irq_handlers(dm->adev)) {
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DRM_ERROR("DM: Failed to initialize IRQ\n");
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@ -1725,7 +1725,7 @@ static int dm_early_init(void *handle)
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adev->mode_info.num_dig = 6;
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adev->mode_info.plane_type = dm_plane_type_default;
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break;
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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case CHIP_RAVEN:
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adev->mode_info.num_crtc = 4;
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adev->mode_info.num_hpd = 4;
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@ -25,7 +25,7 @@
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DC_LIBS = basics bios calcs dce gpio i2caux irq virtual
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ifdef CONFIG_DRM_AMD_DC_DCN1_0
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ifdef CONFIG_X86
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DC_LIBS += dcn10 dml
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endif
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@ -55,7 +55,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
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case DCE_VERSION_11_22:
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*h = dal_cmd_tbl_helper_dce112_get_table2();
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return true;
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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case DCN_VERSION_1_0:
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*h = dal_cmd_tbl_helper_dce112_get_table2();
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return true;
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@ -38,7 +38,7 @@ CFLAGS_dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare
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BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
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ifdef CONFIG_DRM_AMD_DC_DCN1_0
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ifdef CONFIG_X86
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BW_CALCS += dcn_calcs.o dcn_calc_math.o dcn_calc_auto.o
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endif
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@ -476,7 +476,7 @@ static void destruct(struct dc *dc)
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kfree(dc->bw_dceip);
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dc->bw_dceip = NULL;
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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#ifdef CONFIG_X86
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kfree(dc->dcn_soc);
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dc->dcn_soc = NULL;
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@ -492,7 +492,7 @@ static bool construct(struct dc *dc,
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struct dc_context *dc_ctx;
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struct bw_calcs_dceip *dc_dceip;
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struct bw_calcs_vbios *dc_vbios;
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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#ifdef CONFIG_X86
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struct dcn_soc_bounding_box *dcn_soc;
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struct dcn_ip_params *dcn_ip;
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#endif
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@ -514,7 +514,7 @@ static bool construct(struct dc *dc,
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}
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dc->bw_vbios = dc_vbios;
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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#ifdef CONFIG_X86
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dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
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if (!dcn_soc) {
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dm_error("%s: failed to create dcn_soc\n", __func__);
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@ -348,7 +348,7 @@ void context_clock_trace(
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struct dc *dc,
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struct dc_state *context)
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{
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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DC_LOGGER_INIT(dc->ctx->logger);
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CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
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"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
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@ -41,7 +41,7 @@
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#include "dce100/dce100_resource.h"
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#include "dce110/dce110_resource.h"
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#include "dce112/dce112_resource.h"
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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#include "dcn10/dcn10_resource.h"
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#endif
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#include "dce120/dce120_resource.h"
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@ -85,7 +85,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
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case FAMILY_AI:
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dc_version = DCE_VERSION_12_0;
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break;
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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case FAMILY_RV:
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dc_version = DCN_VERSION_1_0;
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break;
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@ -136,7 +136,7 @@ struct resource_pool *dc_create_resource_pool(
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num_virtual_links, dc);
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break;
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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case DCN_VERSION_1_0:
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res_pool = dcn10_create_resource_pool(
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num_virtual_links, dc);
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@ -1213,7 +1213,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream(
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}
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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static int acquire_first_split_pipe(
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struct resource_context *res_ctx,
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const struct resource_pool *pool,
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free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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if (!free_pipe) {
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int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
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if (pipe_idx >= 0)
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/* acquire new resources */
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pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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#ifdef CONFIG_X86
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if (pipe_idx < 0)
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pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
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#endif
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@ -289,7 +289,7 @@ struct dc {
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/* Inputs into BW and WM calculations. */
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struct bw_calcs_dceip *bw_dceip;
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struct bw_calcs_vbios *bw_vbios;
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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#ifdef CONFIG_X86
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struct dcn_soc_bounding_box *dcn_soc;
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struct dcn_ip_params *dcn_ip;
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struct display_mode_lib dml;
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@ -592,7 +592,7 @@ static uint32_t dce110_get_pix_clk_dividers(
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case DCE_VERSION_11_2:
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case DCE_VERSION_11_22:
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case DCE_VERSION_12_0:
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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case DCN_VERSION_1_0:
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#endif
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@ -909,7 +909,7 @@ static bool dce110_program_pix_clk(
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struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
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struct bp_pixel_clock_parameters bp_pc_params = {0};
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
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unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
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unsigned dp_dto_ref_kHz = 700000;
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case DCE_VERSION_11_2:
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case DCE_VERSION_11_22:
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case DCE_VERSION_12_0:
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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case DCN_VERSION_1_0:
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#endif
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@ -55,7 +55,7 @@
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CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
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CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
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SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
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@ -30,7 +30,7 @@
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#include "bios_parser_interface.h"
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#include "dc.h"
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#include "dmcu.h"
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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#include "dcn_calcs.h"
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#endif
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#include "core_types.h"
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@ -478,7 +478,7 @@ static void dce12_update_clocks(struct dccg *dccg,
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}
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}
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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#ifdef CONFIG_X86
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static int dcn1_determine_dppclk_threshold(struct dccg *dccg, struct dc_clocks *new_clocks)
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{
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bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
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}
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}
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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#ifdef CONFIG_X86
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static const struct display_clock_funcs dcn1_funcs = {
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.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
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.set_dispclk = dce112_set_clock,
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@ -821,7 +821,7 @@ struct dccg *dce120_dccg_create(struct dc_context *ctx)
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return &clk_dce->base;
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}
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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#ifdef CONFIG_X86
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struct dccg *dcn1_dccg_create(struct dc_context *ctx)
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{
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struct dc_debug *debug = &ctx->dc->debug;
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@ -111,7 +111,7 @@ struct dccg *dce112_dccg_create(
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struct dccg *dce120_dccg_create(struct dc_context *ctx);
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#ifdef CONFIG_DRM_AMD_DC_DCN1_0
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#ifdef CONFIG_X86
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struct dccg *dcn1_dccg_create(struct dc_context *ctx);
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#endif
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@ -314,7 +314,7 @@ static void dce_get_psr_wait_loop(
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return;
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}
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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static void dcn10_get_dmcu_state(struct dmcu *dmcu)
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{
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struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
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@ -735,7 +735,7 @@ static const struct dmcu_funcs dce_funcs = {
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.is_dmcu_initialized = dce_is_dmcu_initialized
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};
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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static const struct dmcu_funcs dcn10_funcs = {
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.dmcu_init = dcn10_dmcu_init,
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.load_iram = dcn10_dmcu_load_iram,
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@ -787,7 +787,7 @@ struct dmcu *dce_dmcu_create(
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return &dmcu_dce->base;
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}
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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struct dmcu *dcn10_dmcu_create(
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struct dc_context *ctx,
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const struct dce_dmcu_registers *regs,
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@ -135,7 +135,7 @@ static void dce110_update_generic_info_packet(
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AFMT_GENERIC0_UPDATE, (packet_index == 0),
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AFMT_GENERIC2_UPDATE, (packet_index == 2));
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}
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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if (REG(AFMT_VBI_PACKET_CONTROL1)) {
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switch (packet_index) {
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case 0:
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@ -229,7 +229,7 @@ static void dce110_update_hdmi_info_packet(
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HDMI_GENERIC1_SEND, send,
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HDMI_GENERIC1_LINE, line);
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break;
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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case 4:
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if (REG(HDMI_GENERIC_PACKET_CONTROL2))
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REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
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@ -274,7 +274,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
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struct dc_crtc_timing *crtc_timing,
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enum dc_color_space output_color_space)
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{
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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uint32_t h_active_start;
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uint32_t v_active_start;
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uint32_t misc0 = 0;
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@ -317,7 +317,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
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if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
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REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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if (enc110->se_mask->DP_VID_N_MUL)
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REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
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#endif
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@ -328,7 +328,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
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break;
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}
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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if (REG(DP_MSA_MISC))
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misc1 = REG_READ(DP_MSA_MISC);
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#endif
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@ -362,7 +362,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
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/* set dynamic range and YCbCr range */
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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switch (crtc_timing->display_color_depth) {
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case COLOR_DEPTH_666:
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colorimetry_bpc = 0;
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@ -441,7 +441,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
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DP_DYN_RANGE, dynamic_range_rgb,
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DP_YCBCR_RANGE, dynamic_range_ycbcr);
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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if (REG(DP_MSA_COLORIMETRY))
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REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
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@ -476,7 +476,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
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crtc_timing->v_front_porch;
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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/* start at begining of left border */
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if (REG(DP_MSA_TIMING_PARAM2))
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REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
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@ -751,7 +751,7 @@ static void dce110_stream_encoder_update_hdmi_info_packets(
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dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
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}
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#ifdef CONFIG_X86
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if (enc110->se_mask->HDMI_DB_DISABLE) {
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/* for bring up, disable dp double TODO */
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if (REG(HDMI_DB_CONTROL))
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@ -789,7 +789,7 @@ static void dce110_stream_encoder_stop_hdmi_info_packets(
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HDMI_GENERIC1_LINE, 0,
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HDMI_GENERIC1_SEND, 0);
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#ifdef CONFIG_X86
|
||||
/* stop generic packets 2 & 3 on HDMI */
|
||||
if (REG(HDMI_GENERIC_PACKET_CONTROL2))
|
||||
REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
|
||||
|
|
|
@ -1250,7 +1250,7 @@ static void program_scaler(const struct dc *dc,
|
|||
{
|
||||
struct tg_color color = {0};
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#ifdef CONFIG_X86
|
||||
/* TOFPGA */
|
||||
if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
|
||||
return;
|
||||
|
|
|
@ -61,7 +61,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120)
|
|||
###############################################################################
|
||||
# DCN 1x
|
||||
###############################################################################
|
||||
ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
ifdef CONFIG_X86
|
||||
GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o
|
||||
|
||||
AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10))
|
||||
|
|
|
@ -43,7 +43,7 @@
|
|||
#include "dce80/hw_factory_dce80.h"
|
||||
#include "dce110/hw_factory_dce110.h"
|
||||
#include "dce120/hw_factory_dce120.h"
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#ifdef CONFIG_X86
|
||||
#include "dcn10/hw_factory_dcn10.h"
|
||||
#endif
|
||||
|
||||
|
@ -81,7 +81,7 @@ bool dal_hw_factory_init(
|
|||
case DCE_VERSION_12_0:
|
||||
dal_hw_factory_dce120_init(factory);
|
||||
return true;
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#ifdef CONFIG_X86
|
||||
case DCN_VERSION_1_0:
|
||||
dal_hw_factory_dcn10_init(factory);
|
||||
return true;
|
||||
|
|
|
@ -43,7 +43,7 @@
|
|||
#include "dce80/hw_translate_dce80.h"
|
||||
#include "dce110/hw_translate_dce110.h"
|
||||
#include "dce120/hw_translate_dce120.h"
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#ifdef CONFIG_X86
|
||||
#include "dcn10/hw_translate_dcn10.h"
|
||||
#endif
|
||||
|
||||
|
@ -78,7 +78,7 @@ bool dal_hw_translate_init(
|
|||
case DCE_VERSION_12_0:
|
||||
dal_hw_translate_dce120_init(translate);
|
||||
return true;
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#ifdef CONFIG_X86
|
||||
case DCN_VERSION_1_0:
|
||||
dal_hw_translate_dcn10_init(translate);
|
||||
return true;
|
||||
|
|
|
@ -71,7 +71,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112)
|
|||
###############################################################################
|
||||
# DCN 1.0 family
|
||||
###############################################################################
|
||||
ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
ifdef CONFIG_X86
|
||||
I2CAUX_DCN1 = i2caux_dcn10.o
|
||||
|
||||
AMD_DAL_I2CAUX_DCN1 = $(addprefix $(AMDDALPATH)/dc/i2caux/dcn10/,$(I2CAUX_DCN1))
|
||||
|
|
|
@ -59,7 +59,7 @@
|
|||
|
||||
#include "dce120/i2caux_dce120.h"
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#ifdef CONFIG_X86
|
||||
#include "dcn10/i2caux_dcn10.h"
|
||||
#endif
|
||||
|
||||
|
@ -91,7 +91,7 @@ struct i2caux *dal_i2caux_create(
|
|||
return dal_i2caux_dce100_create(ctx);
|
||||
case DCE_VERSION_12_0:
|
||||
return dal_i2caux_dce120_create(ctx);
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#ifdef CONFIG_X86
|
||||
case DCN_VERSION_1_0:
|
||||
return dal_i2caux_dcn10_create(ctx);
|
||||
#endif
|
||||
|
|
|
@ -33,7 +33,7 @@
|
|||
#include "dc_bios_types.h"
|
||||
#include "mem_input.h"
|
||||
#include "hubp.h"
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#ifdef CONFIG_X86
|
||||
#include "mpc.h"
|
||||
#endif
|
||||
|
||||
|
@ -221,7 +221,7 @@ struct pipe_ctx {
|
|||
struct pipe_ctx *top_pipe;
|
||||
struct pipe_ctx *bottom_pipe;
|
||||
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
#ifdef CONFIG_X86
|
||||
struct _vcs_dpi_display_dlg_regs_st dlg_regs;
|
||||
struct _vcs_dpi_display_ttu_regs_st ttu_regs;
|
||||
struct _vcs_dpi_display_rq_regs_st rq_regs;
|
||||
|
@ -276,7 +276,7 @@ struct dc_state {
|
|||
|
||||
/* Note: these are big structures, do *not* put on stack! */
|
||||
struct dm_pp_display_configuration pp_display_cfg;
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
#ifdef CONFIG_X86
|
||||
struct dcn_bw_internal_vars dcn_bw_vars;
|
||||
#endif
|
||||
|
||||
|
|
|
@ -60,7 +60,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12)
|
|||
###############################################################################
|
||||
# DCN 1x
|
||||
###############################################################################
|
||||
ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
ifdef CONFIG_X86
|
||||
IRQ_DCN1 = irq_service_dcn10.o
|
||||
|
||||
AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1))
|
||||
|
|
|
@ -36,7 +36,7 @@
|
|||
#include "dce120/irq_service_dce120.h"
|
||||
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#ifdef CONFIG_X86
|
||||
#include "dcn10/irq_service_dcn10.h"
|
||||
#endif
|
||||
|
||||
|
|
|
@ -48,7 +48,7 @@
|
|||
|
||||
#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#ifdef CONFIG_X86
|
||||
#include <asm/fpu/api.h>
|
||||
#endif
|
||||
|
||||
|
|
Loading…
Reference in a new issue