From 48a1319164d9339ad50a25085cad6b879fef9fbe Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 7 Aug 2022 16:12:17 +0100 Subject: [PATCH] staging: iio: meter: ade7854: Fix alignment for DMA safety ____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Signed-off-by: Jonathan Cameron Reviewed-by: Andy Shevchenko Cc: Rodrigo Siqueira Link: https://lore.kernel.org/r/20220807151218.656881-4-jic23@kernel.org --- drivers/staging/iio/meter/ade7854.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/iio/meter/ade7854.h b/drivers/staging/iio/meter/ade7854.h index a51e6e3183d3..7a49f8f1016f 100644 --- a/drivers/staging/iio/meter/ade7854.h +++ b/drivers/staging/iio/meter/ade7854.h @@ -162,7 +162,7 @@ struct ade7854_state { int bits); int irq; struct mutex buf_lock; - u8 tx[ADE7854_MAX_TX] ____cacheline_aligned; + u8 tx[ADE7854_MAX_TX] __aligned(IIO_DMA_MINALIGN); u8 rx[ADE7854_MAX_RX]; };