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x86/mce: Define amd_mce_usable_address()
Currently, all valid MCA_ADDR values are assumed to be usable on AMD systems. However, this is not correct in most cases. Notifiers expecting usable addresses may then operate on inappropriate values. Define a helper function to do AMD-specific checks for a usable memory address. List out all known cases. [ bp: Tone down the capitalized words. ] Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20230613141142.36801-3-yazen.ghannam@amd.com
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@ -746,6 +746,44 @@ bool amd_mce_is_memory_error(struct mce *m)
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return legacy_mce_is_memory_error(m);
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}
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/*
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* AMD systems do not have an explicit indicator that the value in MCA_ADDR is
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* a system physical address. Therefore, individual cases need to be detected.
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* Future cases and checks will be added as needed.
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*
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* 1) General case
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* a) Assume address is not usable.
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* 2) Poison errors
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* a) Indicated by MCA_STATUS[43]: poison. Defined for all banks except legacy
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* northbridge (bank 4).
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* b) Refers to poison consumption in the core. Does not include "no action",
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* "action optional", or "deferred" error severities.
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* c) Will include a usable address so that immediate action can be taken.
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* 3) Northbridge DRAM ECC errors
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* a) Reported in legacy bank 4 with extended error code (XEC) 8.
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* b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore,
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* this bit should not be checked.
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*
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* NOTE: SMCA UMC memory errors fall into case #1.
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*/
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bool amd_mce_usable_address(struct mce *m)
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{
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/* Check special northbridge case 3) first. */
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if (!mce_flags.smca) {
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if (legacy_mce_is_memory_error(m))
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return true;
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else if (m->bank == 4)
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return false;
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}
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/* Check poison bit for all other bank types. */
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if (m->status & MCI_STATUS_POISON)
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return true;
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/* Assume address is not usable for all others. */
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return false;
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}
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static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
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{
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struct mce m;
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@ -464,6 +464,9 @@ int mce_usable_address(struct mce *m)
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if (!(m->status & MCI_STATUS_ADDRV))
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return 0;
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if (m->cpuvendor == X86_VENDOR_AMD)
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return amd_mce_usable_address(m);
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/* Checks after this one are Intel/Zhaoxin-specific: */
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
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boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
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@ -210,6 +210,7 @@ extern bool filter_mce(struct mce *m);
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#ifdef CONFIG_X86_MCE_AMD
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extern bool amd_filter_mce(struct mce *m);
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bool amd_mce_usable_address(struct mce *m);
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/*
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* If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits
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@ -237,6 +238,7 @@ static __always_inline void smca_extract_err_addr(struct mce *m)
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#else
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static inline bool amd_filter_mce(struct mce *m) { return false; }
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static inline bool amd_mce_usable_address(struct mce *m) { return false; }
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static inline void smca_extract_err_addr(struct mce *m) { }
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#endif
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