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crypto: cavium/nitrox - added support to identify the NITROX device partname.
Get the device partname based on it's capabilities like, core frequency, number of cores and revision id. Signed-off-by: Srikanth Jampala <Jampala.Srikanth@cavium.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Srikanth Jampala
Herbert Xu
parent
dfb89ab3f0
commit
48e10548f8
5 changed files with 184 additions and 22 deletions
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@ -7,9 +7,16 @@
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/* EMU clusters */
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#define NR_CLUSTERS 4
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/* Maximum cores per cluster,
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* varies based on partname
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*/
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#define AE_CORES_PER_CLUSTER 20
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#define SE_CORES_PER_CLUSTER 16
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#define AE_MAX_CORES (AE_CORES_PER_CLUSTER * NR_CLUSTERS)
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#define SE_MAX_CORES (SE_CORES_PER_CLUSTER * NR_CLUSTERS)
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#define ZIP_MAX_CORES 5
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/* BIST registers */
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#define EMU_BIST_STATUSX(_i) (0x1402700 + ((_i) * 0x40000))
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#define UCD_BIST_STATUS 0x12C0070
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@ -111,6 +118,9 @@
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#define LBC_ELM_VF65_128_INT 0x120C000
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#define LBC_ELM_VF65_128_INT_ENA_W1S 0x120F000
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#define RST_BOOT 0x10C1600
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#define FUS_DAT1 0x10C1408
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/* PEM registers */
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#define PEM0_INT 0x1080428
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@ -1082,4 +1092,105 @@ union lbc_inval_status {
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} s;
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};
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/**
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* struct rst_boot: RST Boot Register
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* @jtcsrdis: when set, internal CSR access via JTAG TAP controller
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* is disabled
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* @jt_tst_mode: JTAG test mode
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* @io_supply: I/O power supply setting based on IO_VDD_SELECT pin:
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* 0x1 = 1.8V
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* 0x2 = 2.5V
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* 0x4 = 3.3V
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* All other values are reserved
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* @pnr_mul: clock multiplier
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* @lboot: last boot cause mask, resets only with PLL_DC_OK
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* @rboot: determines whether core 0 remains in reset after
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* chip cold or warm or soft reset
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* @rboot_pin: read only access to REMOTE_BOOT pin
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*/
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union rst_boot {
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u64 value;
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struct {
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#if (defined(__BIG_ENDIAN_BITFIELD))
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u64 raz_63 : 1;
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u64 jtcsrdis : 1;
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u64 raz_59_61 : 3;
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u64 jt_tst_mode : 1;
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u64 raz_40_57 : 18;
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u64 io_supply : 3;
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u64 raz_30_36 : 7;
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u64 pnr_mul : 6;
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u64 raz_12_23 : 12;
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u64 lboot : 10;
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u64 rboot : 1;
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u64 rboot_pin : 1;
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#else
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u64 rboot_pin : 1;
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u64 rboot : 1;
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u64 lboot : 10;
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u64 raz_12_23 : 12;
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u64 pnr_mul : 6;
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u64 raz_30_36 : 7;
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u64 io_supply : 3;
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u64 raz_40_57 : 18;
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u64 jt_tst_mode : 1;
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u64 raz_59_61 : 3;
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u64 jtcsrdis : 1;
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u64 raz_63 : 1;
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#endif
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};
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};
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/**
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* struct fus_dat1: Fuse Data 1 Register
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* @pll_mul: main clock PLL multiplier hardware limit
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* @pll_half_dis: main clock PLL control
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* @efus_lck: efuse lockdown
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* @zip_info: ZIP information
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* @bar2_sz_conf: when zero, BAR2 size conforms to
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* PCIe specification
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* @efus_ign: efuse ignore
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* @nozip: ZIP disable
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* @pll_alt_matrix: select alternate PLL matrix
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* @pll_bwadj_denom: select CLKF denominator for
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* BWADJ value
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* @chip_id: chip ID
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*/
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union fus_dat1 {
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u64 value;
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struct {
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#if (defined(__BIG_ENDIAN_BITFIELD))
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u64 raz_57_63 : 7;
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u64 pll_mul : 3;
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u64 pll_half_dis : 1;
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u64 raz_43_52 : 10;
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u64 efus_lck : 3;
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u64 raz_26_39 : 14;
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u64 zip_info : 5;
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u64 bar2_sz_conf : 1;
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u64 efus_ign : 1;
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u64 nozip : 1;
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u64 raz_11_17 : 7;
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u64 pll_alt_matrix : 1;
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u64 pll_bwadj_denom : 2;
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u64 chip_id : 8;
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#else
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u64 chip_id : 8;
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u64 pll_bwadj_denom : 2;
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u64 pll_alt_matrix : 1;
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u64 raz_11_17 : 7;
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u64 nozip : 1;
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u64 efus_ign : 1;
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u64 bar2_sz_conf : 1;
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u64 zip_info : 5;
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u64 raz_26_39 : 14;
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u64 efus_lck : 3;
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u64 raz_43_52 : 10;
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u64 pll_half_dis : 1;
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u64 pll_mul : 3;
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u64 raz_57_63 : 7;
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#endif
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};
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};
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#endif /* __NITROX_CSR_H */
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@ -5,6 +5,7 @@
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/if.h>
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#define VERSION_LEN 32
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@ -48,15 +49,27 @@ struct nitrox_cmdq {
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dma_addr_t dma;
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};
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/**
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* struct nitrox_hw - NITROX hardware information
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* @partname: partname ex: CNN55xxx-xxx
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* @fw_name: firmware version
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* @freq: NITROX frequency
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* @vendor_id: vendor ID
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* @device_id: device ID
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* @revision_id: revision ID
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* @se_cores: number of symmetric cores
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* @ae_cores: number of asymmetric cores
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* @zip_cores: number of zip cores
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*/
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struct nitrox_hw {
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/* firmware version */
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char partname[IFNAMSIZ * 2];
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char fw_name[VERSION_LEN];
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int freq;
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u16 vendor_id;
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u16 device_id;
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u8 revision_id;
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/* CNN55XX cores */
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u8 se_cores;
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u8 ae_cores;
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u8 zip_cores;
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@ -4,6 +4,8 @@
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#include "nitrox_dev.h"
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#include "nitrox_csr.h"
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#define PLL_REF_CLK 50
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/**
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* emu_enable_cores - Enable EMU cluster cores.
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* @ndev: N5 device
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@ -410,3 +412,58 @@ void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode)
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nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value);
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}
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void nitrox_get_hwinfo(struct nitrox_device *ndev)
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{
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union emu_fuse_map emu_fuse;
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union rst_boot rst_boot;
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union fus_dat1 fus_dat1;
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unsigned char name[IFNAMSIZ * 2] = {};
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int i, dead_cores;
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u64 offset;
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/* get core frequency */
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offset = RST_BOOT;
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rst_boot.value = nitrox_read_csr(ndev, offset);
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ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK;
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for (i = 0; i < NR_CLUSTERS; i++) {
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offset = EMU_FUSE_MAPX(i);
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emu_fuse.value = nitrox_read_csr(ndev, offset);
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if (emu_fuse.s.valid) {
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dead_cores = hweight32(emu_fuse.s.ae_fuse);
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ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores;
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dead_cores = hweight16(emu_fuse.s.se_fuse);
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ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores;
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}
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}
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/* find zip hardware availability */
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offset = FUS_DAT1;
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fus_dat1.value = nitrox_read_csr(ndev, offset);
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if (!fus_dat1.nozip) {
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dead_cores = hweight8(fus_dat1.zip_info);
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ndev->hw.zip_cores = ZIP_MAX_CORES - dead_cores;
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}
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/* determine the partname CNN55<cores>-<freq><pincount>-<rev>*/
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if (ndev->hw.ae_cores == AE_MAX_CORES) {
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switch (ndev->hw.se_cores) {
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case SE_MAX_CORES:
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i = snprintf(name, sizeof(name), "CNN5560");
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break;
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case 40:
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i = snprintf(name, sizeof(name), "CNN5560s");
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break;
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}
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} else if (ndev->hw.ae_cores == (AE_MAX_CORES / 2)) {
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i = snprintf(name, sizeof(name), "CNN5530");
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} else {
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i = snprintf(name, sizeof(name), "CNN5560i");
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}
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snprintf(name + i, sizeof(name) - i, "-%3dBG676-1.%u",
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ndev->hw.freq, ndev->hw.revision_id);
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/* copy partname */
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strncpy(ndev->hw.partname, name, sizeof(ndev->hw.partname));
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}
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@ -18,5 +18,6 @@ void invalidate_lbc(struct nitrox_device *ndev);
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void enable_pkt_input_ring(struct nitrox_device *ndev, int ring);
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void enable_pkt_solicit_port(struct nitrox_device *ndev, int port);
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void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode);
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void nitrox_get_hwinfo(struct nitrox_device *ndev);
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#endif /* __NITROX_HAL_H */
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@ -291,26 +291,6 @@ static int nitrox_bist_check(struct nitrox_device *ndev)
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return 0;
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}
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static void nitrox_get_hwinfo(struct nitrox_device *ndev)
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{
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union emu_fuse_map emu_fuse;
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u64 offset;
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int i;
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for (i = 0; i < NR_CLUSTERS; i++) {
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u8 dead_cores;
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offset = EMU_FUSE_MAPX(i);
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emu_fuse.value = nitrox_read_csr(ndev, offset);
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if (emu_fuse.s.valid) {
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dead_cores = hweight32(emu_fuse.s.ae_fuse);
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ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores;
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dead_cores = hweight16(emu_fuse.s.se_fuse);
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ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores;
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}
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}
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}
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static int nitrox_pf_hw_init(struct nitrox_device *ndev)
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{
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int err;
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