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drm/amd/display: Disable idle optimization when PSR is enabled
[Why] Idle optimization and PSR conflict each other. If both enabled at the same time, display flickering will be observed. [How] Disable idle optimization when PSR is enabled. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 10 additions and 13 deletions
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@ -690,26 +690,23 @@ void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
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bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
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{
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unsigned int surface_size;
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if (!dc->ctx->dmub_srv)
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return false;
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if (enable) {
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if (dc->current_state
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&& dc->current_state->stream_count == 1 // single display only
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&& dc->current_state->stream_status[0].plane_count == 1 // single surface only
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&& dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM
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// Only 8 and 16 bit formats
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&& dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
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&& dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) {
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surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *
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dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height *
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(dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
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if (dc->current_state) {
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int i;
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/* First, check no-memory-requests case */
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for (i = 0; i < dc->current_state->stream_count; i++) {
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if (dc->current_state->stream_status[i]
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.plane_count)
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/* Fail eligibility on a visible stream */
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break;
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}
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}
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/* No applicable optimizations */
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return false;
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}
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