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spi: cadence: Add usleep_range() for cdns_spi_fill_tx_fifo()

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In case of xspi work in busy condition, may send bytes failed.
once something wrong, spi controller did't work any more

My test found this situation appear in both of read/write process.
so when TX FIFO is full, add one byte delay before send data;

Signed-off-by: sxauwsk <sxauwsk@163.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
sxauwsk 2018-04-17 04:01:27 +08:00 committed by Mark Brown
parent 10b4640833
commit 49530e6411
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1 changed files with 8 additions and 0 deletions
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8
drivers/spi/spi-cadence.c
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@ -313,6 +313,14 @@ static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) && while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
(xspi->tx_bytes > 0)) { (xspi->tx_bytes > 0)) {
/* When xspi in busy condition, bytes may send failed,
* then spi control did't work thoroughly, add one byte delay
*/
if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
CDNS_SPI_IXR_TXFULL)
usleep_range(10, 20);
if (xspi->txbuf) if (xspi->txbuf)
cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++); cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
else else