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drm: Add some HDCP related #defines
In preparation for implementing HDCP in i915, add some HDCP related register offsets and defines. The dpcd register offsets will go in drm_dp_helper.h whereas the ddc offsets along with generic HDCP stuff will get stuffed in drm_hdcp.h, which is new. Changes in v2: - drm_hdcp.h gets MIT license (Daniel) Changes in v3: - None Changes in v4: - None Changes in v5: - None Changes in v6: - SPDX license Cc: Daniel Vetter <daniel.vetter@intel.com> Reviewed-by: Ramalingam C <ramalingm.c@intel.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180108195545.218615-5-seanpaul@chromium.org
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#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
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#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
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#define DP_AUX_HDCP_BKSV 0x68000
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#define DP_AUX_HDCP_RI_PRIME 0x68005
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#define DP_AUX_HDCP_AKSV 0x68007
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#define DP_AUX_HDCP_AN 0x6800C
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#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
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#define DP_AUX_HDCP_BCAPS 0x68028
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# define DP_BCAPS_REPEATER_PRESENT BIT(1)
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# define DP_BCAPS_HDCP_CAPABLE BIT(0)
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#define DP_AUX_HDCP_BSTATUS 0x68029
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# define DP_BSTATUS_REAUTH_REQ BIT(3)
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# define DP_BSTATUS_LINK_FAILURE BIT(2)
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# define DP_BSTATUS_R0_PRIME_READY BIT(1)
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# define DP_BSTATUS_READY BIT(0)
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#define DP_AUX_HDCP_BINFO 0x6802A
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#define DP_AUX_HDCP_KSV_FIFO 0x6802C
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#define DP_AUX_HDCP_AINFO 0x6803B
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/* DP 1.2 Sideband message defines */
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/* peer device type - DP 1.2a Table 2-92 */
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#define DP_PEER_DEVICE_NONE 0x0
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39
include/drm/drm_hdcp.h
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39
include/drm/drm_hdcp.h
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (C) 2017 Google, Inc.
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*
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* Authors:
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* Sean Paul <seanpaul@chromium.org>
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*/
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#ifndef _DRM_HDCP_H_INCLUDED_
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#define _DRM_HDCP_H_INCLUDED_
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/* Period of hdcp checks (to ensure we're still authenticated) */
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#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16)
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/* Shared lengths/masks between HDMI/DVI/DisplayPort */
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#define DRM_HDCP_AN_LEN 8
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#define DRM_HDCP_BSTATUS_LEN 2
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#define DRM_HDCP_KSV_LEN 5
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#define DRM_HDCP_RI_LEN 2
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#define DRM_HDCP_V_PRIME_PART_LEN 4
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#define DRM_HDCP_V_PRIME_NUM_PARTS 5
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#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x3f)
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/* Slave address for the HDCP registers in the receiver */
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#define DRM_HDCP_DDC_ADDR 0x3A
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/* HDCP register offsets for HDMI/DVI devices */
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#define DRM_HDCP_DDC_BKSV 0x00
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#define DRM_HDCP_DDC_RI_PRIME 0x08
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#define DRM_HDCP_DDC_AKSV 0x10
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#define DRM_HDCP_DDC_AN 0x18
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#define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4)
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#define DRM_HDCP_DDC_BCAPS 0x40
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#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6)
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#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5)
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#define DRM_HDCP_DDC_BSTATUS 0x41
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#define DRM_HDCP_DDC_KSV_FIFO 0x43
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#endif
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