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OMAP: DSS2: FEATURES: DSI PLL parameter cleanup
The DSI PLL parameters (regm, regn, regm_dispc, regm_dsi, fint) have different fields and also different Max values on OMAP3 and OMAP4. Use dss features to calculate the register fields and min/max values based on current OMAP revision. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
parent
31ef82377f
commit
4964111639
3 changed files with 113 additions and 50 deletions
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@ -185,14 +185,6 @@ struct dsi_reg { u16 idx; };
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#define DSI_DT_RX_SHORT_READ_1 0x21
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#define DSI_DT_RX_SHORT_READ_2 0x22
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#define FINT_MAX 2100000
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#define FINT_MIN 750000
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#define REGN_MAX (1 << 7)
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#define REGM_MAX ((1 << 11) - 1)
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#define REGM_DISPC_MAX (1 << 4)
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#define REGM_DSI_MAX (1 << 4)
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#define LP_DIV_MAX ((1 << 13) - 1)
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enum fifo_size {
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DSI_FIFO_SIZE_0 = 0,
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DSI_FIFO_SIZE_32 = 1,
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@ -277,6 +269,11 @@ static struct
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spinlock_t irq_stats_lock;
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struct dsi_irq_stats irq_stats;
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#endif
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/* DSI PLL Parameter Ranges */
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unsigned long regm_max, regn_max;
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unsigned long regm_dispc_max, regm_dsi_max;
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unsigned long fint_min, fint_max;
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unsigned long lpdiv_max;
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} dsi;
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#ifdef DEBUG
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@ -751,7 +748,7 @@ static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
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lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
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if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
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if (lp_clk_div == 0 || lp_clk_div > dsi.lpdiv_max)
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return -EINVAL;
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dsi_fclk = dsi_fclk_rate();
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@ -801,16 +798,16 @@ static int dsi_pll_power(enum dsi_pll_power_state state)
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static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
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struct dsi_clock_info *cinfo)
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{
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if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
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if (cinfo->regn == 0 || cinfo->regn > dsi.regn_max)
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return -EINVAL;
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if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
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if (cinfo->regm == 0 || cinfo->regm > dsi.regm_max)
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return -EINVAL;
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if (cinfo->regm_dispc > REGM_DISPC_MAX)
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if (cinfo->regm_dispc > dsi.regm_dispc_max)
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return -EINVAL;
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if (cinfo->regm_dsi > REGM_DSI_MAX)
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if (cinfo->regm_dsi > dsi.regm_dsi_max)
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return -EINVAL;
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if (cinfo->use_sys_clk) {
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@ -829,7 +826,7 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
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cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
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if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
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if (cinfo->fint > dsi.fint_max || cinfo->fint < dsi.fint_min)
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return -EINVAL;
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cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
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@ -899,17 +896,17 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
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/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
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/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
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/* To reduce PLL lock time, keep Fint high (around 2 MHz) */
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for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
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for (cur.regn = 1; cur.regn < dsi.regn_max; ++cur.regn) {
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if (cur.highfreq == 0)
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cur.fint = cur.clkin / cur.regn;
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else
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cur.fint = cur.clkin / (2 * cur.regn);
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if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
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if (cur.fint > dsi.fint_max || cur.fint < dsi.fint_min)
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continue;
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/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
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for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
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for (cur.regm = 1; cur.regm < dsi.regm_max; ++cur.regm) {
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unsigned long a, b;
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a = 2 * cur.regm * (cur.clkin/1000);
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@ -921,7 +918,7 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
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/* dsi_pll_hsdiv_dispc_clk(MHz) =
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* DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
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for (cur.regm_dispc = 1; cur.regm_dispc < REGM_DISPC_MAX;
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for (cur.regm_dispc = 1; cur.regm_dispc < dsi.regm_dispc_max;
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++cur.regm_dispc) {
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struct dispc_clock_info cur_dispc;
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cur.dsi_pll_hsdiv_dispc_clk =
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@ -994,6 +991,8 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
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int r = 0;
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u32 l;
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int f;
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u8 regn_start, regn_end, regm_start, regm_end;
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u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
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DSSDBGF();
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@ -1038,19 +1037,30 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
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dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
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cinfo->dsi_pll_hsdiv_dsi_clk);
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dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
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dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
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dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start,
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®m_dispc_end);
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dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
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®m_dsi_end);
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REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
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l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
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l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
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l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
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l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
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/* DSI_PLL_REGN */
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l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
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/* DSI_PLL_REGM */
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l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
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/* DSI_CLOCK_DIV */
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l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
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22, 19); /* DSI_CLOCK_DIV */
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regm_dispc_start, regm_dispc_end);
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/* DSIPROTO_CLOCK_DIV */
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l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
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26, 23); /* DSIPROTO_CLOCK_DIV */
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regm_dsi_start, regm_dsi_end);
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dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
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BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
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BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max);
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if (cinfo->fint < 1000000)
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f = 0x3;
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else if (cinfo->fint < 1250000)
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@ -3333,6 +3343,17 @@ void dsi_wait_pll_hsdiv_dsi_active(void)
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dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
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}
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static void dsi_calc_clock_param_ranges(void)
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{
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dsi.regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
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dsi.regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
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dsi.regm_dispc_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
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dsi.regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
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dsi.fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
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dsi.fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
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dsi.lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
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}
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static int dsi_init(struct platform_device *pdev)
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{
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u32 rev;
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@ -3397,6 +3418,8 @@ static int dsi_init(struct platform_device *pdev)
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dsi.vc[i].vc_id = 0;
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}
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dsi_calc_clock_param_ranges();
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enable_clocks(1);
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rev = dsi_read_reg(DSI_REVISION);
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@ -55,36 +55,48 @@ struct omap_dss_features {
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static struct omap_dss_features *omap_current_dss_features;
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static const struct dss_reg_field omap2_dss_reg_fields[] = {
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[FEAT_REG_FIRHINC] = { 11, 0 },
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[FEAT_REG_FIRVINC] = { 27, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
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[FEAT_REG_FIFOSIZE] = { 8, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
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[FEAT_REG_VERTICALACCU] = { 25, 16 },
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[FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
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[FEAT_REG_FIRHINC] = { 11, 0 },
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[FEAT_REG_FIRVINC] = { 27, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
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[FEAT_REG_FIFOSIZE] = { 8, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
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[FEAT_REG_VERTICALACCU] = { 25, 16 },
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[FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
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[FEAT_REG_DSIPLL_REGN] = { 0, 0 },
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[FEAT_REG_DSIPLL_REGM] = { 0, 0 },
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[FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 },
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[FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 },
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};
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static const struct dss_reg_field omap3_dss_reg_fields[] = {
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[FEAT_REG_FIRHINC] = { 12, 0 },
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[FEAT_REG_FIRVINC] = { 28, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
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[FEAT_REG_FIFOSIZE] = { 10, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
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[FEAT_REG_VERTICALACCU] = { 25, 16 },
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[FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
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[FEAT_REG_FIRHINC] = { 12, 0 },
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[FEAT_REG_FIRVINC] = { 28, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
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[FEAT_REG_FIFOSIZE] = { 10, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
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[FEAT_REG_VERTICALACCU] = { 25, 16 },
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[FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
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[FEAT_REG_DSIPLL_REGN] = { 7, 1 },
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[FEAT_REG_DSIPLL_REGM] = { 18, 8 },
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[FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 },
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[FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 },
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};
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static const struct dss_reg_field omap4_dss_reg_fields[] = {
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[FEAT_REG_FIRHINC] = { 12, 0 },
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[FEAT_REG_FIRVINC] = { 28, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
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[FEAT_REG_FIFOSIZE] = { 15, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 10, 0 },
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[FEAT_REG_VERTICALACCU] = { 26, 16 },
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[FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
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[FEAT_REG_FIRHINC] = { 12, 0 },
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[FEAT_REG_FIRVINC] = { 28, 16 },
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[FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
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[FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
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[FEAT_REG_FIFOSIZE] = { 15, 0 },
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[FEAT_REG_HORIZONTALACCU] = { 10, 0 },
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[FEAT_REG_VERTICALACCU] = { 26, 16 },
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[FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
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[FEAT_REG_DSIPLL_REGN] = { 8, 1 },
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[FEAT_REG_DSIPLL_REGM] = { 20, 9 },
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[FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
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[FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
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};
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static const enum omap_display_type omap2_dss_supported_displays[] = {
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};
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static const struct dss_param_range omap2_dss_param_range[] = {
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[FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
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[FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
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[FEAT_PARAM_DSIPLL_REGN] = { 0, 0 },
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[FEAT_PARAM_DSIPLL_REGM] = { 0, 0 },
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[FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, 0 },
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[FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, 0 },
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[FEAT_PARAM_DSIPLL_FINT] = { 0, 0 },
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[FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 },
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};
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static const struct dss_param_range omap3_dss_param_range[] = {
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[FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
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[FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
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[FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 },
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[FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 },
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[FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 4) - 1 },
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[FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 4) - 1 },
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[FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 },
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[FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
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};
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static const struct dss_param_range omap4_dss_param_range[] = {
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[FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
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[FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
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[FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
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[FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
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[FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
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[FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
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[FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
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[FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
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};
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/* OMAP2 DSS Features */
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@ -52,10 +52,20 @@ enum dss_feat_reg_field {
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FEAT_REG_HORIZONTALACCU,
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FEAT_REG_VERTICALACCU,
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FEAT_REG_DISPC_CLK_SWITCH,
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FEAT_REG_DSIPLL_REGN,
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FEAT_REG_DSIPLL_REGM,
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FEAT_REG_DSIPLL_REGM_DISPC,
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FEAT_REG_DSIPLL_REGM_DSI,
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};
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enum dss_range_param {
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FEAT_PARAM_DSS_FCK,
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FEAT_PARAM_DSIPLL_REGN,
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FEAT_PARAM_DSIPLL_REGM,
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FEAT_PARAM_DSIPLL_REGM_DISPC,
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FEAT_PARAM_DSIPLL_REGM_DSI,
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FEAT_PARAM_DSIPLL_FINT,
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FEAT_PARAM_DSIPLL_LPDIV,
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};
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/* DSS Feature Functions */
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