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drm/amd/amdgpu: Add offset variant to SOC15 macros
Allows reading/writing via SOC15 macros with offset for various register banks. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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@ -63,6 +63,13 @@ struct nbio_pcie_index_data {
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(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
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(ip##_BASE__INST##inst##_SEG4 + reg))))))
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#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
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RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
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(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
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(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
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(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
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(ip##_BASE__INST##inst##_SEG4 + reg))))) + offset)
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#define WREG32_SOC15(ip, inst, reg, value) \
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WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
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(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
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@ -70,6 +77,13 @@ struct nbio_pcie_index_data {
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(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
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(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
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#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
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WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
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(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
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(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
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(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
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(ip##_BASE__INST##inst##_SEG4 + reg))))) + offset, value)
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#endif
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