mlx5: Implement SyncE support using DPLL infrastructure
Implement SyncE support using newly introduced DPLL support. Make sure that each PFs/VFs/SFs probed with appropriate capability will spawn a dpll auxiliary device and register appropriate dpll device and pin instances. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Signed-off-by: Vadim Fedorenko <vadim.fedorenko@linux.dev> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jiri Pirko
David S. Miller
parent
09eeb3aecc
commit
496fd0a26b
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@ -189,3 +189,11 @@ config MLX5_SF_MANAGER
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port is managed through devlink. A subfunction supports RDMA, netdevice
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and vdpa device. It is similar to a SRIOV VF but it doesn't require
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SRIOV support.
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config MLX5_DPLL
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tristate "Mellanox 5th generation network adapters (ConnectX series) DPLL support"
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depends on NETDEVICES && ETHERNET && PCI && MLX5_CORE
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select DPLL
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help
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DPLL support in Mellanox Technologies ConnectX NICs.
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@ -128,3 +128,6 @@ mlx5_core-$(CONFIG_MLX5_SF) += sf/vhca_event.o sf/dev/dev.o sf/dev/driver.o irq_
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# SF manager
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#
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mlx5_core-$(CONFIG_MLX5_SF_MANAGER) += sf/cmd.o sf/hw_table.o sf/devlink.o
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obj-$(CONFIG_MLX5_DPLL) += mlx5_dpll.o
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mlx5_dpll-y := dpll.o
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@ -206,6 +206,19 @@ static bool is_ib_enabled(struct mlx5_core_dev *dev)
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return err ? false : val.vbool;
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}
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static bool is_dpll_supported(struct mlx5_core_dev *dev)
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{
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if (!IS_ENABLED(CONFIG_MLX5_DPLL))
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return false;
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if (!MLX5_CAP_MCAM_REG2(dev, synce_registers)) {
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mlx5_core_warn(dev, "Missing SyncE capability\n");
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return false;
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}
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return true;
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}
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enum {
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MLX5_INTERFACE_PROTOCOL_ETH,
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MLX5_INTERFACE_PROTOCOL_ETH_REP,
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@ -215,6 +228,8 @@ enum {
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MLX5_INTERFACE_PROTOCOL_MPIB,
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MLX5_INTERFACE_PROTOCOL_VNET,
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MLX5_INTERFACE_PROTOCOL_DPLL,
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};
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static const struct mlx5_adev_device {
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@ -237,6 +252,8 @@ static const struct mlx5_adev_device {
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.is_supported = &is_ib_rep_supported },
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[MLX5_INTERFACE_PROTOCOL_MPIB] = { .suffix = "multiport",
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.is_supported = &is_mp_supported },
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[MLX5_INTERFACE_PROTOCOL_DPLL] = { .suffix = "dpll",
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.is_supported = &is_dpll_supported },
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};
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int mlx5_adev_idx_alloc(void)
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@ -0,0 +1,432 @@
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// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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/* Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
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#include <linux/dpll.h>
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#include <linux/mlx5/driver.h>
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/* This structure represents a reference to DPLL, one is created
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* per mdev instance.
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*/
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struct mlx5_dpll {
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struct dpll_device *dpll;
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struct dpll_pin *dpll_pin;
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struct mlx5_core_dev *mdev;
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struct workqueue_struct *wq;
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struct delayed_work work;
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struct {
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bool valid;
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enum dpll_lock_status lock_status;
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enum dpll_pin_state pin_state;
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} last;
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struct notifier_block mdev_nb;
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struct net_device *tracking_netdev;
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};
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static int mlx5_dpll_clock_id_get(struct mlx5_core_dev *mdev, u64 *clock_id)
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{
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u32 out[MLX5_ST_SZ_DW(msecq_reg)] = {};
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u32 in[MLX5_ST_SZ_DW(msecq_reg)] = {};
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int err;
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err = mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out),
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MLX5_REG_MSECQ, 0, 0);
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if (err)
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return err;
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*clock_id = MLX5_GET64(msecq_reg, out, local_clock_identity);
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return 0;
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}
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static int
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mlx5_dpll_synce_status_get(struct mlx5_core_dev *mdev,
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enum mlx5_msees_admin_status *admin_status,
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enum mlx5_msees_oper_status *oper_status,
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bool *ho_acq)
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{
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u32 out[MLX5_ST_SZ_DW(msees_reg)] = {};
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u32 in[MLX5_ST_SZ_DW(msees_reg)] = {};
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int err;
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err = mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out),
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MLX5_REG_MSEES, 0, 0);
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if (err)
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return err;
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if (admin_status)
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*admin_status = MLX5_GET(msees_reg, out, admin_status);
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*oper_status = MLX5_GET(msees_reg, out, oper_status);
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if (ho_acq)
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*ho_acq = MLX5_GET(msees_reg, out, ho_acq);
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return 0;
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}
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static int
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mlx5_dpll_synce_status_set(struct mlx5_core_dev *mdev,
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enum mlx5_msees_admin_status admin_status)
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{
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u32 out[MLX5_ST_SZ_DW(msees_reg)] = {};
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u32 in[MLX5_ST_SZ_DW(msees_reg)] = {};
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MLX5_SET(msees_reg, in, field_select,
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MLX5_MSEES_FIELD_SELECT_ENABLE |
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MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS);
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MLX5_SET(msees_reg, in, admin_status, admin_status);
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return mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out),
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MLX5_REG_MSEES, 0, 1);
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}
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static enum dpll_lock_status
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mlx5_dpll_lock_status_get(enum mlx5_msees_oper_status oper_status, bool ho_acq)
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{
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switch (oper_status) {
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case MLX5_MSEES_OPER_STATUS_SELF_TRACK:
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fallthrough;
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case MLX5_MSEES_OPER_STATUS_OTHER_TRACK:
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return ho_acq ? DPLL_LOCK_STATUS_LOCKED_HO_ACQ :
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DPLL_LOCK_STATUS_LOCKED;
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case MLX5_MSEES_OPER_STATUS_HOLDOVER:
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fallthrough;
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case MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER:
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return DPLL_LOCK_STATUS_HOLDOVER;
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default:
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return DPLL_LOCK_STATUS_UNLOCKED;
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}
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}
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static enum dpll_pin_state
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mlx5_dpll_pin_state_get(enum mlx5_msees_admin_status admin_status,
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enum mlx5_msees_oper_status oper_status)
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{
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return (admin_status == MLX5_MSEES_ADMIN_STATUS_TRACK &&
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(oper_status == MLX5_MSEES_OPER_STATUS_SELF_TRACK ||
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oper_status == MLX5_MSEES_OPER_STATUS_OTHER_TRACK)) ?
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DPLL_PIN_STATE_CONNECTED : DPLL_PIN_STATE_DISCONNECTED;
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}
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static int mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll,
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void *priv,
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enum dpll_lock_status *status,
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struct netlink_ext_ack *extack)
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{
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enum mlx5_msees_oper_status oper_status;
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struct mlx5_dpll *mdpll = priv;
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bool ho_acq;
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int err;
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err = mlx5_dpll_synce_status_get(mdpll->mdev, NULL,
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&oper_status, &ho_acq);
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if (err)
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return err;
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*status = mlx5_dpll_lock_status_get(oper_status, ho_acq);
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return 0;
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}
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static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll,
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void *priv,
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u32 *mode, struct netlink_ext_ack *extack)
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{
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*mode = DPLL_MODE_MANUAL;
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return 0;
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}
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static bool mlx5_dpll_device_mode_supported(const struct dpll_device *dpll,
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void *priv,
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enum dpll_mode mode,
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struct netlink_ext_ack *extack)
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{
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return mode == DPLL_MODE_MANUAL;
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}
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static const struct dpll_device_ops mlx5_dpll_device_ops = {
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.lock_status_get = mlx5_dpll_device_lock_status_get,
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.mode_get = mlx5_dpll_device_mode_get,
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.mode_supported = mlx5_dpll_device_mode_supported,
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};
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static int mlx5_dpll_pin_direction_get(const struct dpll_pin *pin,
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void *pin_priv,
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const struct dpll_device *dpll,
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void *dpll_priv,
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enum dpll_pin_direction *direction,
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struct netlink_ext_ack *extack)
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{
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*direction = DPLL_PIN_DIRECTION_INPUT;
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return 0;
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}
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static int mlx5_dpll_state_on_dpll_get(const struct dpll_pin *pin,
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void *pin_priv,
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const struct dpll_device *dpll,
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void *dpll_priv,
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enum dpll_pin_state *state,
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struct netlink_ext_ack *extack)
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{
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enum mlx5_msees_admin_status admin_status;
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enum mlx5_msees_oper_status oper_status;
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struct mlx5_dpll *mdpll = pin_priv;
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int err;
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err = mlx5_dpll_synce_status_get(mdpll->mdev, &admin_status,
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&oper_status, NULL);
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if (err)
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return err;
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*state = mlx5_dpll_pin_state_get(admin_status, oper_status);
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return 0;
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}
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static int mlx5_dpll_state_on_dpll_set(const struct dpll_pin *pin,
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void *pin_priv,
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const struct dpll_device *dpll,
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void *dpll_priv,
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enum dpll_pin_state state,
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struct netlink_ext_ack *extack)
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{
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struct mlx5_dpll *mdpll = pin_priv;
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return mlx5_dpll_synce_status_set(mdpll->mdev,
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state == DPLL_PIN_STATE_CONNECTED ?
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MLX5_MSEES_ADMIN_STATUS_TRACK :
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MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING);
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}
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static const struct dpll_pin_ops mlx5_dpll_pins_ops = {
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.direction_get = mlx5_dpll_pin_direction_get,
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.state_on_dpll_get = mlx5_dpll_state_on_dpll_get,
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.state_on_dpll_set = mlx5_dpll_state_on_dpll_set,
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};
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static const struct dpll_pin_properties mlx5_dpll_pin_properties = {
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.type = DPLL_PIN_TYPE_SYNCE_ETH_PORT,
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.capabilities = DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE,
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};
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#define MLX5_DPLL_PERIODIC_WORK_INTERVAL 500 /* ms */
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static void mlx5_dpll_periodic_work_queue(struct mlx5_dpll *mdpll)
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{
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queue_delayed_work(mdpll->wq, &mdpll->work,
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msecs_to_jiffies(MLX5_DPLL_PERIODIC_WORK_INTERVAL));
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}
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static void mlx5_dpll_periodic_work(struct work_struct *work)
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{
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struct mlx5_dpll *mdpll = container_of(work, struct mlx5_dpll,
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work.work);
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enum mlx5_msees_admin_status admin_status;
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enum mlx5_msees_oper_status oper_status;
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enum dpll_lock_status lock_status;
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enum dpll_pin_state pin_state;
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bool ho_acq;
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int err;
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err = mlx5_dpll_synce_status_get(mdpll->mdev, &admin_status,
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&oper_status, &ho_acq);
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if (err)
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goto err_out;
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lock_status = mlx5_dpll_lock_status_get(oper_status, ho_acq);
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pin_state = mlx5_dpll_pin_state_get(admin_status, oper_status);
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if (!mdpll->last.valid)
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goto invalid_out;
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if (mdpll->last.lock_status != lock_status)
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dpll_device_change_ntf(mdpll->dpll);
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if (mdpll->last.pin_state != pin_state)
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dpll_pin_change_ntf(mdpll->dpll_pin);
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invalid_out:
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mdpll->last.lock_status = lock_status;
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mdpll->last.pin_state = pin_state;
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mdpll->last.valid = true;
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err_out:
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mlx5_dpll_periodic_work_queue(mdpll);
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}
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static void mlx5_dpll_netdev_dpll_pin_set(struct mlx5_dpll *mdpll,
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struct net_device *netdev)
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{
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if (mdpll->tracking_netdev)
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return;
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netdev_dpll_pin_set(netdev, mdpll->dpll_pin);
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mdpll->tracking_netdev = netdev;
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}
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static void mlx5_dpll_netdev_dpll_pin_clear(struct mlx5_dpll *mdpll)
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{
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if (!mdpll->tracking_netdev)
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return;
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netdev_dpll_pin_clear(mdpll->tracking_netdev);
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mdpll->tracking_netdev = NULL;
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}
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static int mlx5_dpll_mdev_notifier_event(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct mlx5_dpll *mdpll = container_of(nb, struct mlx5_dpll, mdev_nb);
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struct net_device *netdev = data;
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switch (event) {
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case MLX5_DRIVER_EVENT_UPLINK_NETDEV:
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if (netdev)
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mlx5_dpll_netdev_dpll_pin_set(mdpll, netdev);
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else
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mlx5_dpll_netdev_dpll_pin_clear(mdpll);
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break;
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default:
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return NOTIFY_DONE;
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}
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return NOTIFY_OK;
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}
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static void mlx5_dpll_mdev_netdev_track(struct mlx5_dpll *mdpll,
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struct mlx5_core_dev *mdev)
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{
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mdpll->mdev_nb.notifier_call = mlx5_dpll_mdev_notifier_event;
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mlx5_blocking_notifier_register(mdev, &mdpll->mdev_nb);
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mlx5_core_uplink_netdev_event_replay(mdev);
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}
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static void mlx5_dpll_mdev_netdev_untrack(struct mlx5_dpll *mdpll,
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struct mlx5_core_dev *mdev)
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{
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mlx5_blocking_notifier_unregister(mdev, &mdpll->mdev_nb);
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mlx5_dpll_netdev_dpll_pin_clear(mdpll);
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}
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static int mlx5_dpll_probe(struct auxiliary_device *adev,
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const struct auxiliary_device_id *id)
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{
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struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
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struct mlx5_core_dev *mdev = edev->mdev;
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struct mlx5_dpll *mdpll;
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u64 clock_id;
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int err;
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err = mlx5_dpll_synce_status_set(mdev,
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MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING);
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if (err)
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return err;
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err = mlx5_dpll_clock_id_get(mdev, &clock_id);
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if (err)
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return err;
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mdpll = kzalloc(sizeof(*mdpll), GFP_KERNEL);
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if (!mdpll)
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return -ENOMEM;
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mdpll->mdev = mdev;
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auxiliary_set_drvdata(adev, mdpll);
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/* Multiple mdev instances might share one DPLL device. */
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mdpll->dpll = dpll_device_get(clock_id, 0, THIS_MODULE);
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if (IS_ERR(mdpll->dpll)) {
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err = PTR_ERR(mdpll->dpll);
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goto err_free_mdpll;
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}
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err = dpll_device_register(mdpll->dpll, DPLL_TYPE_EEC,
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&mlx5_dpll_device_ops, mdpll);
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if (err)
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goto err_put_dpll_device;
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/* Multiple mdev instances might share one DPLL pin. */
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mdpll->dpll_pin = dpll_pin_get(clock_id, mlx5_get_dev_index(mdev),
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THIS_MODULE, &mlx5_dpll_pin_properties);
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if (IS_ERR(mdpll->dpll_pin)) {
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err = PTR_ERR(mdpll->dpll_pin);
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goto err_unregister_dpll_device;
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}
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err = dpll_pin_register(mdpll->dpll, mdpll->dpll_pin,
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&mlx5_dpll_pins_ops, mdpll);
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if (err)
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goto err_put_dpll_pin;
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mdpll->wq = create_singlethread_workqueue("mlx5_dpll");
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if (!mdpll->wq) {
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err = -ENOMEM;
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goto err_unregister_dpll_pin;
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}
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mlx5_dpll_mdev_netdev_track(mdpll, mdev);
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INIT_DELAYED_WORK(&mdpll->work, &mlx5_dpll_periodic_work);
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mlx5_dpll_periodic_work_queue(mdpll);
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return 0;
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|
||||
err_unregister_dpll_pin:
|
||||
dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin,
|
||||
&mlx5_dpll_pins_ops, mdpll);
|
||||
err_put_dpll_pin:
|
||||
dpll_pin_put(mdpll->dpll_pin);
|
||||
err_unregister_dpll_device:
|
||||
dpll_device_unregister(mdpll->dpll, &mlx5_dpll_device_ops, mdpll);
|
||||
err_put_dpll_device:
|
||||
dpll_device_put(mdpll->dpll);
|
||||
err_free_mdpll:
|
||||
kfree(mdpll);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void mlx5_dpll_remove(struct auxiliary_device *adev)
|
||||
{
|
||||
struct mlx5_dpll *mdpll = auxiliary_get_drvdata(adev);
|
||||
struct mlx5_core_dev *mdev = mdpll->mdev;
|
||||
|
||||
cancel_delayed_work(&mdpll->work);
|
||||
mlx5_dpll_mdev_netdev_untrack(mdpll, mdev);
|
||||
destroy_workqueue(mdpll->wq);
|
||||
dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin,
|
||||
&mlx5_dpll_pins_ops, mdpll);
|
||||
dpll_pin_put(mdpll->dpll_pin);
|
||||
dpll_device_unregister(mdpll->dpll, &mlx5_dpll_device_ops, mdpll);
|
||||
dpll_device_put(mdpll->dpll);
|
||||
kfree(mdpll);
|
||||
|
||||
mlx5_dpll_synce_status_set(mdev,
|
||||
MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING);
|
||||
}
|
||||
|
||||
static int mlx5_dpll_suspend(struct auxiliary_device *adev, pm_message_t state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mlx5_dpll_resume(struct auxiliary_device *adev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct auxiliary_device_id mlx5_dpll_id_table[] = {
|
||||
{ .name = MLX5_ADEV_NAME ".dpll", },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(auxiliary, mlx5_dpll_id_table);
|
||||
|
||||
static struct auxiliary_driver mlx5_dpll_driver = {
|
||||
.name = "dpll",
|
||||
.probe = mlx5_dpll_probe,
|
||||
.remove = mlx5_dpll_remove,
|
||||
.suspend = mlx5_dpll_suspend,
|
||||
.resume = mlx5_dpll_resume,
|
||||
.id_table = mlx5_dpll_id_table,
|
||||
};
|
||||
|
||||
static int __init mlx5_dpll_init(void)
|
||||
{
|
||||
return auxiliary_driver_register(&mlx5_dpll_driver);
|
||||
}
|
||||
|
||||
static void __exit mlx5_dpll_exit(void)
|
||||
{
|
||||
auxiliary_driver_unregister(&mlx5_dpll_driver);
|
||||
}
|
||||
|
||||
module_init(mlx5_dpll_init);
|
||||
module_exit(mlx5_dpll_exit);
|
||||
|
||||
MODULE_AUTHOR("Jiri Pirko <jiri@nvidia.com>");
|
||||
MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) DPLL driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
|
@ -155,6 +155,8 @@ enum {
|
|||
MLX5_REG_MCC = 0x9062,
|
||||
MLX5_REG_MCDA = 0x9063,
|
||||
MLX5_REG_MCAM = 0x907f,
|
||||
MLX5_REG_MSECQ = 0x9155,
|
||||
MLX5_REG_MSEES = 0x9156,
|
||||
MLX5_REG_MIRC = 0x9162,
|
||||
MLX5_REG_SBCAM = 0xB01F,
|
||||
MLX5_REG_RESOURCE_DUMP = 0xC000,
|
||||
|
|
|
|||
|
|
@ -10176,7 +10176,9 @@ struct mlx5_ifc_mcam_access_reg_bits2 {
|
|||
u8 mirc[0x1];
|
||||
u8 regs_97_to_96[0x2];
|
||||
|
||||
u8 regs_95_to_64[0x20];
|
||||
u8 regs_95_to_87[0x09];
|
||||
u8 synce_registers[0x2];
|
||||
u8 regs_84_to_64[0x15];
|
||||
|
||||
u8 regs_63_to_32[0x20];
|
||||
|
||||
|
|
@ -12549,4 +12551,59 @@ struct mlx5_ifc_modify_page_track_obj_in_bits {
|
|||
struct mlx5_ifc_page_track_bits obj_context;
|
||||
};
|
||||
|
||||
struct mlx5_ifc_msecq_reg_bits {
|
||||
u8 reserved_at_0[0x20];
|
||||
|
||||
u8 reserved_at_20[0x12];
|
||||
u8 network_option[0x2];
|
||||
u8 local_ssm_code[0x4];
|
||||
u8 local_enhanced_ssm_code[0x8];
|
||||
|
||||
u8 local_clock_identity[0x40];
|
||||
|
||||
u8 reserved_at_80[0x180];
|
||||
};
|
||||
|
||||
enum {
|
||||
MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0),
|
||||
MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1),
|
||||
MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2),
|
||||
};
|
||||
|
||||
enum mlx5_msees_admin_status {
|
||||
MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0,
|
||||
MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1,
|
||||
};
|
||||
|
||||
enum mlx5_msees_oper_status {
|
||||
MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0,
|
||||
MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1,
|
||||
MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2,
|
||||
MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3,
|
||||
MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4,
|
||||
MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5,
|
||||
};
|
||||
|
||||
struct mlx5_ifc_msees_reg_bits {
|
||||
u8 reserved_at_0[0x8];
|
||||
u8 local_port[0x8];
|
||||
u8 pnat[0x2];
|
||||
u8 lp_msb[0x2];
|
||||
u8 reserved_at_14[0xc];
|
||||
|
||||
u8 field_select[0x20];
|
||||
|
||||
u8 admin_status[0x4];
|
||||
u8 oper_status[0x4];
|
||||
u8 ho_acq[0x1];
|
||||
u8 reserved_at_49[0xc];
|
||||
u8 admin_freq_measure[0x1];
|
||||
u8 oper_freq_measure[0x1];
|
||||
u8 failure_reason[0x9];
|
||||
|
||||
u8 frequency_diff[0x20];
|
||||
|
||||
u8 reserved_at_80[0x180];
|
||||
};
|
||||
|
||||
#endif /* MLX5_IFC_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue