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drm/i915: Change plane_config to store a tiling_mode
Rather than having "tiled" meaning "is it X-tiled?" convert the field to explicitely store the tiling mode. The code doesn't have to change much as 1 is conveniently I915_TILING_X. This is to accommodate future changes around tiling modes and scannout buffers. v2: Rebase on top of Ander's "Make intel_crtc->config a pointer" Reviewed-By: Tvrtko Ursulin <tvrtko.ursulin@intel.com> (v1) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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parent
38c2352716
commit
49af449b45
3 changed files with 10 additions and 11 deletions
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@ -2352,10 +2352,9 @@ static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
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if (!obj)
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return false;
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if (plane_config->tiled) {
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obj->tiling_mode = I915_TILING_X;
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obj->tiling_mode = plane_config->tiling;
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if (obj->tiling_mode == I915_TILING_X)
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obj->stride = crtc->base.primary->fb->pitches[0];
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}
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mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
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mode_cmd.width = crtc->base.primary->fb->width;
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@ -6565,7 +6564,7 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
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if (INTEL_INFO(dev)->gen >= 4)
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if (val & DISPPLANE_TILED)
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plane_config->tiled = true;
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plane_config->tiling = I915_TILING_X;
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pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
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fourcc = intel_format_to_fourcc(pixel_format);
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@ -6574,7 +6573,7 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
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drm_format_plane_cpp(fourcc, 0) * 8;
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if (INTEL_INFO(dev)->gen >= 4) {
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if (plane_config->tiled)
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if (plane_config->tiling)
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offset = I915_READ(DSPTILEOFF(plane));
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else
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offset = I915_READ(DSPLINOFF(plane));
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@ -6592,7 +6591,7 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
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crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
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aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
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plane_config->tiled);
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plane_config->tiling);
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plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
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aligned_height);
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@ -7619,7 +7618,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
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if (INTEL_INFO(dev)->gen >= 4)
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if (val & DISPPLANE_TILED)
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plane_config->tiled = true;
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plane_config->tiling = I915_TILING_X;
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pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
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fourcc = intel_format_to_fourcc(pixel_format);
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@ -7631,7 +7630,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
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if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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offset = I915_READ(DSPOFFSET(plane));
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} else {
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if (plane_config->tiled)
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if (plane_config->tiling)
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offset = I915_READ(DSPTILEOFF(plane));
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else
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offset = I915_READ(DSPLINOFF(plane));
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@ -7646,7 +7645,7 @@ static void ironlake_get_plane_config(struct intel_crtc *crtc,
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crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
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aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
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plane_config->tiled);
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plane_config->tiling);
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plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
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aligned_height);
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@ -258,7 +258,7 @@ struct intel_plane_state {
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};
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struct intel_plane_config {
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bool tiled;
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unsigned int tiling;
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int size;
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u32 base;
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};
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@ -593,7 +593,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
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}
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cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay;
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cur_size = ALIGN(cur_size, plane_config->tiled ? (IS_GEN2(dev) ? 16 : 8) : 1);
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cur_size = ALIGN(cur_size, plane_config->tiling ? (IS_GEN2(dev) ? 16 : 8) : 1);
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cur_size *= fb->base.pitches[0];
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DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
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pipe_name(intel_crtc->pipe),
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