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net/mlx5e: Fix broken disable 1PPS flow
Need to disable the MTPPS and unsubscribe from the pulse events
when user disables the 1PPS functionality.
Fixes: ee7f12205a
('net/mlx5e: Implement 1PPS support')
Signed-off-by: Eugenia Emantayev <eugenia@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
parent
fa3676885e
commit
49c5031ca6
1 changed files with 46 additions and 29 deletions
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@ -265,6 +265,8 @@ static int mlx5e_extts_configure(struct ptp_clock_info *ptp,
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struct mlx5e_priv *priv =
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container_of(tstamp, struct mlx5e_priv, tstamp);
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u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
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u32 field_select = 0;
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u8 pin_mode = 0;
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u8 pattern = 0;
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int pin = -1;
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int err = 0;
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@ -279,18 +281,21 @@ static int mlx5e_extts_configure(struct ptp_clock_info *ptp,
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pin = ptp_find_pin(tstamp->ptp, PTP_PF_EXTTS, rq->extts.index);
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if (pin < 0)
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return -EBUSY;
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pin_mode = MLX5E_PIN_MODE_IN;
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pattern = !!(rq->extts.flags & PTP_FALLING_EDGE);
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field_select = MLX5E_MTPPS_FS_PIN_MODE |
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MLX5E_MTPPS_FS_PATTERN |
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MLX5E_MTPPS_FS_ENABLE;
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} else {
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pin = rq->extts.index;
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field_select = MLX5E_MTPPS_FS_ENABLE;
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}
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if (rq->extts.flags & PTP_FALLING_EDGE)
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pattern = 1;
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MLX5_SET(mtpps_reg, in, pin, pin);
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MLX5_SET(mtpps_reg, in, pin_mode, MLX5E_PIN_MODE_IN);
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MLX5_SET(mtpps_reg, in, pin_mode, pin_mode);
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MLX5_SET(mtpps_reg, in, pattern, pattern);
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MLX5_SET(mtpps_reg, in, enable, on);
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MLX5_SET(mtpps_reg, in, field_select, MLX5E_MTPPS_FS_PIN_MODE |
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MLX5E_MTPPS_FS_PATTERN |
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MLX5E_MTPPS_FS_ENABLE);
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MLX5_SET(mtpps_reg, in, field_select, field_select);
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err = mlx5_set_mtpps(priv->mdev, in, sizeof(in));
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if (err)
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@ -313,6 +318,9 @@ static int mlx5e_perout_configure(struct ptp_clock_info *ptp,
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u64 cycles_now, cycles_delta;
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struct timespec64 ts;
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unsigned long flags;
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u32 field_select = 0;
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u8 pin_mode = 0;
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u8 pattern = 0;
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int pin = -1;
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s64 ns;
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@ -327,34 +335,43 @@ static int mlx5e_perout_configure(struct ptp_clock_info *ptp,
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rq->perout.index);
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if (pin < 0)
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return -EBUSY;
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}
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ts.tv_sec = rq->perout.period.sec;
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ts.tv_nsec = rq->perout.period.nsec;
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ns = timespec64_to_ns(&ts);
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if (on)
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pin_mode = MLX5E_PIN_MODE_OUT;
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pattern = MLX5E_OUT_PATTERN_PERIODIC;
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ts.tv_sec = rq->perout.period.sec;
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ts.tv_nsec = rq->perout.period.nsec;
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ns = timespec64_to_ns(&ts);
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if ((ns >> 1) != 500000000LL)
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return -EINVAL;
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ts.tv_sec = rq->perout.start.sec;
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ts.tv_nsec = rq->perout.start.nsec;
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ns = timespec64_to_ns(&ts);
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cycles_now = mlx5_read_internal_timer(tstamp->mdev);
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write_lock_irqsave(&tstamp->lock, flags);
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nsec_now = timecounter_cyc2time(&tstamp->clock, cycles_now);
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nsec_delta = ns - nsec_now;
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cycles_delta = div64_u64(nsec_delta << tstamp->cycles.shift,
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tstamp->cycles.mult);
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write_unlock_irqrestore(&tstamp->lock, flags);
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time_stamp = cycles_now + cycles_delta;
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ts.tv_sec = rq->perout.start.sec;
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ts.tv_nsec = rq->perout.start.nsec;
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ns = timespec64_to_ns(&ts);
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cycles_now = mlx5_read_internal_timer(tstamp->mdev);
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write_lock_irqsave(&tstamp->lock, flags);
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nsec_now = timecounter_cyc2time(&tstamp->clock, cycles_now);
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nsec_delta = ns - nsec_now;
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cycles_delta = div64_u64(nsec_delta << tstamp->cycles.shift,
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tstamp->cycles.mult);
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write_unlock_irqrestore(&tstamp->lock, flags);
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time_stamp = cycles_now + cycles_delta;
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field_select = MLX5E_MTPPS_FS_PIN_MODE |
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MLX5E_MTPPS_FS_PATTERN |
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MLX5E_MTPPS_FS_ENABLE |
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MLX5E_MTPPS_FS_TIME_STAMP;
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} else {
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pin = rq->perout.index;
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field_select = MLX5E_MTPPS_FS_ENABLE;
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}
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MLX5_SET(mtpps_reg, in, pin, pin);
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MLX5_SET(mtpps_reg, in, pin_mode, MLX5E_PIN_MODE_OUT);
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MLX5_SET(mtpps_reg, in, pattern, MLX5E_OUT_PATTERN_PERIODIC);
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MLX5_SET(mtpps_reg, in, pin_mode, pin_mode);
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MLX5_SET(mtpps_reg, in, pattern, pattern);
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MLX5_SET(mtpps_reg, in, enable, on);
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MLX5_SET64(mtpps_reg, in, time_stamp, time_stamp);
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MLX5_SET(mtpps_reg, in, field_select, MLX5E_MTPPS_FS_PIN_MODE |
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MLX5E_MTPPS_FS_PATTERN |
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MLX5E_MTPPS_FS_ENABLE |
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MLX5E_MTPPS_FS_TIME_STAMP);
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MLX5_SET(mtpps_reg, in, field_select, field_select);
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return mlx5_set_mtpps(priv->mdev, in, sizeof(in));
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}
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