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iommu/vt-d: Update register definitions to VT-d 3.0 specification
Add new register definitions added in the VT-d 3.0 specification. Also include registers that were missing previously. Cc: Lu Baolu <baolu.lu@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Ashok Raj <ashok.raj@intel.com> Cc: Gayatri Kammela <gayatri.kammela@intel.com> Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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#define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
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#define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
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#define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
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#define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
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#define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
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#define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
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#define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */
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#define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */
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#define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */
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#define DMAR_MTRR_FIX16K_80000_REG 0x128
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#define DMAR_MTRR_FIX16K_A0000_REG 0x130
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#define DMAR_MTRR_FIX4K_C0000_REG 0x138
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#define DMAR_MTRR_FIX4K_C8000_REG 0x140
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#define DMAR_MTRR_FIX4K_D0000_REG 0x148
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#define DMAR_MTRR_FIX4K_D8000_REG 0x150
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#define DMAR_MTRR_FIX4K_E0000_REG 0x158
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#define DMAR_MTRR_FIX4K_E8000_REG 0x160
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#define DMAR_MTRR_FIX4K_F0000_REG 0x168
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#define DMAR_MTRR_FIX4K_F8000_REG 0x170
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#define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */
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#define DMAR_MTRR_PHYSMASK0_REG 0x188
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#define DMAR_MTRR_PHYSBASE1_REG 0x190
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#define DMAR_MTRR_PHYSMASK1_REG 0x198
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#define DMAR_MTRR_PHYSBASE2_REG 0x1a0
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#define DMAR_MTRR_PHYSMASK2_REG 0x1a8
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#define DMAR_MTRR_PHYSBASE3_REG 0x1b0
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#define DMAR_MTRR_PHYSMASK3_REG 0x1b8
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#define DMAR_MTRR_PHYSBASE4_REG 0x1c0
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#define DMAR_MTRR_PHYSMASK4_REG 0x1c8
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#define DMAR_MTRR_PHYSBASE5_REG 0x1d0
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#define DMAR_MTRR_PHYSMASK5_REG 0x1d8
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#define DMAR_MTRR_PHYSBASE6_REG 0x1e0
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#define DMAR_MTRR_PHYSMASK6_REG 0x1e8
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#define DMAR_MTRR_PHYSBASE7_REG 0x1f0
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#define DMAR_MTRR_PHYSMASK7_REG 0x1f8
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#define DMAR_MTRR_PHYSBASE8_REG 0x200
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#define DMAR_MTRR_PHYSMASK8_REG 0x208
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#define DMAR_MTRR_PHYSBASE9_REG 0x210
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#define DMAR_MTRR_PHYSMASK9_REG 0x218
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#define DMAR_VCCAP_REG 0xe00 /* Virtual command capability register */
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#define DMAR_VCMD_REG 0xe10 /* Virtual command register */
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#define DMAR_VCRSP_REG 0xe20 /* Virtual command response register */
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#define OFFSET_STRIDE (9)
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#define OFFSET_STRIDE (9)
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