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drm/amd/display: Update NV1x SR latency values
[Why] HW team measurement requires updating values [How] Update bounding box values Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 2 additions and 2 deletions
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@ -298,8 +298,8 @@ static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
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},
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},
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.num_states = 5,
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.sr_exit_time_us = 8.6,
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.sr_enter_plus_exit_time_us = 10.9,
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.sr_exit_time_us = 11.6,
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.sr_enter_plus_exit_time_us = 13.9,
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.urgent_latency_us = 4.0,
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.urgent_latency_pixel_data_only_us = 4.0,
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.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
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