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ARM: plat-mxc: hook special idle handlers to arm_pm_idle
... and remove redundant include of <mach/system.h>. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
This commit is contained in:
parent
92311272c1
commit
4a3ea24405
3 changed files with 37 additions and 46 deletions
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@ -34,31 +34,29 @@ static void imx3_idle(void)
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{
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unsigned long reg = 0;
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if (!need_resched())
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__asm__ __volatile__(
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/* disable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"bic %0, %0, #0x00001000\n"
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"bic %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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/* invalidate I cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c5, 0\n"
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/* clear and invalidate D cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c14, 0\n"
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/* WFI */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c0, 4\n"
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"nop\n" "nop\n" "nop\n" "nop\n"
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"nop\n" "nop\n" "nop\n"
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/* enable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"orr %0, %0, #0x00001000\n"
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"orr %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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: "=r" (reg));
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local_irq_enable();
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__asm__ __volatile__(
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/* disable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"bic %0, %0, #0x00001000\n"
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"bic %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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/* invalidate I cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c5, 0\n"
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/* clear and invalidate D cache */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c14, 0\n"
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/* WFI */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c0, 4\n"
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"nop\n" "nop\n" "nop\n" "nop\n"
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"nop\n" "nop\n" "nop\n"
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/* enable I and D cache */
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"mrc p15, 0, %0, c1, c0, 0\n"
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"orr %0, %0, #0x00001000\n"
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"orr %0, %0, #0x00000004\n"
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"mcr p15, 0, %0, c1, c0, 0\n"
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: "=r" (reg));
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}
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static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
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@ -134,8 +132,8 @@ void __init imx31_init_early(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX31);
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mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
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pm_idle = imx3_idle;
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imx_ioremap = imx3_ioremap;
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arm_pm_idle = imx3_idle;
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}
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void __init mx31_init_irq(void)
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@ -197,7 +195,7 @@ void __init imx35_init_early(void)
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mxc_set_cpu_type(MXC_CPU_MX35);
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mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
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pm_idle = imx3_idle;
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arm_pm_idle = imx3_idle;
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imx_ioremap = imx3_ioremap;
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}
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@ -10,7 +10,6 @@
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#include <linux/kernel.h>
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#include <linux/suspend.h>
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#include <linux/io.h>
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#include <mach/system.h>
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#include <mach/hardware.h>
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static int mx27_suspend_enter(suspend_state_t state)
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@ -23,7 +22,7 @@ static int mx27_suspend_enter(suspend_state_t state)
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cscr &= 0xFFFFFFFC;
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__raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
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/* Executes WFI */
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arch_idle();
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cpu_do_idle();
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break;
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default:
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@ -26,23 +26,17 @@ static struct clk *gpc_dvfs_clk;
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static void imx5_idle(void)
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{
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if (!need_resched()) {
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/* gpc clock is needed for SRPG */
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if (gpc_dvfs_clk == NULL) {
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gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
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if (IS_ERR(gpc_dvfs_clk))
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goto err0;
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}
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clk_enable(gpc_dvfs_clk);
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mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
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if (tzic_enable_wake())
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goto err1;
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cpu_do_idle();
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err1:
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clk_disable(gpc_dvfs_clk);
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/* gpc clock is needed for SRPG */
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if (gpc_dvfs_clk == NULL) {
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gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
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if (IS_ERR(gpc_dvfs_clk))
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return;
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}
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err0:
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local_irq_enable();
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clk_enable(gpc_dvfs_clk);
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mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
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if (tzic_enable_wake() != 0)
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cpu_do_idle();
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clk_disable(gpc_dvfs_clk);
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}
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/*
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@ -108,7 +102,7 @@ void __init imx51_init_early(void)
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mxc_set_cpu_type(MXC_CPU_MX51);
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mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
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pm_idle = imx5_idle;
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arm_pm_idle = imx5_idle;
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}
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void __init imx53_init_early(void)
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