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spi: rockchip: Set rx_fifo interrupt waterline base on transfer item
The error here is to calculate the width as 8 bits. In fact, 16 bits should be considered. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://lore.kernel.org/r/20210621104800.19088-4-jon.lin@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
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1 changed files with 2 additions and 2 deletions
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@ -540,8 +540,8 @@ static int rockchip_spi_config(struct rockchip_spi *rs,
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* interrupt exactly when the fifo is full doesn't seem to work,
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* so we need the strict inequality here
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*/
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if (xfer->len < rs->fifo_len)
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writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
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if ((xfer->len / rs->n_bytes) < rs->fifo_len)
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writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
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else
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writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
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