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thermal: armada: Fix register offsets for AXP
As shown in its device tree, Armada XP has the control1 register at 0x184d0, not 0x182d0. Signed-off-by: Zachary Hays <zhays@lexmark.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/BN8PR10MB337990B7688320D736760BB68C580@BN8PR10MB3379.namprd10.prod.outlook.com
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@ -578,7 +578,7 @@ static const struct armada_thermal_data armadaxp_data = {
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.coef_m = 10000000ULL,
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.coef_div = 13825,
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.syscon_status_off = 0xb0,
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.syscon_control1_off = 0xd0,
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.syscon_control1_off = 0x2d0,
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};
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static const struct armada_thermal_data armada370_data = {
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