net: hns: Some registers use wrong address according to the datasheet.
According to the hip06 datasheet: 1.Six registers use wrong address: RCB_COM_SF_CFG_INTMASK_RING RCB_COM_SF_CFG_RING_STS RCB_COM_SF_CFG_RING RCB_COM_SF_CFG_INTMASK_BD RCB_COM_SF_CFG_BD_RINT_STS DSAF_INODE_VC1_IN_PKT_NUM_0_REG 2.The offset of DSAF_INODE_VC1_IN_PKT_NUM_0_REG should be 0x103C + 0x80 * all_chn_num 3.The offset to show the value of DSAF_INODE_IN_DATA_STP_DISC_0_REG is wrong, so the value of DSAF_INODE_SW_VLAN_TAG_DISC_0_REG will be overwrite These registers are only used in "ethtool -d", so that did not cause ndev to misfunction. Signed-off-by: Yonglong Liu <liuyonglong@huawei.com> Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yonglong Liu
David S. Miller
parent
308c6cafde
commit
4ad26f117b
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@ -2285,237 +2285,237 @@ void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
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DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
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p[223 + i] = dsaf_read_dev(ddev,
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DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
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p[224 + i] = dsaf_read_dev(ddev,
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p[226 + i] = dsaf_read_dev(ddev,
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DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
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}
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p[227] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
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p[229] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
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for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
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j = i * DSAF_COMM_CHN + port;
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p[228 + i] = dsaf_read_dev(ddev,
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p[230 + i] = dsaf_read_dev(ddev,
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DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
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}
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p[231] = dsaf_read_dev(ddev,
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DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 4);
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p[233] = dsaf_read_dev(ddev,
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DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 0x80);
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/* dsaf inode registers */
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for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
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j = i * DSAF_COMM_CHN + port;
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p[232 + i] = dsaf_read_dev(ddev,
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p[234 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_CFG_REG_0_REG + j * 0x80);
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p[235 + i] = dsaf_read_dev(ddev,
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p[237 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
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p[238 + i] = dsaf_read_dev(ddev,
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p[240 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
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p[241 + i] = dsaf_read_dev(ddev,
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p[243 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
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p[244 + i] = dsaf_read_dev(ddev,
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p[246 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
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p[245 + i] = dsaf_read_dev(ddev,
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p[249 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
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p[248 + i] = dsaf_read_dev(ddev,
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p[252 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
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p[251 + i] = dsaf_read_dev(ddev,
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p[255 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
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p[254 + i] = dsaf_read_dev(ddev,
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p[258 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
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p[257 + i] = dsaf_read_dev(ddev,
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p[261 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
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p[260 + i] = dsaf_read_dev(ddev,
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p[264 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_INER_ST_0_REG + j * 0x80);
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p[263 + i] = dsaf_read_dev(ddev,
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p[267 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
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p[266 + i] = dsaf_read_dev(ddev,
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p[270 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
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p[269 + i] = dsaf_read_dev(ddev,
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p[273 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
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p[272 + i] = dsaf_read_dev(ddev,
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p[276 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
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p[275 + i] = dsaf_read_dev(ddev,
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p[279 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
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p[278 + i] = dsaf_read_dev(ddev,
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p[282 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
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p[281 + i] = dsaf_read_dev(ddev,
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p[285 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
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p[284 + i] = dsaf_read_dev(ddev,
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p[288 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
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p[287 + i] = dsaf_read_dev(ddev,
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p[291 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
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p[290 + i] = dsaf_read_dev(ddev,
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p[294 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
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p[293 + i] = dsaf_read_dev(ddev,
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p[297 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
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p[296 + i] = dsaf_read_dev(ddev,
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p[300 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
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p[299 + i] = dsaf_read_dev(ddev,
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p[303 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
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p[302 + i] = dsaf_read_dev(ddev,
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p[306 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
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p[305 + i] = dsaf_read_dev(ddev,
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p[309 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
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p[308 + i] = dsaf_read_dev(ddev,
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p[312 + i] = dsaf_read_dev(ddev,
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DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
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}
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/* dsaf onode registers */
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for (i = 0; i < DSAF_XOD_NUM; i++) {
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p[311 + i] = dsaf_read_dev(ddev,
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p[315 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
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p[319 + i] = dsaf_read_dev(ddev,
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p[323 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
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p[327 + i] = dsaf_read_dev(ddev,
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p[331 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
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p[335 + i] = dsaf_read_dev(ddev,
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p[339 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
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p[343 + i] = dsaf_read_dev(ddev,
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p[347 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
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p[351 + i] = dsaf_read_dev(ddev,
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p[355 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
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}
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p[359] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
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p[360] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
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p[361] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
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p[363] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
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p[364] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
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p[365] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
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for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
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j = i * DSAF_COMM_CHN + port;
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p[362 + i] = dsaf_read_dev(ddev,
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p[366 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_GNT_L_0_REG + j * 0x90);
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p[365 + i] = dsaf_read_dev(ddev,
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p[369 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_GNT_H_0_REG + j * 0x90);
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p[368 + i] = dsaf_read_dev(ddev,
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p[372 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
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p[371 + i] = dsaf_read_dev(ddev,
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p[375 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
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p[374 + i] = dsaf_read_dev(ddev,
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p[378 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
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p[377 + i] = dsaf_read_dev(ddev,
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p[381 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
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p[380 + i] = dsaf_read_dev(ddev,
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p[384 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
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p[383 + i] = dsaf_read_dev(ddev,
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p[387 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
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p[386 + i] = dsaf_read_dev(ddev,
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p[390 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
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p[389 + i] = dsaf_read_dev(ddev,
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p[393 + i] = dsaf_read_dev(ddev,
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DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
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}
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p[392] = dsaf_read_dev(ddev,
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DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
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p[393] = dsaf_read_dev(ddev,
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DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
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p[394] = dsaf_read_dev(ddev,
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DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
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p[395] = dsaf_read_dev(ddev,
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DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
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p[396] = dsaf_read_dev(ddev,
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DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
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DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
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p[397] = dsaf_read_dev(ddev,
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DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
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DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
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p[398] = dsaf_read_dev(ddev,
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DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
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DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
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p[399] = dsaf_read_dev(ddev,
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DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
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DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
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p[400] = dsaf_read_dev(ddev,
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DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
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DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
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p[401] = dsaf_read_dev(ddev,
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DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
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DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
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p[402] = dsaf_read_dev(ddev,
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DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
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DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
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p[403] = dsaf_read_dev(ddev,
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DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
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DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
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p[404] = dsaf_read_dev(ddev,
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DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
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p[405] = dsaf_read_dev(ddev,
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DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
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p[406] = dsaf_read_dev(ddev,
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DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
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p[407] = dsaf_read_dev(ddev,
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DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
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p[408] = dsaf_read_dev(ddev,
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DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
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/* dsaf voq registers */
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for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
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j = (i * DSAF_COMM_CHN + port) * 0x90;
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p[405 + i] = dsaf_read_dev(ddev,
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p[409 + i] = dsaf_read_dev(ddev,
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DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
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p[408 + i] = dsaf_read_dev(ddev,
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p[412 + i] = dsaf_read_dev(ddev,
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DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
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p[411 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
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p[414 + i] = dsaf_read_dev(ddev,
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p[415 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
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p[418 + i] = dsaf_read_dev(ddev,
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DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
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p[417 + i] = dsaf_read_dev(ddev,
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p[421 + i] = dsaf_read_dev(ddev,
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DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
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p[420 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
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p[423 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
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p[426 + i] = dsaf_read_dev(ddev,
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p[424 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
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p[427 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
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p[430 + i] = dsaf_read_dev(ddev,
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DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
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p[429 + i] = dsaf_read_dev(ddev,
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p[433 + i] = dsaf_read_dev(ddev,
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DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
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p[432 + i] = dsaf_read_dev(ddev,
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p[436 + i] = dsaf_read_dev(ddev,
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DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
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p[435 + i] = dsaf_read_dev(ddev,
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p[439 + i] = dsaf_read_dev(ddev,
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DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
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p[438 + i] = dsaf_read_dev(ddev,
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p[442 + i] = dsaf_read_dev(ddev,
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DSAF_VOQ_BP_ALL_THRD_0_REG + j);
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}
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/* dsaf tbl registers */
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p[441] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
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p[442] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
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p[443] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
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p[444] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
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p[445] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
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p[446] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
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p[447] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
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p[448] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
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p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
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p[450] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
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p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
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p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
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p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
|
||||
p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
|
||||
p[455] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
|
||||
p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
|
||||
p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
|
||||
p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
|
||||
p[459] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
|
||||
p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
|
||||
p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
|
||||
p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
|
||||
p[463] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
|
||||
p[445] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
|
||||
p[446] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
|
||||
p[447] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
|
||||
p[448] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
|
||||
p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
|
||||
p[450] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
|
||||
p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
|
||||
p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
|
||||
p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
|
||||
p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
|
||||
p[455] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
|
||||
p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
|
||||
p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
|
||||
p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
|
||||
p[459] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
|
||||
p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
|
||||
p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
|
||||
p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
|
||||
p[463] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
|
||||
p[464] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
|
||||
p[465] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
|
||||
p[466] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
|
||||
p[467] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
|
||||
|
||||
for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
|
||||
j = i * 0x8;
|
||||
p[464 + 2 * i] = dsaf_read_dev(ddev,
|
||||
p[468 + 2 * i] = dsaf_read_dev(ddev,
|
||||
DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
|
||||
p[465 + 2 * i] = dsaf_read_dev(ddev,
|
||||
p[469 + 2 * i] = dsaf_read_dev(ddev,
|
||||
DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
|
||||
}
|
||||
|
||||
p[480] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
|
||||
p[481] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
|
||||
p[482] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
|
||||
p[483] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
|
||||
p[484] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
|
||||
p[485] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
|
||||
p[486] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
|
||||
p[487] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
|
||||
p[488] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
|
||||
p[489] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
|
||||
p[490] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
|
||||
p[491] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
|
||||
p[484] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
|
||||
p[485] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
|
||||
p[486] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
|
||||
p[487] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
|
||||
p[488] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
|
||||
p[489] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
|
||||
p[490] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
|
||||
p[491] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
|
||||
p[492] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
|
||||
p[493] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
|
||||
p[494] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
|
||||
p[495] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
|
||||
|
||||
/* dsaf other registers */
|
||||
p[492] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
|
||||
p[493] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
|
||||
p[494] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
|
||||
p[495] = dsaf_read_dev(ddev,
|
||||
p[496] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
|
||||
p[497] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
|
||||
p[498] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
|
||||
p[499] = dsaf_read_dev(ddev,
|
||||
DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
|
||||
p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
|
||||
p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
|
||||
p[500] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
|
||||
p[501] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
|
||||
|
||||
if (!is_ver1)
|
||||
p[498] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
|
||||
p[502] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
|
||||
|
||||
/* mark end of dsaf regs */
|
||||
for (i = 499; i < 504; i++)
|
||||
for (i = 503; i < 504; i++)
|
||||
p[i] = 0xdddddddd;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -176,7 +176,7 @@
|
|||
#define DSAF_INODE_IN_DATA_STP_DISC_0_REG 0x1A50
|
||||
#define DSAF_INODE_GE_FC_EN_0_REG 0x1B00
|
||||
#define DSAF_INODE_VC0_IN_PKT_NUM_0_REG 0x1B50
|
||||
#define DSAF_INODE_VC1_IN_PKT_NUM_0_REG 0x1C00
|
||||
#define DSAF_INODE_VC1_IN_PKT_NUM_0_REG 0x103C
|
||||
#define DSAF_INODE_IN_PRIO_PAUSE_BASE_REG 0x1C00
|
||||
#define DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET 0x100
|
||||
#define DSAF_INODE_IN_PRIO_PAUSE_OFFSET 0x50
|
||||
|
|
@ -404,11 +404,11 @@
|
|||
#define RCB_ECC_ERR_ADDR4_REG 0x460
|
||||
#define RCB_ECC_ERR_ADDR5_REG 0x464
|
||||
|
||||
#define RCB_COM_SF_CFG_INTMASK_RING 0x480
|
||||
#define RCB_COM_SF_CFG_RING_STS 0x484
|
||||
#define RCB_COM_SF_CFG_RING 0x488
|
||||
#define RCB_COM_SF_CFG_INTMASK_BD 0x48C
|
||||
#define RCB_COM_SF_CFG_BD_RINT_STS 0x470
|
||||
#define RCB_COM_SF_CFG_INTMASK_RING 0x470
|
||||
#define RCB_COM_SF_CFG_RING_STS 0x474
|
||||
#define RCB_COM_SF_CFG_RING 0x478
|
||||
#define RCB_COM_SF_CFG_INTMASK_BD 0x47C
|
||||
#define RCB_COM_SF_CFG_BD_RINT_STS 0x480
|
||||
#define RCB_COM_RCB_RD_BD_BUSY 0x490
|
||||
#define RCB_COM_RCB_FBD_CRT_EN 0x494
|
||||
#define RCB_COM_AXI_WR_ERR_INTMASK 0x498
|
||||
|
|
|
|||
Loading…
Reference in New Issue