mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-09-29 22:02:02 +00:00
Code Issues Releases Wiki Activity

ARM: dts: exynos: move assigned-clock* properties to i2s0 node in Odroid XU4

Browse source 
The purpose of those assigned-clock-* properties is to configure clock for
the I2S device so move them to respective node.  This silences the
dtschema warnings like:

  'clocks' is a dependency of 'assigned-clocks'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200906142146.21266-3-krzk@kernel.org
This commit is contained in:
Krzysztof Kozlowski 2020-09-06 16:21:46 +02:00
parent eaf2d2f689
commit 4afb06afd7
1 changed files with 27 additions and 33 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

60
arch/arm/boot/dts/exynos5422-odroidxu4.dts
View file

@ -35,30 +35,6 @@ sound: sound {
samsung,audio-routing = "I2S Playback", "Mixer DAI TX";
assigned-clocks = <&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MOUT_USER_MAU_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>,
<&clock_audss EXYNOS_DOUT_SRP>,
<&clock_audss EXYNOS_DOUT_AUD_BUS>,
<&clock_audss EXYNOS_DOUT_I2S>;
assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MAU_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>;
assigned-clock-rates = <0>,
<0>,
<0>,
<0>,
<0>,
<196608001>,
<(196608002 / 2)>,
<196608000>;
cpu {
sound-dai = <&i2s0 0>, <&i2s0 1>;
};
@ -69,17 +45,35 @@ codec {
};
};
&clock_audss {
assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
<&clock CLK_FOUT_EPLL>;
assigned-clock-rates = <(196608000 / 256)>,
<196608000>;
};
&i2s0 {
status = "okay";
assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
assigned-clocks = <&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MOUT_USER_MAU_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>,
<&i2s0 CLK_I2S_RCLK_SRC>,
<&clock_audss EXYNOS_DOUT_SRP>,
<&clock_audss EXYNOS_DOUT_AUD_BUS>,
<&clock_audss EXYNOS_DOUT_I2S>;
assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MAU_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_SCLK_I2S>;
assigned-clock-rates = <0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<196608001>,
<(196608002 / 2)>,
<196608000>;
};
&pwm {