mirrors
/
linux-stable
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
1
0
Fork 0
Code Issues Releases Wiki Activity

pwm: dwc: add PWM bit unset in get_state call 

If we are not in PWM mode, then the output is technically a 50%
output based on a single timer instead of the high-low based on
the two counters. Add a check for the PWM mode in dwc_pwm_get_state()
and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle.

This may only be an issue on initialisation, as the rest of the
code currently assumes we're always going to have the extended
PWM mode using two counters.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230907161242.67190-4-ben.dooks@codethink.co.uk
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Ben Dooks 2023-09-07 17:12:39 +01:00 committed by Thierry Reding
parent 81432e2e51
commit 4aff152d14
1 changed files with 19 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/pwm/pwm-dwc-core.c
View File

@ -122,24 +122,32 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
{
struct dwc_pwm *dwc = to_dwc_pwm(chip);
u64 duty, period;
u32 ctrl, ld, ld2;
pm_runtime_get_sync(chip->dev);
state->enabled = !!(dwc_pwm_readl(dwc,
DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN);
ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm));
ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
duty += 1;
duty *= dwc->clk_ns;
state->duty_cycle = duty;
state->enabled = !!(ctrl & DWC_TIM_CTRL_EN);
period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
period += 1;
period *= dwc->clk_ns;
period += duty;
state->period = period;
/*
* If we're not in PWM, technically the output is a 50-50
* based on the timer load-count only.
*/
if (ctrl & DWC_TIM_CTRL_PWM) {
duty = (ld + 1) * dwc->clk_ns;
period = (ld2 + 1) * dwc->clk_ns;
period += duty;
} else {
duty = (ld + 1) * dwc->clk_ns;
period = duty * 2;
}
state->polarity = PWM_POLARITY_INVERSED;
state->period = period;
state->duty_cycle = duty;
pm_runtime_put_sync(chip->dev);