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drm/amd/display: Populate socclk entries for dcn2.1

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[Why]
Dcn2.1 socclk entries in bandwidth params are not initialized.
They are not used now, but will be needed for dml validation.

[How]
Populate socclk bw params from dpm clock table

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Roman Li 2021-02-23 21:28:25 -05:00 committed by Alex Deucher
parent 639979887a
commit 4b256c28ad
1 changed files with 13 additions and 0 deletions
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13
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
View file

@ -797,7 +797,18 @@ static struct wm_table lpddr4_wm_table_rn = {
},
}
};
static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
{
int i;
for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
if (clock_table->SocClocks[i].Vol == voltage)
return clock_table->SocClocks[i].Freq;
}
ASSERT(0);
return 0;
}
static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
{
int i;
@ -841,6 +852,8 @@ static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params
bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table,
bw_params->clk_table.entries[i].voltage);
}
bw_params->vram_type = bios_info->memory_type;