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[ARM] S3C64XX: Add initial clock framework
Add the initial clocks definitions for the s3c6400 and s3c6410. Move the epll and ext clock from the s3c2443 support into the common code. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
parent
952b564b4d
commit
4b31d8b225
7 changed files with 279 additions and 20 deletions
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@ -93,12 +93,6 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)
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/* clock selections */
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/* CPU EXTCLK input */
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static struct clk clk_ext = {
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.name = "extclk",
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.id = -1,
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};
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static struct clk clk_erefclk = {
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.name = "erefclk",
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.id = -1,
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@ -147,12 +147,6 @@ static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk,
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/* clock selections */
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/* CPU EXTCLK input */
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static struct clk clk_ext = {
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.name = "ext",
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.id = -1,
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};
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static struct clk clk_mpllref = {
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.name = "mpllref",
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.parent = &clk_xtal,
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@ -167,14 +161,6 @@ static struct clk clk_mpll = {
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};
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#endif
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static struct clk clk_epllref;
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static struct clk clk_epll = {
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.name = "epll",
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.parent = &clk_epllref,
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.id = -1,
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};
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static struct clk clk_i2s_ext = {
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.name = "i2s-ext",
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.id = -1,
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@ -1072,6 +1058,7 @@ void __init s3c2443_init_clocks(int xtal)
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}
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clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
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clk_epll.parent = &clk_epllref;
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clk_usb_bus.parent = &clk_usb_bus_host;
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/* ensure usb bus clock is within correct rate of 48MHz */
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@ -56,6 +56,7 @@ void __init s3c6410_init_clocks(int xtal)
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{
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printk(KERN_INFO "%s: initialising clocks\n", __func__);
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s3c24xx_register_baseclocks(xtal);
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s3c64xx_register_clocks();
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}
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void __init s3c6410_init_irq(void)
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@ -239,6 +239,16 @@ struct clk clk_xtal = {
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.ctrlbit = 0,
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};
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struct clk clk_ext = {
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.name = "ext",
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.id = -1,
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};
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struct clk clk_epll = {
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.name = "epll",
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.id = -1,
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};
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struct clk clk_mpll = {
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.name = "mpll",
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.id = -1,
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@ -45,7 +45,13 @@ extern struct clk clk_h;
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extern struct clk clk_p;
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extern struct clk clk_mpll;
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extern struct clk clk_upll;
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extern struct clk clk_epll;
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extern struct clk clk_xtal;
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extern struct clk clk_ext;
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/* S3C64XX specific clocks */
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extern struct clk clk_27m;
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extern struct clk clk_48m;
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/* exports for arch/arm/mach-s3c2410
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*
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@ -61,6 +67,8 @@ extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
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extern int s3c24xx_register_baseclocks(unsigned long xtal);
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extern void s3c64xx_register_clocks(void);
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extern void s3c24xx_setup_clocks(unsigned long fclk,
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unsigned long hclk,
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unsigned long pclk);
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@ -15,6 +15,7 @@ obj- :=
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obj-y += dev-uart.o
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obj-y += cpu.o
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obj-y += irq.o
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obj-y += clock.o
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# CPU support
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258
arch/arm/plat-s3c64xx/clock.c
Normal file
258
arch/arm/plat-s3c64xx/clock.c
Normal file
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@ -0,0 +1,258 @@
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/* linux/arch/arm/plat-s3c64xx/clock.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX Base clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <plat/regs-clock.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/clock.h>
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struct clk clk_27m = {
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.name = "clk_27m",
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.id = -1,
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.rate = 27000000,
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};
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struct clk clk_48m = {
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.name = "clk_48m",
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.id = -1,
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.rate = 48000000,
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};
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static int inline s3c64xx_gate(void __iomem *reg,
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struct clk *clk,
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int enable)
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{
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unsigned int ctrlbit = clk->ctrlbit;
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u32 con;
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con = __raw_readl(reg);
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if (enable)
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con |= ctrlbit;
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else
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con &= ~ctrlbit;
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__raw_writel(con, reg);
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return 0;
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}
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static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
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{
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return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
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}
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static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
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{
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return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
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}
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static int s3c6xx_sclk_ctrl(struct clk *clk, int enable)
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{
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return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
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}
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static struct clk init_clocks_disable[] = {
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{
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.name = "nand",
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.id = -1,
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.parent = &clk_h,
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}, {
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.name = "adc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_TSADC,
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}, {
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.name = "i2c",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_IIC,
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}, {
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.name = "iis",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_IIS0,
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}, {
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.name = "iis",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_IIS1,
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}, {
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.name = "spi",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_SPI0,
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}, {
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.name = "spi",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_SPI1,
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}, {
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.name = "48m",
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.id = 0,
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.parent = &clk_48m,
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
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}, {
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.name = "48m",
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.id = 1,
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.parent = &clk_48m,
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
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}, {
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.name = "48m",
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.id = 2,
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.parent = &clk_48m,
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
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},
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};
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static struct clk init_clocks[] = {
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{
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.name = "lcd",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_LCD,
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}, {
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.name = "gpio",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_GPIO,
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}, {
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.name = "usb-host",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_UHOST,
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}, {
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.name = "hsmmc",
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.id = 0,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
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}, {
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.name = "hsmmc",
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.id = 1,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
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}, {
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.name = "hsmmc",
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.id = 2,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
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}, {
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.name = "timers",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_PWM,
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}, {
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.name = "uart",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_UART0,
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}, {
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.name = "uart",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_UART1,
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}, {
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.name = "uart",
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.id = 2,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_UART2,
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}, {
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.name = "uart",
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.id = 3,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_UART3,
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}, {
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.name = "rtc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_RTC,
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}, {
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.name = "watchdog",
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.id = -1,
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.parent = &clk_p,
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.ctrlbit = S3C_CLKCON_PCLK_WDT,
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}, {
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.name = "ac97",
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.id = -1,
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.parent = &clk_p,
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.ctrlbit = S3C_CLKCON_PCLK_AC97,
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}
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};
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static struct clk *clks[] __initdata = {
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&clk_ext,
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&clk_epll,
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&clk_27m,
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&clk_48m,
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};
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void s3c64xx_register_clocks(void)
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{
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struct clk *clkp;
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int ret;
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int ptr;
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s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
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clkp = init_clocks;
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for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
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ret = s3c24xx_register_clock(clkp);
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if (ret < 0) {
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printk(KERN_ERR "Failed to register clock %s (%d)\n",
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clkp->name, ret);
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}
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}
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clkp = init_clocks_disable;
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for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
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ret = s3c24xx_register_clock(clkp);
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if (ret < 0) {
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printk(KERN_ERR "Failed to register clock %s (%d)\n",
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clkp->name, ret);
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}
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(clkp->enable)(clkp, 0);
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}
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}
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