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drm/radeon/uvd: lower msg&fb buffer requirements on UVD3
Starting with UVD3 message and feedback buffers have their own 256MB segment, so no need to force them into VRAM any more. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
4a1132a023
commit
4b40e59212
3 changed files with 5 additions and 5 deletions
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@ -85,8 +85,9 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
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VRAM, also but everything into VRAM on AGP cards to avoid
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image corruptions */
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if (p->ring == R600_RING_TYPE_UVD_INDEX &&
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p->rdev->family < CHIP_PALM &&
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(i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
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/* TODO: is this still needed for NI+ ? */
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p->relocs[i].lobj.domain =
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RADEON_GEM_DOMAIN_VRAM;
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@ -476,8 +476,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
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return -EINVAL;
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}
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/* TODO: is this still necessary on NI+ ? */
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if ((cmd == 0 || cmd == 0x3) &&
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if (p->rdev->family < CHIP_PALM && (cmd == 0 || cmd == 0x3) &&
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(start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
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DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
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start, end);
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@ -212,8 +212,8 @@ int uvd_v1_0_start(struct radeon_device *rdev)
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/* enable VCPU clock */
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WREG32(UVD_VCPU_CNTL, 1 << 9);
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/* enable UMC */
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WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
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/* enable UMC and NC0 */
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WREG32_P(UVD_LMI_CTRL2, 1 << 13, ~((1 << 8) | (1 << 13)));
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/* boot up the VCPU */
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WREG32(UVD_SOFT_RESET, 0);
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