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powerpc/eeh: Don't use pci_dev during BAR restore
While restoring BARs for one specific PCI device, the pci_dev instance should have been released. So it's not reliable to use the pci_dev instance on restoring BARs. However, we still need some information (e.g. PCIe capability position, header type) from the pci_dev instance. So we have to store those information to EEH device in advance. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
parent
f5c57710dd
commit
4b83bd452f
4 changed files with 91 additions and 16 deletions
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@ -84,8 +84,11 @@ struct eeh_pe {
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* another tree except the currently existing tree of PCI
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* buses and PCI devices
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*/
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#define EEH_DEV_IRQ_DISABLED (1 << 0) /* Interrupt disabled */
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#define EEH_DEV_DISCONNECTED (1 << 1) /* Removing from PE */
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#define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */
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#define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */
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#define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */
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#define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
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#define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
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struct eeh_dev {
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int mode; /* EEH mode */
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@ -93,6 +96,7 @@ struct eeh_dev {
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int config_addr; /* Config address */
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int pe_config_addr; /* PE config address */
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u32 config_space[16]; /* Saved PCI config space */
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u8 pcie_cap; /* Saved PCIe capability */
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struct eeh_pe *pe; /* Associated PE */
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struct list_head list; /* Form link list in the PE */
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struct pci_controller *phb; /* Associated PHB */
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@ -578,7 +578,7 @@ void eeh_pe_state_clear(struct eeh_pe *pe, int state)
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* blocked on normal path during the stage. So we need utilize
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* eeh operations, which is always permitted.
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*/
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static void eeh_bridge_check_link(struct pci_dev *pdev,
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static void eeh_bridge_check_link(struct eeh_dev *edev,
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struct device_node *dn)
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{
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int cap;
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@ -589,16 +589,17 @@ static void eeh_bridge_check_link(struct pci_dev *pdev,
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* We only check root port and downstream ports of
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* PCIe switches
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*/
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if (!pci_is_pcie(pdev) ||
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(pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
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pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
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if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT)))
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return;
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pr_debug("%s: Check PCIe link for %s ...\n",
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__func__, pci_name(pdev));
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pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n",
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__func__, edev->phb->global_number,
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edev->config_addr >> 8,
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PCI_SLOT(edev->config_addr & 0xFF),
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PCI_FUNC(edev->config_addr & 0xFF));
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/* Check slot status */
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cap = pdev->pcie_cap;
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cap = edev->pcie_cap;
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eeh_ops->read_config(dn, cap + PCI_EXP_SLTSTA, 2, &val);
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if (!(val & PCI_EXP_SLTSTA_PDS)) {
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pr_debug(" No card in the slot (0x%04x) !\n", val);
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@ -652,8 +653,7 @@ static void eeh_bridge_check_link(struct pci_dev *pdev,
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#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
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#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
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static void eeh_restore_bridge_bars(struct pci_dev *pdev,
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struct eeh_dev *edev,
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static void eeh_restore_bridge_bars(struct eeh_dev *edev,
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struct device_node *dn)
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{
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int i;
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@ -679,7 +679,7 @@ static void eeh_restore_bridge_bars(struct pci_dev *pdev,
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eeh_ops->write_config(dn, PCI_COMMAND, 4, edev->config_space[1]);
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/* Check the PCIe link is ready */
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eeh_bridge_check_link(pdev, dn);
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eeh_bridge_check_link(edev, dn);
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}
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static void eeh_restore_device_bars(struct eeh_dev *edev,
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@ -729,12 +729,11 @@ static void eeh_restore_device_bars(struct eeh_dev *edev,
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static void *eeh_restore_one_device_bars(void *data, void *flag)
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{
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struct eeh_dev *edev = (struct eeh_dev *)data;
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struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
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struct device_node *dn = eeh_dev_to_of_node(edev);
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/* Do special restore for bridges */
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if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
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eeh_restore_bridge_bars(pdev, edev, dn);
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if (edev->mode & EEH_DEV_BRIDGE)
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eeh_restore_bridge_bars(edev, dn);
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else
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eeh_restore_device_bars(edev, dn);
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@ -124,6 +124,17 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
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/* Initialize eeh device */
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edev->class_code = dev->class;
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edev->mode = 0;
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if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
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edev->mode |= EEH_DEV_BRIDGE;
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if (pci_is_pcie(dev)) {
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edev->pcie_cap = pci_pcie_cap(dev);
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
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edev->mode |= EEH_DEV_ROOT_PORT;
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else if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)
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edev->mode |= EEH_DEV_DS_PORT;
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}
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edev->config_addr = ((dev->bus->number << 8) | dev->devfn);
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edev->pe_config_addr = phb->bdfn_to_pe(phb, dev->bus, dev->devfn & 0xff);
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@ -133,6 +133,48 @@ static int pseries_eeh_init(void)
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return 0;
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}
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static int pseries_eeh_cap_start(struct device_node *dn)
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{
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struct pci_dn *pdn = PCI_DN(dn);
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u32 status;
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if (!pdn)
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return 0;
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rtas_read_config(pdn, PCI_STATUS, 2, &status);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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return PCI_CAPABILITY_LIST;
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}
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static int pseries_eeh_find_cap(struct device_node *dn, int cap)
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{
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struct pci_dn *pdn = PCI_DN(dn);
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int pos = pseries_eeh_cap_start(dn);
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int cnt = 48; /* Maximal number of capabilities */
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u32 id;
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if (!pos)
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return 0;
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while (cnt--) {
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rtas_read_config(pdn, pos, 1, &pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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rtas_read_config(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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/**
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* pseries_eeh_of_probe - EEH probe on the given device
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* @dn: OF node
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@ -146,8 +188,10 @@ static void *pseries_eeh_of_probe(struct device_node *dn, void *flag)
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{
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struct eeh_dev *edev;
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struct eeh_pe pe;
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struct pci_dn *pdn = PCI_DN(dn);
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const u32 *class_code, *vendor_id, *device_id;
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const u32 *regs;
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u32 pcie_flags;
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int enable = 0;
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int ret;
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@ -167,9 +211,26 @@ static void *pseries_eeh_of_probe(struct device_node *dn, void *flag)
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if (dn->type && !strcmp(dn->type, "isa"))
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return NULL;
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/* Update class code and mode of eeh device */
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/*
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* Update class code and mode of eeh device. We need
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* correctly reflects that current device is root port
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* or PCIe switch downstream port.
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*/
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edev->class_code = *class_code;
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edev->pcie_cap = pseries_eeh_find_cap(dn, PCI_CAP_ID_EXP);
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edev->mode = 0;
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if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
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edev->mode |= EEH_DEV_BRIDGE;
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if (edev->pcie_cap) {
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rtas_read_config(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
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2, &pcie_flags);
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pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
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if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
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edev->mode |= EEH_DEV_ROOT_PORT;
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else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
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edev->mode |= EEH_DEV_DS_PORT;
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}
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}
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/* Retrieve the device address */
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regs = of_get_property(dn, "reg", NULL);
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