mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Devicetree changes for TI K3 platforms for v5.13 merge window:
* New SoCs: - AM642 mean for industrial control, motor control, remote IO, IoT gateway etc. * New Boards: - AM65: Siemens SIMATIC IOT2050 advanced and basic boards - AM64: EVM and SK boards * New peripherals: - AM65: watchdog - AM65,J721E: ICSSG - J7200: OSPI, GPIO * Fixes: - AM65: pcie node fixup, ospi speed updates - J721e, J7200: MMC speed updates, ospi speed updates and compatibles fixups. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE+KKGk1TrgjIXoxo03bWEnRc2JJ0FAmBrMDYACgkQ3bWEnRc2 JJ3v6BAAq6iVnQz5jGZXMP1SQcZyhRMFG5K3kEp/NHA6v4Sth4Knudd9s+aGPeHM tZvilR4pNCl+oXTohktXBcs81BOzcJAiSIEQqWMo/7OkOxvpA5dseYXzeDmlZBl1 98NwqgE2vXnxy1o9acWLHh2kWzdPr6N7zl/7hPrXKX8ohFi4MAGCZpwRvUsfj8e7 jzr5oC1WEtiB8i7YASKaLOhpMFjBlMc7++mU9P6SqTyDd7IfjI4Q5vquP0Gtakay mGd2lSwlqDdaXcemVDHfcKOToS/WoHyiwBt8nf+AByDnLtCxY/jOxNrEgvXS5Zkh Xk9uRhuYhNv/OJz3JQ92SCGUjIIjHeBc+KuUcJ9mP0WyLZlAfc+ZYmeYXaHyLAS5 QnBiFbvbJpasOA1mk2ePcYOzI3hvSTrbEO0bzoxsvAP0QENmmc8RGbT0mqi/u7RO kOa10SvNl5O0eHl7Z3t+lCyph6hUcN+0wJAdz/6z57rm2U7Vv4NJ6jIL998j8RSs dYe+fAT3lEyfKQCtj0p8mKcwAglQw8fhjhWJ8FVdpVKYkh/hKrJuMNFF9usCl8Rh S9xZieGA3LxldtEIOCEJJFKvo+XkJRozHRHo3dL+YBZVDjyJViFbrzqNZsYpOPrk 3GPF4GDjuuDfJsNoV6lHEnQ7urQ0zruSm6cCSM55HF6FdSxHhBE= =FXts -----END PGP SIGNATURE----- Merge tag 'ti-k3-dt-for-v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt Devicetree changes for TI K3 platforms for v5.13 merge window: * New SoCs: - AM642 mean for industrial control, motor control, remote IO, IoT gateway etc. * New Boards: - AM65: Siemens SIMATIC IOT2050 advanced and basic boards - AM64: EVM and SK boards * New peripherals: - AM65: watchdog - AM65,J721E: ICSSG - J7200: OSPI, GPIO * Fixes: - AM65: pcie node fixup, ospi speed updates - J721e, J7200: MMC speed updates, ospi speed updates and compatibles fixups. * tag 'ti-k3-dt-for-v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (39 commits) arm64: dts: ti: k3-am64-main: Fix ospi compatible arm64: dts: ti: k3-j7200-mcu: Fix ospi compatible arm64: dts: ti: k3-j721e-mcu: Fix ospi compatible arm64: dts: ti: k3-j7200: Add support for higher speed modes and update delay select values for MMCSD subsystems arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules arm64: dts: ti: k3-j7200: Add gpio nodes arm64: dts: ti: k3-am642-evm/sk: Add IPC sub-mailbox nodes arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes arm64: dts: ti: k3-am64-main: Add hwspinlock node arm64: dts: ti: k3-am642: reserve gpio in mcu domain for firmware usage arm64: dts: ti: k3-am64: Add GPIO DT nodes arm64: dts: ti: k3-am64-evm/sk: Add OSPI flash DT node arm64: dts: ti: k3-am64-main: Add OSPI node arm64: dts: ti: k3-am64-main: Add ADC nodes arm64: dts: ti: k3-am642-evm: Add USB support arm64: dts: ti: k3-am64-main: Add DT node for USB subsystem arm64: dts: ti: Add support for Siemens IOT2050 boards dt-bindings: arm: ti: Add bindings for Siemens IOT2050 boards dt-bindings: Add Siemens vendor prefix arm64: dts: ti: k3-am642-evm: Add support for SPI EEPROM ... Link: https://lore.kernel.org/r/20210405155336.smohb7uzkperqwuz@reflex Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
4b8cf90637
23 changed files with 3501 additions and 11 deletions
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@ -23,6 +23,8 @@ properties:
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items:
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- enum:
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- ti,am654-evm
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- siemens,iot2050-basic
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- siemens,iot2050-advanced
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- const: ti,am654
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- description: K3 J721E SoC
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@ -33,6 +35,13 @@ properties:
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items:
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- const: ti,j7200
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- description: K3 AM642 SoC
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items:
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- enum:
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- ti,am642-evm
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- ti,am642-sk
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- const: ti,am642
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additionalProperties: true
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...
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@ -1026,6 +1026,8 @@ patternProperties:
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description: Silex Insight
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"^siliconmitus,.*":
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description: Silicon Mitus, Inc.
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"^siemens,.*":
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description: Siemens AG
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"^simtek,.*":
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description: Cypress Semiconductor Corporation (Simtek Corporation)
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"^sinlinx,.*":
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@ -3,11 +3,17 @@
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# Make file to build device tree binaries for boards based on
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# Texas Instruments Inc processors
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#
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# Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
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# Copyright (C) 2016-2021 Texas Instruments Incorporated - https://www.ti.com/
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#
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dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
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675
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
Normal file
675
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
Normal file
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@ -0,0 +1,675 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM642 SoC Family Main Domain peripherals
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*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_main {
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oc_sram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x00 0x70000000 0x00 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x70000000 0x200000>;
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atf-sram@0 {
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reg = <0x0 0x1a000>;
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};
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01840000 0x00 0xC0000>; /* GICR */
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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dmss: dmss {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges;
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ranges;
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ti,sci-dev-id = <25>;
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secure_proxy_main: mailbox@4d000000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x4d000000 0x00 0x80000>,
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<0x00 0x4a600000 0x00 0x80000>,
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<0x00 0x4a400000 0x00 0x80000>;
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interrupt-names = "rx_012";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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inta_main_dmss: interrupt-controller@48000000 {
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compatible = "ti,sci-inta";
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reg = <0x00 0x48000000 0x00 0x100000>;
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#interrupt-cells = <0>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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msi-controller;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <28>;
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ti,interrupt-ranges = <4 68 36>;
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ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
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};
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main_bcdma: dma-controller@485c0100 {
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compatible = "ti,am64-dmss-bcdma";
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reg = <0x00 0x485c0100 0x00 0x100>,
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<0x00 0x4c000000 0x00 0x20000>,
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<0x00 0x4a820000 0x00 0x20000>,
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<0x00 0x4aa40000 0x00 0x20000>,
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<0x00 0x4bc00000 0x00 0x100000>;
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reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
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msi-parent = <&inta_main_dmss>;
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#dma-cells = <3>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <26>;
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ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
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ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
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ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
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};
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main_pktdma: dma-controller@485c0000 {
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compatible = "ti,am64-dmss-pktdma";
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reg = <0x00 0x485c0000 0x00 0x100>,
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<0x00 0x4a800000 0x00 0x20000>,
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<0x00 0x4aa00000 0x00 0x40000>,
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<0x00 0x4b800000 0x00 0x400000>;
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reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
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msi-parent = <&inta_main_dmss>;
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#dma-cells = <2>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <30>;
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ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
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<0x24>, /* CPSW_TX_CHAN */
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<0x25>, /* SAUL_TX_0_CHAN */
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<0x26>, /* SAUL_TX_1_CHAN */
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<0x27>, /* ICSSG_0_TX_CHAN */
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<0x28>; /* ICSSG_1_TX_CHAN */
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ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
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<0x11>, /* RING_CPSW_TX_CHAN */
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<0x12>, /* RING_SAUL_TX_0_CHAN */
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<0x13>, /* RING_SAUL_TX_1_CHAN */
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<0x14>, /* RING_ICSSG_0_TX_CHAN */
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<0x15>; /* RING_ICSSG_1_TX_CHAN */
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ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
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<0x2b>, /* CPSW_RX_CHAN */
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<0x2d>, /* SAUL_RX_0_CHAN */
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<0x2f>, /* SAUL_RX_1_CHAN */
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<0x31>, /* SAUL_RX_2_CHAN */
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<0x33>, /* SAUL_RX_3_CHAN */
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<0x35>, /* ICSSG_0_RX_CHAN */
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<0x37>; /* ICSSG_1_RX_CHAN */
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ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
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<0x2c>, /* FLOW_CPSW_RX_CHAN */
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<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
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<0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
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<0x36>, /* FLOW_ICSSG_0_RX_CHAN */
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<0x38>; /* FLOW_ICSSG_1_RX_CHAN */
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};
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};
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dmsc: dmsc@44043000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 12>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44043000 0x00 0xfe0>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clocks {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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main_pmx0: pinctrl@f4000 {
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compatible = "pinctrl-single";
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reg = <0x00 0xf4000 0x00 0x2d0>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_conf: syscon@43000000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x00 0x43000000 0x00 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x43000000 0x20000>;
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chipid@14 {
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compatible = "ti,am654-chipid";
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reg = <0x00000014 0x4>;
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};
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phy_gmii_sel: phy@4044 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x4044 0x8>;
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#phy-cells = <1>;
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};
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};
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main_uart0: serial@2800000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 0>;
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clock-names = "fclk";
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};
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main_uart1: serial@2810000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 152 0>;
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clock-names = "fclk";
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};
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main_uart2: serial@2820000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 153 0>;
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clock-names = "fclk";
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};
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main_uart3: serial@2830000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02830000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 154 0>;
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clock-names = "fclk";
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};
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main_uart4: serial@2840000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02840000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 155 0>;
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clock-names = "fclk";
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};
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main_uart5: serial@2850000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02850000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 156 0>;
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clock-names = "fclk";
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};
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main_uart6: serial@2860000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02860000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 158 0>;
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clock-names = "fclk";
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};
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main_i2c0: i2c@20000000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20000000 0x00 0x100>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 102 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_i2c1: i2c@20010000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20010000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 103 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_i2c2: i2c@20020000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20020000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 104 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_i2c3: i2c@20030000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x20030000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 105 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
main_spi0: spi@20100000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x20100000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 141 0>;
|
||||
dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
|
||||
dma-names = "tx0", "rx0";
|
||||
};
|
||||
|
||||
main_spi1: spi@20110000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20110000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 142 0>;
|
||||
};
|
||||
|
||||
main_spi2: spi@20120000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20120000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 143 0>;
|
||||
};
|
||||
|
||||
main_spi3: spi@20130000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20130000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 144 0>;
|
||||
};
|
||||
|
||||
main_spi4: spi@20140000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20140000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 145 0>;
|
||||
};
|
||||
|
||||
main_gpio_intr: interrupt-controller0 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <3>;
|
||||
ti,interrupt-ranges = <0 32 16>;
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x00600000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <190>, <191>, <192>,
|
||||
<193>, <194>, <195>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <87>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 77 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_gpio1: gpio@601000 {
|
||||
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x00601000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <180>, <181>, <182>,
|
||||
<183>, <184>, <185>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <88>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 78 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
sdhci0: mmc@fa10000 {
|
||||
compatible = "ti,am64-sdhci-8bit";
|
||||
reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
ti,trm-icp = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-mmc-hs = <0x0>;
|
||||
ti,otap-del-sel-ddr52 = <0x6>;
|
||||
ti,otap-del-sel-hs200 = <0x7>;
|
||||
ti,otap-del-sel-hs400 = <0x4>;
|
||||
};
|
||||
|
||||
sdhci1: mmc@fa00000 {
|
||||
compatible = "ti,am64-sdhci-4bit";
|
||||
reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
ti,trm-icp = <0x2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0xf>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x6>;
|
||||
ti,otap-del-sel-ddr50 = <0x9>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
};
|
||||
|
||||
cpsw3g: ethernet@8000000 {
|
||||
compatible = "ti,am642-cpsw-nuss";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x0 0x8000000 0x0 0x200000>;
|
||||
reg-names = "cpsw_nuss";
|
||||
ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
assigned-clocks = <&k3_clks 13 1>;
|
||||
assigned-clock-parents = <&k3_clks 13 9>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
dmas = <&main_pktdma 0xC500 15>,
|
||||
<&main_pktdma 0xC501 15>,
|
||||
<&main_pktdma 0xC502 15>,
|
||||
<&main_pktdma 0xC503 15>,
|
||||
<&main_pktdma 0xC504 15>,
|
||||
<&main_pktdma 0xC505 15>,
|
||||
<&main_pktdma 0xC506 15>,
|
||||
<&main_pktdma 0xC507 15>,
|
||||
<&main_pktdma 0x4500 15>;
|
||||
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
|
||||
"tx7", "rx";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpsw_port1: port@1 {
|
||||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
mac-address = [00 00 de ad be ef];
|
||||
};
|
||||
|
||||
cpsw_port2: port@2 {
|
||||
reg = <2>;
|
||||
ti,mac-only;
|
||||
label = "port2";
|
||||
phys = <&phy_gmii_sel 2>;
|
||||
mac-address = [00 01 de ad be ef];
|
||||
};
|
||||
};
|
||||
|
||||
cpsw3g_mdio: mdio@f00 {
|
||||
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||
reg = <0x0 0xf00 0x0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
|
||||
cpts@3d000 {
|
||||
compatible = "ti,j721e-cpts";
|
||||
reg = <0x0 0x3d000 0x0 0x400>;
|
||||
clocks = <&k3_clks 13 1>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-ext-ts-inputs = <4>;
|
||||
ti,cpts-periodic-outputs = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
cpts@39000000 {
|
||||
compatible = "ti,j721e-cpts";
|
||||
reg = <0x0 0x39000000 0x0 0x400>;
|
||||
reg-names = "cpts";
|
||||
power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 84 0>;
|
||||
clock-names = "cpts";
|
||||
assigned-clocks = <&k3_clks 84 0>;
|
||||
assigned-clock-parents = <&k3_clks 84 8>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-periodic-outputs = <6>;
|
||||
ti,cpts-ext-ts-inputs = <8>;
|
||||
};
|
||||
|
||||
usbss0: cdns-usb@f900000{
|
||||
compatible = "ti,am64-usb";
|
||||
reg = <0x00 0xf900000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
|
||||
clock-names = "ref", "lpm";
|
||||
assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
|
||||
assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
usb0: usb@f400000{
|
||||
compatible = "cdns,usb3";
|
||||
reg = <0x00 0xf400000 0x00 0x10000>,
|
||||
<0x00 0xf410000 0x00 0x10000>,
|
||||
<0x00 0xf420000 0x00 0x10000>;
|
||||
reg-names = "otg",
|
||||
"xhci",
|
||||
"dev";
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
||||
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
|
||||
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
|
||||
interrupt-names = "host",
|
||||
"peripheral",
|
||||
"otg";
|
||||
maximum-speed = "super-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
};
|
||||
|
||||
tscadc0: tscadc@28001000 {
|
||||
compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
|
||||
reg = <0x00 0x28001000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 0 0>;
|
||||
assigned-clocks = <&k3_clks 0 0>;
|
||||
assigned-clock-parents = <&k3_clks 0 3>;
|
||||
assigned-clock-rates = <60000000>;
|
||||
clock-names = "adc_tsc_fck";
|
||||
|
||||
adc {
|
||||
#io-channel-cells = <1>;
|
||||
compatible = "ti,am654-adc", "ti,am3359-adc";
|
||||
};
|
||||
};
|
||||
|
||||
fss: bus@fc00000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x00 0x0fc00000 0x00 0x70000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ospi0: spi@fc40000 {
|
||||
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
||||
reg = <0x00 0x0fc40000 0x00 0x100>,
|
||||
<0x05 0x00000000 0x01 0x00000000>;
|
||||
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cdns,fifo-depth = <256>;
|
||||
cdns,fifo-width = <4>;
|
||||
cdns,trigger-address = <0x0>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
clocks = <&k3_clks 75 6>;
|
||||
assigned-clocks = <&k3_clks 75 6>;
|
||||
assigned-clock-parents = <&k3_clks 75 7>;
|
||||
assigned-clock-rates = <166666666>;
|
||||
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@2a000000 {
|
||||
compatible = "ti,am64-hwspinlock";
|
||||
reg = <0x00 0x2a000000 0x00 0x1000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
mailbox0_cluster2: mailbox@29020000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29020000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
|
||||
mailbox0_cluster3: mailbox@29030000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29030000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
|
||||
mailbox0_cluster4: mailbox@29040000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29040000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
|
||||
mailbox0_cluster5: mailbox@29050000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29050000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
|
||||
mailbox0_cluster6: mailbox@29060000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29060000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
|
||||
mailbox0_cluster7: mailbox@29070000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29070000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
};
|
||||
103
arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
Normal file
103
arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM64 SoC Family MCU Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu {
|
||||
mcu_uart0: serial@4a00000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 149 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
mcu_uart1: serial@4a10000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a10000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 160 0>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
mcu_i2c0: i2c@4900000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x04900000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 106 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
mcu_i2c1: i2c@4910000 {
|
||||
compatible = "ti,am64-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x04910000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 107 2>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
mcu_spi0: spi@4b00000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b00000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 147 0>;
|
||||
};
|
||||
|
||||
mcu_spi1: spi@4b10000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b10000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 148 0>;
|
||||
};
|
||||
|
||||
mcu_gpio_intr: interrupt-controller1 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <5>;
|
||||
ti,interrupt-ranges = <0 104 4>;
|
||||
};
|
||||
|
||||
mcu_gpio0: gpio@4201000 {
|
||||
compatible = "ti,am64-gpio", "keystone-gpio";
|
||||
reg = <0x0 0x4201000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&mcu_gpio_intr>;
|
||||
interrupts = <30>, <31>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <23>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 79 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
};
|
||||
105
arch/arm64/boot/dts/ti/k3-am64.dtsi
Normal file
105
arch/arm64/boot/dts/ti/k3-am64.dtsi
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM642 SoC Family
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 AM642 SoC";
|
||||
compatible = "ti,am642";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &mcu_uart0;
|
||||
serial1 = &mcu_uart1;
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
serial4 = &main_uart2;
|
||||
serial5 = &main_uart3;
|
||||
serial6 = &main_uart4;
|
||||
serial7 = &main_uart5;
|
||||
serial8 = &main_uart6;
|
||||
ethernet0 = &cpsw_port1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a53_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@f4000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
|
||||
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
|
||||
<0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
|
||||
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
|
||||
<0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
|
||||
<0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
|
||||
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
|
||||
<0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
|
||||
<0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
|
||||
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
||||
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
|
||||
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
|
||||
<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
|
||||
<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
|
||||
<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
|
||||
|
||||
/* MCU Domain Range */
|
||||
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
|
||||
|
||||
cbass_mcu: bus@4000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include the peripherals for each bus segments */
|
||||
#include "k3-am64-main.dtsi"
|
||||
#include "k3-am64-mcu.dtsi"
|
||||
468
arch/arm64/boot/dts/ti/k3-am642-evm.dts
Normal file
468
arch/arm64/boot/dts/ti/k3-am642-evm.dts
Normal file
|
|
@ -0,0 +1,468 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am642-evm", "ti,am642";
|
||||
model = "Texas Instruments AM642 EVM";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
/* main DC jack */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_12v0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_5v0: fixedregulator-vsys5v0 {
|
||||
/* output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_3v3: fixedregulator-vsys3v3 {
|
||||
/* output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: fixed-regulator-sd {
|
||||
/* TPS2051BD */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vddb: fixedregulator-vddb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddb_3v3_display";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
label = "am64-evm:red:heartbeat";
|
||||
gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
mdio_mux: mux-controller {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
|
||||
mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
mdio-mux-1 {
|
||||
compatible = "mdio-mux-multiplexer";
|
||||
mux-controls = <&mdio_mux>;
|
||||
mdio-parent-bus = <&cpsw3g_mdio>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@1 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpsw3g_phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
|
||||
AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
|
||||
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
|
||||
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_spi0_pins_default: main-spi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
|
||||
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
|
||||
AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
|
||||
AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
|
||||
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
mdio1_pins_default: mdio1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
|
||||
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii1_pins_default: rgmii1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
|
||||
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
|
||||
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii2_pins_default: rgmii2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
|
||||
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
|
||||
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
|
||||
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
|
||||
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
|
||||
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
|
||||
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
|
||||
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
|
||||
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
|
||||
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
|
||||
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
|
||||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usb0_pins_default: main-usb0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
|
||||
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
|
||||
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
|
||||
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
|
||||
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
|
||||
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
|
||||
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
|
||||
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
|
||||
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
|
||||
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
|
||||
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
||||
/* main_uart1 is reserved for firmware usage */
|
||||
&main_uart1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@22 {
|
||||
compatible = "ti,tca6424";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
|
||||
"GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
|
||||
"GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
|
||||
"MMC1_SD_EN", "FSI_FET_SEL",
|
||||
"MCAN0_STB_3V3", "MCAN1_STB_3V3",
|
||||
"CPSW_FET_SEL", "CPSW_FET2_SEL",
|
||||
"PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
|
||||
"GPIO_OLED_RESETn", "VPP_LDO_EN",
|
||||
"TEST_LED1", "TP92", "TP90", "TP88",
|
||||
"TP87", "TP86", "TP89", "TP91";
|
||||
};
|
||||
|
||||
/* osd9616p0899-10 */
|
||||
display@3c {
|
||||
compatible = "solomon,ssd1306fb-i2c";
|
||||
reg = <0x3c>;
|
||||
reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
|
||||
vbat-supply = <&vddb>;
|
||||
solomon,height = <16>;
|
||||
solomon,width = <96>;
|
||||
solomon,com-seq;
|
||||
solomon,com-invdir;
|
||||
solomon,page-offset = <0>;
|
||||
solomon,prechargep1 = <2>;
|
||||
solomon,prechargep2 = <13>;
|
||||
};
|
||||
};
|
||||
|
||||
/* mcu_gpio0 is reserved for mcu firmware usage */
|
||||
&mcu_gpio0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_spi0_pins_default>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
eeprom@0 {
|
||||
compatible = "microchip,93lc46b";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
spi-cs-high;
|
||||
data-size = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
/* emmc */
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
ti,usb2-only;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb0_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
&rgmii1_pins_default
|
||||
&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy3>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
/* ADC is reserved for R5 usage */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
334
arch/arm64/boot/dts/ti/k3-am642-sk.dts
Normal file
334
arch/arm64/boot/dts/ti/k3-am642-sk.dts
Normal file
|
|
@ -0,0 +1,334 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am642-sk", "ti,am642";
|
||||
model = "Texas Instruments AM642 SK";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vusb_main: fixed-regulator-vusb-main5v0 {
|
||||
/* USB MAIN INPUT 5V DC */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vusb_main5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
|
||||
/* output of LP8733xx */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_sys";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vusb_main>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: fixed-regulator-sd {
|
||||
/* TPS2051BD */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vcc_3v3_sys>;
|
||||
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
|
||||
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
mdio1_pins_default: mdio1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
|
||||
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii1_pins_default: rgmii1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
|
||||
AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
|
||||
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
rgmii2_pins_default: rgmii2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
|
||||
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
|
||||
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
|
||||
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
|
||||
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
|
||||
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
|
||||
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
|
||||
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
|
||||
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
|
||||
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
|
||||
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
|
||||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
|
||||
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
|
||||
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
|
||||
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
|
||||
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
|
||||
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
|
||||
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
|
||||
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
|
||||
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
|
||||
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
|
||||
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
/* main_uart1 is reserved for firmware usage */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@70 {
|
||||
compatible = "nxp,pca9538";
|
||||
reg = <0x70>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
|
||||
"PRU_DETECT", "MMC1_SD_EN",
|
||||
"VPP_LDO_EN", "RPI_PS_3V3_En",
|
||||
"RPI_PS_5V0_En", "RPI_HAT_DETECT";
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* mcu_gpio0 is reserved for mcu firmware usage */
|
||||
&mcu_gpio0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
&rgmii1_pins_default
|
||||
&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
|
||||
cpsw3g_phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
65
arch/arm64/boot/dts/ti/k3-am642.dtsi
Normal file
65
arch/arm64/boot/dts/ti/k3-am642.dtsi
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for AM642 SoC family in Dual core configuration
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am64.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x40000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
};
|
||||
};
|
||||
655
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
Normal file
655
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
Normal file
|
|
@ -0,0 +1,655 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) Siemens AG, 2018-2021
|
||||
*
|
||||
* Authors:
|
||||
* Le Jin <le.jin@siemens.com>
|
||||
* Jan Kiszka <jan.kiszk@siemens.com>
|
||||
*
|
||||
* Common bits of the IOT2050 Basic and Advanced variants
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am654.dtsi"
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
spi0 = &mcu_spi0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial3:115200n8";
|
||||
bootargs = "earlycon=ns16550a,mmio32,0x02810000";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: secure-ddr@9e800000 {
|
||||
reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa0000000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa0100000 0 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa1000000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa1100000 0 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a2000000 {
|
||||
reg = <0x00 0xa2000000 0x00 0x00200000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins_default>;
|
||||
|
||||
status-led-red {
|
||||
gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>;
|
||||
panic-indicator;
|
||||
};
|
||||
|
||||
status-led-green {
|
||||
gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
user-led1-red {
|
||||
gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
user-led1-green {
|
||||
gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
user-led2-red {
|
||||
gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
user-led2-green {
|
||||
gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
dp_refclk: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (AC7) WKUP_I2C0_SCL */
|
||||
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0)
|
||||
/* (AD6) WKUP_I2C0_SDA */
|
||||
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0)
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_i2c0_pins_default: mcu-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (AD8) MCU_I2C0_SCL */
|
||||
AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0)
|
||||
/* (AD7) MCU_I2C0_SDA */
|
||||
AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0)
|
||||
>;
|
||||
};
|
||||
|
||||
arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (R2) WKUP_GPIO0_21 */
|
||||
AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
|
||||
>;
|
||||
};
|
||||
|
||||
push_button_pins_default: push-button-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
|
||||
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7)
|
||||
>;
|
||||
};
|
||||
|
||||
arduino_uart_pins_default: arduino-uart-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (P4) MCU_UART0_RXD */
|
||||
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
|
||||
/* (P5) MCU_UART0_TXD */
|
||||
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
|
||||
>;
|
||||
};
|
||||
|
||||
arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (P1) WKUP_GPIO0_31 */
|
||||
AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
|
||||
/* (N3) WKUP_GPIO0_33 */
|
||||
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7)
|
||||
>;
|
||||
};
|
||||
|
||||
arduino_io_oe_pins_default: arduino-io-oe-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (N4) WKUP_GPIO0_34 */
|
||||
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
|
||||
/* (M2) WKUP_GPIO0_36 */
|
||||
AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7)
|
||||
/* (M3) WKUP_GPIO0_37 */
|
||||
AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7)
|
||||
/* (M4) WKUP_GPIO0_38 */
|
||||
AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7)
|
||||
/* (M1) WKUP_GPIO0_41 */
|
||||
AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7)
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (V1) MCU_OSPI0_CLK */
|
||||
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0)
|
||||
/* (U2) MCU_OSPI0_DQS */
|
||||
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)
|
||||
/* (U4) MCU_OSPI0_D0 */
|
||||
AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)
|
||||
/* (U5) MCU_OSPI0_D1 */
|
||||
AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)
|
||||
/* (R4) MCU_OSPI0_CSn0 */
|
||||
AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0)
|
||||
>;
|
||||
};
|
||||
|
||||
db9_com_mode_pins_default: db9-com-mode-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
|
||||
AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)
|
||||
/* (AC3) WKUP_GPIO0_4, used as uart0 mode 1 */
|
||||
AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7)
|
||||
/* (AC1) WKUP_GPIO0_7, used as uart0 term */
|
||||
AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7)
|
||||
/* (AC2) WKUP_GPIO0_6, used as uart0 en */
|
||||
AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7)
|
||||
>;
|
||||
};
|
||||
|
||||
leds_pins_default: leds-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (T2) WKUP_GPIO0_17, used as user led1 red */
|
||||
AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)
|
||||
/* (R3) WKUP_GPIO0_22, used as user led1 green */
|
||||
AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7)
|
||||
/* (R5) WKUP_GPIO0_24, used as status led red */
|
||||
AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7)
|
||||
/* (N2) WKUP_GPIO0_32, used as status led green */
|
||||
AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7)
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_spi0_pins_default: mcu-spi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (Y1) MCU_SPI0_CLK */
|
||||
AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
|
||||
/* (Y3) MCU_SPI0_D0 */
|
||||
AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0)
|
||||
/* (Y2) MCU_SPI0_D1 */
|
||||
AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0)
|
||||
/* (Y4) MCU_SPI0_CS0 */
|
||||
AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
|
||||
>;
|
||||
};
|
||||
|
||||
minipcie_pins_default: minipcie-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
/* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
|
||||
AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_uart1_pins_default: main-uart1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
|
||||
AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */
|
||||
AM65X_IOPAD(0x0178, PIN_INPUT, 6) /* (AD22) UART1_CTSn */
|
||||
AM65X_IOPAD(0x017c, PIN_OUTPUT, 6) /* (AC21) UART1_RTSn */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c3_pins_default: main-i2c3-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */
|
||||
AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
|
||||
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
|
||||
AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
|
||||
AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
|
||||
AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
|
||||
AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
|
||||
AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
|
||||
AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */
|
||||
>;
|
||||
};
|
||||
|
||||
usb0_pins_default: usb0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
usb1_pins_default: usb1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */
|
||||
AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */
|
||||
AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */
|
||||
AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */
|
||||
AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */
|
||||
AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */
|
||||
>;
|
||||
};
|
||||
|
||||
dss_vout1_pins_default: dss-vout1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
|
||||
AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */
|
||||
AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */
|
||||
AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */
|
||||
AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */
|
||||
AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */
|
||||
AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */
|
||||
AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */
|
||||
AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */
|
||||
AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */
|
||||
AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */
|
||||
AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */
|
||||
AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */
|
||||
AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */
|
||||
AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */
|
||||
AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */
|
||||
AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */
|
||||
AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */
|
||||
AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */
|
||||
AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */
|
||||
AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */
|
||||
AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */
|
||||
AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */
|
||||
AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */
|
||||
AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */
|
||||
AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */
|
||||
AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */
|
||||
AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */
|
||||
>;
|
||||
};
|
||||
|
||||
dp_pins_default: dp-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c2_pins_default: main-i2c2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
|
||||
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx1 {
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
|
||||
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
|
||||
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
ecap0_pins_default: ecap0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
/* Wakeup UART is used by System firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&arduino_uart_pins_default>;
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>;
|
||||
gpio-line-names =
|
||||
"main_gpio0-base", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
"", "", "", "IO4", "", "IO5", "", "", "IO6", "",
|
||||
"", "", "", "IO7", "", "", "", "", "IO8", "",
|
||||
"", "IO9";
|
||||
};
|
||||
|
||||
&wkup_gpio0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&arduino_io_d2_to_d3_pins_default
|
||||
&arduino_i2c_aio_switch_pins_default
|
||||
&arduino_io_oe_pins_default
|
||||
&push_button_pins_default
|
||||
&db9_com_mode_pins_default
|
||||
>;
|
||||
gpio-line-names =
|
||||
/* 0..9 */
|
||||
"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
|
||||
"UART0-enable", "UART0-terminate", "", "WIFI-disable",
|
||||
/* 10..19 */
|
||||
"", "", "", "", "", "", "", "", "", "",
|
||||
/* 20..29 */
|
||||
"", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0",
|
||||
/* 30..39 */
|
||||
"IO1", "IO2", "", "IO3", "IO17-direction", "A5",
|
||||
"IO16-direction", "IO15-direction", "IO14-direction", "A3",
|
||||
/* 40..49 */
|
||||
"", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13",
|
||||
"IO11",
|
||||
/* 50..51 */
|
||||
"IO12", "IO10";
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
psu: regulator@60 {
|
||||
compatible = "ti,tps62363";
|
||||
reg = <0x60>;
|
||||
regulator-name = "tps62363-vout";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
ti,vsel0-state-high;
|
||||
ti,vsel1-state-high;
|
||||
ti,enable-vout-discharge;
|
||||
};
|
||||
|
||||
/* D4200 */
|
||||
pcal9535_1: gpio@20 {
|
||||
compatible = "nxp,pcal9535";
|
||||
reg = <0x20>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-line-names =
|
||||
"A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull",
|
||||
"A5-pull", "", "",
|
||||
"IO14-enable", "IO15-enable", "IO16-enable",
|
||||
"IO17-enable", "IO18-enable", "IO19-enable";
|
||||
};
|
||||
|
||||
/* D4201 */
|
||||
pcal9535_2: gpio@21 {
|
||||
compatible = "nxp,pcal9535";
|
||||
reg = <0x21>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-line-names =
|
||||
"IO0-direction", "IO1-direction", "IO2-direction",
|
||||
"IO3-direction", "IO4-direction", "IO5-direction",
|
||||
"IO6-direction", "IO7-direction",
|
||||
"IO8-direction", "IO9-direction", "IO10-direction",
|
||||
"IO11-direction", "IO12-direction", "IO13-direction",
|
||||
"IO19-direction";
|
||||
};
|
||||
|
||||
/* D4202 */
|
||||
pcal9535_3: gpio@25 {
|
||||
compatible = "nxp,pcal9535";
|
||||
reg = <0x25>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-line-names =
|
||||
"IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull",
|
||||
"IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull",
|
||||
"IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull",
|
||||
"IO12-pull", "IO13-pull";
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
rtc: rtc8564@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
eeprom: eeprom@54 {
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x54>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&main_i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c2_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&main_i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c3_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
edp-bridge@f {
|
||||
compatible = "toshiba,tc358767";
|
||||
reg = <0x0f>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dp_pins_default>;
|
||||
reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
clock-names = "ref";
|
||||
clocks = <&dp_refclk>;
|
||||
|
||||
toshiba,hpd-pin = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
bridge_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap0_pins_default>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb0_pins_default>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb1_pins_default>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&mcu_spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_spi0_pins_default>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells= <0>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&tscadc1 {
|
||||
adc {
|
||||
ti,adc-channels = <0 1 2 3 4 5>;
|
||||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dss_vout1_pins_default>;
|
||||
|
||||
assigned-clocks = <&k3_clks 67 2>;
|
||||
assigned-clock-parents = <&k3_clks 67 5>;
|
||||
};
|
||||
|
||||
&dss_ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dpi_out: endpoint {
|
||||
remote-endpoint = <&bridge_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie1_rc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&minipcie_pins_default>;
|
||||
|
||||
num-lanes = <1>;
|
||||
phys = <&serdes1 PHY_TYPE_PCIE 0>;
|
||||
phy-names = "pcie-phy0";
|
||||
reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&pcie1_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -707,6 +707,7 @@ pcie0_rc: pcie@5500000 {
|
|||
dma-coherent;
|
||||
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pcie0_ep: pcie-ep@5500000 {
|
||||
|
|
@ -739,6 +740,7 @@ pcie1_rc: pcie@5600000 {
|
|||
dma-coherent;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
|
||||
msi-map = <0x0 &gic_its 0x10000 0x10000>;
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pcie1_ep: pcie-ep@5600000 {
|
||||
|
|
@ -919,4 +921,397 @@ ehrpwm5: pwm@3050000 {
|
|||
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
};
|
||||
|
||||
icssg0: icssg@b000000 {
|
||||
compatible = "ti,am654-icssg";
|
||||
reg = <0x00 0xb000000 0x00 0x80000>;
|
||||
power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0xb000000 0x80000>;
|
||||
|
||||
icssg0_mem: memories@0 {
|
||||
reg = <0x0 0x2000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x10000 0x10000>;
|
||||
reg-names = "dram0", "dram1",
|
||||
"shrdram2";
|
||||
};
|
||||
|
||||
icssg0_cfg: cfg@26000 {
|
||||
compatible = "ti,pruss-cfg", "syscon";
|
||||
reg = <0x26000 0x200>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x26000 0x2000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
icssg0_coreclk_mux: coreclk-mux@3c {
|
||||
reg = <0x3c>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
|
||||
<&k3_clks 62 3>; /* icssg0_iclk */
|
||||
assigned-clocks = <&icssg0_coreclk_mux>;
|
||||
assigned-clock-parents = <&k3_clks 62 3>;
|
||||
};
|
||||
|
||||
icssg0_iepclk_mux: iepclk-mux@30 {
|
||||
reg = <0x30>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */
|
||||
<&icssg0_coreclk_mux>; /* core_clk */
|
||||
assigned-clocks = <&icssg0_iepclk_mux>;
|
||||
assigned-clock-parents = <&icssg0_coreclk_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
icssg0_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
};
|
||||
|
||||
icssg0_mii_g_rt: mii-g-rt@33000 {
|
||||
compatible = "ti,pruss-mii-g", "syscon";
|
||||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg0_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host_intr0", "host_intr1",
|
||||
"host_intr2", "host_intr3",
|
||||
"host_intr4", "host_intr5",
|
||||
"host_intr6", "host_intr7";
|
||||
};
|
||||
|
||||
pru0_0: pru@34000 {
|
||||
compatible = "ti,am654-pru";
|
||||
reg = <0x34000 0x4000>,
|
||||
<0x22000 0x100>,
|
||||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru0_0-fw";
|
||||
};
|
||||
|
||||
rtu0_0: rtu@4000 {
|
||||
compatible = "ti,am654-rtu";
|
||||
reg = <0x4000 0x2000>,
|
||||
<0x23000 0x100>,
|
||||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu0_0-fw";
|
||||
};
|
||||
|
||||
tx_pru0_0: txpru@a000 {
|
||||
compatible = "ti,am654-tx-pru";
|
||||
reg = <0xa000 0x1800>,
|
||||
<0x25000 0x100>,
|
||||
<0x25400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-txpru0_0-fw";
|
||||
};
|
||||
|
||||
pru0_1: pru@38000 {
|
||||
compatible = "ti,am654-pru";
|
||||
reg = <0x38000 0x4000>,
|
||||
<0x24000 0x100>,
|
||||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru0_1-fw";
|
||||
};
|
||||
|
||||
rtu0_1: rtu@6000 {
|
||||
compatible = "ti,am654-rtu";
|
||||
reg = <0x6000 0x2000>,
|
||||
<0x23800 0x100>,
|
||||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu0_1-fw";
|
||||
};
|
||||
|
||||
tx_pru0_1: txpru@c000 {
|
||||
compatible = "ti,am654-tx-pru";
|
||||
reg = <0xc000 0x1800>,
|
||||
<0x25800 0x100>,
|
||||
<0x25c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-txpru0_1-fw";
|
||||
};
|
||||
};
|
||||
|
||||
icssg1: icssg@b100000 {
|
||||
compatible = "ti,am654-icssg";
|
||||
reg = <0x00 0xb100000 0x00 0x80000>;
|
||||
power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0xb100000 0x80000>;
|
||||
|
||||
icssg1_mem: memories@0 {
|
||||
reg = <0x0 0x2000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x10000 0x10000>;
|
||||
reg-names = "dram0", "dram1",
|
||||
"shrdram2";
|
||||
};
|
||||
|
||||
icssg1_cfg: cfg@26000 {
|
||||
compatible = "ti,pruss-cfg", "syscon";
|
||||
reg = <0x26000 0x200>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x26000 0x2000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
icssg1_coreclk_mux: coreclk-mux@3c {
|
||||
reg = <0x3c>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
|
||||
<&k3_clks 63 3>; /* icssg1_iclk */
|
||||
assigned-clocks = <&icssg1_coreclk_mux>;
|
||||
assigned-clock-parents = <&k3_clks 63 3>;
|
||||
};
|
||||
|
||||
icssg1_iepclk_mux: iepclk-mux@30 {
|
||||
reg = <0x30>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */
|
||||
<&icssg1_coreclk_mux>; /* core_clk */
|
||||
assigned-clocks = <&icssg1_iepclk_mux>;
|
||||
assigned-clock-parents = <&icssg1_coreclk_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
icssg1_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
};
|
||||
|
||||
icssg1_mii_g_rt: mii-g-rt@33000 {
|
||||
compatible = "ti,pruss-mii-g", "syscon";
|
||||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg1_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host_intr0", "host_intr1",
|
||||
"host_intr2", "host_intr3",
|
||||
"host_intr4", "host_intr5",
|
||||
"host_intr6", "host_intr7";
|
||||
};
|
||||
|
||||
pru1_0: pru@34000 {
|
||||
compatible = "ti,am654-pru";
|
||||
reg = <0x34000 0x4000>,
|
||||
<0x22000 0x100>,
|
||||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru1_0-fw";
|
||||
};
|
||||
|
||||
rtu1_0: rtu@4000 {
|
||||
compatible = "ti,am654-rtu";
|
||||
reg = <0x4000 0x2000>,
|
||||
<0x23000 0x100>,
|
||||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu1_0-fw";
|
||||
};
|
||||
|
||||
tx_pru1_0: txpru@a000 {
|
||||
compatible = "ti,am654-tx-pru";
|
||||
reg = <0xa000 0x1800>,
|
||||
<0x25000 0x100>,
|
||||
<0x25400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-txpru1_0-fw";
|
||||
};
|
||||
|
||||
pru1_1: pru@38000 {
|
||||
compatible = "ti,am654-pru";
|
||||
reg = <0x38000 0x4000>,
|
||||
<0x24000 0x100>,
|
||||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru1_1-fw";
|
||||
};
|
||||
|
||||
rtu1_1: rtu@6000 {
|
||||
compatible = "ti,am654-rtu";
|
||||
reg = <0x6000 0x2000>,
|
||||
<0x23800 0x100>,
|
||||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu1_1-fw";
|
||||
};
|
||||
|
||||
tx_pru1_1: txpru@c000 {
|
||||
compatible = "ti,am654-tx-pru";
|
||||
reg = <0xc000 0x1800>,
|
||||
<0x25800 0x100>,
|
||||
<0x25c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-txpru1_1-fw";
|
||||
};
|
||||
};
|
||||
|
||||
icssg2: icssg@b200000 {
|
||||
compatible = "ti,am654-icssg";
|
||||
reg = <0x00 0xb200000 0x00 0x80000>;
|
||||
power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0xb200000 0x80000>;
|
||||
|
||||
icssg2_mem: memories@0 {
|
||||
reg = <0x0 0x2000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x10000 0x10000>;
|
||||
reg-names = "dram0", "dram1",
|
||||
"shrdram2";
|
||||
};
|
||||
|
||||
icssg2_cfg: cfg@26000 {
|
||||
compatible = "ti,pruss-cfg", "syscon";
|
||||
reg = <0x26000 0x200>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x26000 0x2000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
icssg2_coreclk_mux: coreclk-mux@3c {
|
||||
reg = <0x3c>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
|
||||
<&k3_clks 64 3>; /* icssg1_iclk */
|
||||
assigned-clocks = <&icssg2_coreclk_mux>;
|
||||
assigned-clock-parents = <&k3_clks 64 3>;
|
||||
};
|
||||
|
||||
icssg2_iepclk_mux: iepclk-mux@30 {
|
||||
reg = <0x30>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */
|
||||
<&icssg2_coreclk_mux>; /* core_clk */
|
||||
assigned-clocks = <&icssg2_iepclk_mux>;
|
||||
assigned-clock-parents = <&icssg2_coreclk_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
icssg2_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
};
|
||||
|
||||
icssg2_mii_g_rt: mii-g-rt@33000 {
|
||||
compatible = "ti,pruss-mii-g", "syscon";
|
||||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg2_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host_intr0", "host_intr1",
|
||||
"host_intr2", "host_intr3",
|
||||
"host_intr4", "host_intr5",
|
||||
"host_intr6", "host_intr7";
|
||||
};
|
||||
|
||||
pru2_0: pru@34000 {
|
||||
compatible = "ti,am654-pru";
|
||||
reg = <0x34000 0x4000>,
|
||||
<0x22000 0x100>,
|
||||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru2_0-fw";
|
||||
};
|
||||
|
||||
rtu2_0: rtu@4000 {
|
||||
compatible = "ti,am654-rtu";
|
||||
reg = <0x4000 0x2000>,
|
||||
<0x23000 0x100>,
|
||||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu2_0-fw";
|
||||
};
|
||||
|
||||
tx_pru2_0: txpru@a000 {
|
||||
compatible = "ti,am654-tx-pru";
|
||||
reg = <0xa000 0x1800>,
|
||||
<0x25000 0x100>,
|
||||
<0x25400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-txpru2_0-fw";
|
||||
};
|
||||
|
||||
pru2_1: pru@38000 {
|
||||
compatible = "ti,am654-pru";
|
||||
reg = <0x38000 0x4000>,
|
||||
<0x24000 0x100>,
|
||||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-pru2_1-fw";
|
||||
};
|
||||
|
||||
rtu2_1: rtu@6000 {
|
||||
compatible = "ti,am654-rtu";
|
||||
reg = <0x6000 0x2000>,
|
||||
<0x23800 0x100>,
|
||||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-rtu2_1-fw";
|
||||
};
|
||||
|
||||
tx_pru2_1: txpru@c000 {
|
||||
compatible = "ti,am654-tx-pru";
|
||||
reg = <0xc000 0x1800>,
|
||||
<0x25800 0x100>,
|
||||
<0x25c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "am65x-txpru2_1-fw";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -308,4 +308,13 @@ mcu_r5fss0_core1: r5f@41400000 {
|
|||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
mcu_rti1: watchdog@40610000 {
|
||||
compatible = "ti,j7-rti-wdt";
|
||||
reg = <0x0 0x40610000 0x0 0x100>;
|
||||
clocks = <&k3_clks 135 0>;
|
||||
power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
|
||||
assigned-clocks = <&k3_clks 135 0>;
|
||||
assigned-clock-parents = <&k3_clks 135 4>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
61
arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
Normal file
61
arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) Siemens AG, 2018-2021
|
||||
*
|
||||
* Authors:
|
||||
* Le Jin <le.jin@siemens.com>
|
||||
* Jan Kiszka <jan.kiszk@siemens.com>
|
||||
*
|
||||
* AM6528-based (dual-core) IOT2050 Basic variant
|
||||
* 1 GB RAM, no eMMC, main_uart0 on connector X30
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am65-iot2050-common.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "siemens,iot2050-basic", "ti,am654";
|
||||
model = "SIMATIC IOT2050 Basic";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 1G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu-map {
|
||||
/delete-node/ cluster1;
|
||||
};
|
||||
/delete-node/ cpu@100;
|
||||
/delete-node/ cpu@101;
|
||||
};
|
||||
|
||||
/delete-node/ l2-cache1;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sdhci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
|
||||
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
|
||||
AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
|
||||
AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
|
||||
AM65X_IOPAD(0x0188, PIN_INPUT, 1) /* (D25) UART0_DCDn */
|
||||
AM65X_IOPAD(0x018c, PIN_INPUT, 1) /* (B26) UART0_DSRn */
|
||||
AM65X_IOPAD(0x0190, PIN_OUTPUT, 1) /* (A24) UART0_DTRn */
|
||||
AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
|
@ -483,9 +483,9 @@ &ospi0 {
|
|||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <40000000>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
|
|
|
|||
60
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
Normal file
60
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) Siemens AG, 2018-2021
|
||||
*
|
||||
* Authors:
|
||||
* Le Jin <le.jin@siemens.com>
|
||||
* Jan Kiszka <jan.kiszk@siemens.com>
|
||||
*
|
||||
* AM6548-based (quad-core) IOT2050 Advanced variant
|
||||
* 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am65-iot2050-common.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "siemens,iot2050-advanced", "ti,am654";
|
||||
model = "SIMATIC IOT2050 Advanced";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc0_pins_default: main-mmc0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
|
||||
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
|
||||
AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
|
||||
AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
|
||||
AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
|
||||
AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
|
||||
AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
|
||||
AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
|
||||
AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
|
||||
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
|
||||
AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP, 7) /* (B23) MMC0_SDWP */
|
||||
AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
|
||||
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -16,6 +16,65 @@ chosen {
|
|||
stdout-path = "serial2:115200n8";
|
||||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
/* main supply */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_12v0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_3v3: fixedregulator-vsys3v3 {
|
||||
/* Output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_5v0: fixedregulator-vsys5v0 {
|
||||
/* Output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: fixedregulator-sd {
|
||||
/* Output of TPS22918 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vdd_sd_dv: gpio-regulator-TLV71033 {
|
||||
/* Output of TLV71033 */
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "tlv71033";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_sd_dv_pins_default>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vsys_5v0>;
|
||||
gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x0>,
|
||||
<3300000 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
|
|
@ -45,6 +104,13 @@ J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
|
|||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
|
||||
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
|
||||
|
|
@ -70,6 +136,12 @@ main_usbss0_pins_default: main-usbss0-pins-default {
|
|||
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
|
|
@ -122,6 +194,22 @@ &main_uart9 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_gpio2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_gpio4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_gpio6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wkup_gpio1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
||||
|
|
@ -141,6 +229,10 @@ &cpsw_port1 {
|
|||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
|
|
@ -190,6 +282,8 @@ &main_sdhci1 {
|
|||
/* SD card */
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -512,11 +512,16 @@ main_sdhci0: mmc@4f80000 {
|
|||
ti,otap-del-sel-mmc-hs = <0x0>;
|
||||
ti,otap-del-sel-ddr52 = <0x6>;
|
||||
ti,otap-del-sel-hs200 = <0x8>;
|
||||
ti,otap-del-sel-hs400 = <0x0>;
|
||||
ti,otap-del-sel-hs400 = <0x5>;
|
||||
ti,itap-del-sel-legacy = <0x10>;
|
||||
ti,itap-del-sel-mmc-hs = <0xa>;
|
||||
ti,strobe-sel = <0x77>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,trm-icp = <0x8>;
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
|
|
@ -534,7 +539,12 @@ main_sdhci1: mmc@4fb0000 {
|
|||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x5>;
|
||||
ti,otap-del-sel-ddr50 = <0xc>;
|
||||
no-1-8-v;
|
||||
ti,itap-del-sel-legacy = <0x0>;
|
||||
ti,itap-del-sel-sd-hs = <0x0>;
|
||||
ti,itap-del-sel-sdr12 = <0x0>;
|
||||
ti,itap-del-sel-sdr25 = <0x0>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,trm-icp = <0x8>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
|
|
@ -672,6 +682,78 @@ usb0: usb@6000000 {
|
|||
};
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00600000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <145>, <146>, <147>, <148>,
|
||||
<149>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 105 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_gpio2: gpio@610000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00610000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <154>, <155>, <156>, <157>,
|
||||
<158>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 107 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_gpio4: gpio@620000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00620000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <163>, <164>, <165>, <166>,
|
||||
<167>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 109 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_gpio6: gpio@630000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00630000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <172>, <173>, <174>, <175>,
|
||||
<176>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 111 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_r5fss0: r5fss@5c00000 {
|
||||
compatible = "ti,j7200-r5fss";
|
||||
ti,cluster-mode = <1>;
|
||||
|
|
|
|||
|
|
@ -107,6 +107,40 @@ wkup_gpio_intr: interrupt-controller2 {
|
|||
ti,interrupt-ranges = <16 960 16>;
|
||||
};
|
||||
|
||||
wkup_gpio0: gpio@42110000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x42110000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&wkup_gpio_intr>;
|
||||
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <85>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 113 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
wkup_gpio1: gpio@42100000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x42100000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&wkup_gpio_intr>;
|
||||
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
ti,ngpio = <85>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 114 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
mcu_navss: bus@28380000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -269,6 +303,23 @@ hbmc: hyperbus@47034000 {
|
|||
#size-cells = <1>;
|
||||
mux-controls = <&hbmc_mux 0>;
|
||||
};
|
||||
|
||||
ospi0: spi@47040000 {
|
||||
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
||||
reg = <0x0 0x47040000 0x0 0x100>,
|
||||
<0x5 0x00000000 0x1 0x0000000>;
|
||||
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cdns,fifo-depth = <256>;
|
||||
cdns,fifo-width = <4>;
|
||||
cdns,trigger-address = <0x0>;
|
||||
clocks = <&k3_clks 103 0>;
|
||||
assigned-clocks = <&k3_clks 103 0>;
|
||||
assigned-clock-parents = <&k3_clks 103 2>;
|
||||
assigned-clock-rates = <166666666>;
|
||||
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tscadc0: tscadc@40200000 {
|
||||
|
|
|
|||
|
|
@ -100,6 +100,22 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
|
|||
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
|
||||
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
|
||||
J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
|
||||
J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
|
||||
J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
|
||||
J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
|
||||
J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
|
||||
J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
|
||||
J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
|
||||
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
|
||||
J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
|
|
@ -235,3 +251,23 @@ exp_som: gpio@21 {
|
|||
"GPIO_LIN_EN", "CAN_STB";
|
||||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1042,13 +1042,16 @@ main_sdhci0: mmc@4f80000 {
|
|||
assigned-clocks = <&k3_clks 91 1>;
|
||||
assigned-clock-parents = <&k3_clks 91 2>;
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-ddr-1_8v;
|
||||
ti,otap-del-sel-legacy = <0xf>;
|
||||
ti,otap-del-sel-mmc-hs = <0xf>;
|
||||
ti,otap-del-sel-ddr52 = <0x5>;
|
||||
ti,otap-del-sel-hs200 = <0x6>;
|
||||
ti,otap-del-sel-hs400 = <0x0>;
|
||||
ti,itap-del-sel-legacy = <0x10>;
|
||||
ti,itap-del-sel-mmc-hs = <0xa>;
|
||||
ti,itap-del-sel-ddr52 = <0x3>;
|
||||
ti,trm-icp = <0x8>;
|
||||
ti,strobe-sel = <0x77>;
|
||||
dma-coherent;
|
||||
|
|
@ -1069,9 +1072,15 @@ main_sdhci1: mmc@4fb0000 {
|
|||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-ddr50 = <0xc>;
|
||||
ti,itap-del-sel-legacy = <0x0>;
|
||||
ti,itap-del-sel-sd-hs = <0x0>;
|
||||
ti,itap-del-sel-sdr12 = <0x0>;
|
||||
ti,itap-del-sel-sdr25 = <0x0>;
|
||||
ti,itap-del-sel-ddr50 = <0x2>;
|
||||
ti,trm-icp = <0x8>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
dma-coherent;
|
||||
sdhci-caps-mask = <0x2 0x0>;
|
||||
};
|
||||
|
||||
main_sdhci2: mmc@4f98000 {
|
||||
|
|
@ -1089,9 +1098,15 @@ main_sdhci2: mmc@4f98000 {
|
|||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-ddr50 = <0xc>;
|
||||
ti,itap-del-sel-legacy = <0x0>;
|
||||
ti,itap-del-sel-sd-hs = <0x0>;
|
||||
ti,itap-del-sel-sdr12 = <0x0>;
|
||||
ti,itap-del-sel-sdr25 = <0x0>;
|
||||
ti,itap-del-sel-ddr50 = <0x2>;
|
||||
ti,trm-icp = <0x8>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
dma-coherent;
|
||||
sdhci-caps-mask = <0x2 0x0>;
|
||||
};
|
||||
|
||||
usbss0: cdns-usb@4104000 {
|
||||
|
|
@ -1647,4 +1662,266 @@ c71_0: dsp@64800000 {
|
|||
resets = <&k3_reset 15 1>;
|
||||
firmware-name = "j7-c71_0-fw";
|
||||
};
|
||||
|
||||
icssg0: icssg@b000000 {
|
||||
compatible = "ti,j721e-icssg";
|
||||
reg = <0x00 0xb000000 0x00 0x80000>;
|
||||
power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x0b000000 0x100000>;
|
||||
|
||||
icssg0_mem: memories@0 {
|
||||
reg = <0x0 0x2000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x10000 0x10000>;
|
||||
reg-names = "dram0", "dram1",
|
||||
"shrdram2";
|
||||
};
|
||||
|
||||
icssg0_cfg: cfg@26000 {
|
||||
compatible = "ti,pruss-cfg", "syscon";
|
||||
reg = <0x26000 0x200>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x26000 0x2000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
icssg0_coreclk_mux: coreclk-mux@3c {
|
||||
reg = <0x3c>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
|
||||
<&k3_clks 119 1>; /* icssg0_iclk */
|
||||
assigned-clocks = <&icssg0_coreclk_mux>;
|
||||
assigned-clock-parents = <&k3_clks 119 1>;
|
||||
};
|
||||
|
||||
icssg0_iepclk_mux: iepclk-mux@30 {
|
||||
reg = <0x30>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */
|
||||
<&icssg0_coreclk_mux>; /* core_clk */
|
||||
assigned-clocks = <&icssg0_iepclk_mux>;
|
||||
assigned-clock-parents = <&icssg0_coreclk_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
icssg0_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
};
|
||||
|
||||
icssg0_mii_g_rt: mii-g-rt@33000 {
|
||||
compatible = "ti,pruss-mii-g", "syscon";
|
||||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg0_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host_intr0", "host_intr1",
|
||||
"host_intr2", "host_intr3",
|
||||
"host_intr4", "host_intr5",
|
||||
"host_intr6", "host_intr7";
|
||||
};
|
||||
|
||||
pru0_0: pru@34000 {
|
||||
compatible = "ti,j721e-pru";
|
||||
reg = <0x34000 0x3000>,
|
||||
<0x22000 0x100>,
|
||||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-pru0_0-fw";
|
||||
};
|
||||
|
||||
rtu0_0: rtu@4000 {
|
||||
compatible = "ti,j721e-rtu";
|
||||
reg = <0x4000 0x2000>,
|
||||
<0x23000 0x100>,
|
||||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-rtu0_0-fw";
|
||||
};
|
||||
|
||||
tx_pru0_0: txpru@a000 {
|
||||
compatible = "ti,j721e-tx-pru";
|
||||
reg = <0xa000 0x1800>,
|
||||
<0x25000 0x100>,
|
||||
<0x25400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-txpru0_0-fw";
|
||||
};
|
||||
|
||||
pru0_1: pru@38000 {
|
||||
compatible = "ti,j721e-pru";
|
||||
reg = <0x38000 0x3000>,
|
||||
<0x24000 0x100>,
|
||||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-pru0_1-fw";
|
||||
};
|
||||
|
||||
rtu0_1: rtu@6000 {
|
||||
compatible = "ti,j721e-rtu";
|
||||
reg = <0x6000 0x2000>,
|
||||
<0x23800 0x100>,
|
||||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-rtu0_1-fw";
|
||||
};
|
||||
|
||||
tx_pru0_1: txpru@c000 {
|
||||
compatible = "ti,j721e-tx-pru";
|
||||
reg = <0xc000 0x1800>,
|
||||
<0x25800 0x100>,
|
||||
<0x25c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-txpru0_1-fw";
|
||||
};
|
||||
};
|
||||
|
||||
icssg1: icssg@b100000 {
|
||||
compatible = "ti,j721e-icssg";
|
||||
reg = <0x00 0xb100000 0x00 0x80000>;
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x0b100000 0x100000>;
|
||||
|
||||
icssg1_mem: memories@b100000 {
|
||||
reg = <0x0 0x2000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x10000 0x10000>;
|
||||
reg-names = "dram0", "dram1",
|
||||
"shrdram2";
|
||||
};
|
||||
|
||||
icssg1_cfg: cfg@26000 {
|
||||
compatible = "ti,pruss-cfg", "syscon";
|
||||
reg = <0x26000 0x200>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x26000 0x2000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
icssg1_coreclk_mux: coreclk-mux@3c {
|
||||
reg = <0x3c>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
|
||||
<&k3_clks 120 4>; /* icssg1_iclk */
|
||||
assigned-clocks = <&icssg1_coreclk_mux>;
|
||||
assigned-clock-parents = <&k3_clks 120 4>;
|
||||
};
|
||||
|
||||
icssg1_iepclk_mux: iepclk-mux@30 {
|
||||
reg = <0x30>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */
|
||||
<&icssg1_coreclk_mux>; /* core_clk */
|
||||
assigned-clocks = <&icssg1_iepclk_mux>;
|
||||
assigned-clock-parents = <&icssg1_coreclk_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
icssg1_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
};
|
||||
|
||||
icssg1_mii_g_rt: mii-g-rt@33000 {
|
||||
compatible = "ti,pruss-mii-g", "syscon";
|
||||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg1_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host_intr0", "host_intr1",
|
||||
"host_intr2", "host_intr3",
|
||||
"host_intr4", "host_intr5",
|
||||
"host_intr6", "host_intr7";
|
||||
};
|
||||
|
||||
pru1_0: pru@34000 {
|
||||
compatible = "ti,j721e-pru";
|
||||
reg = <0x34000 0x4000>,
|
||||
<0x22000 0x100>,
|
||||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-pru1_0-fw";
|
||||
};
|
||||
|
||||
rtu1_0: rtu@4000 {
|
||||
compatible = "ti,j721e-rtu";
|
||||
reg = <0x4000 0x2000>,
|
||||
<0x23000 0x100>,
|
||||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-rtu1_0-fw";
|
||||
};
|
||||
|
||||
tx_pru1_0: txpru@a000 {
|
||||
compatible = "ti,j721e-tx-pru";
|
||||
reg = <0xa000 0x1800>,
|
||||
<0x25000 0x100>,
|
||||
<0x25400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-txpru1_0-fw";
|
||||
};
|
||||
|
||||
pru1_1: pru@38000 {
|
||||
compatible = "ti,j721e-pru";
|
||||
reg = <0x38000 0x4000>,
|
||||
<0x24000 0x100>,
|
||||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-pru1_1-fw";
|
||||
};
|
||||
|
||||
rtu1_1: rtu@6000 {
|
||||
compatible = "ti,j721e-rtu";
|
||||
reg = <0x6000 0x2000>,
|
||||
<0x23800 0x100>,
|
||||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-rtu1_1-fw";
|
||||
};
|
||||
|
||||
tx_pru1_1: txpru@c000 {
|
||||
compatible = "ti,j721e-tx-pru";
|
||||
reg = <0xc000 0x1800>,
|
||||
<0x25800 0x100>,
|
||||
<0x25c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-txpru1_1-fw";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -180,7 +180,7 @@ fss: fss@47000000 {
|
|||
ranges;
|
||||
|
||||
ospi0: spi@47040000 {
|
||||
compatible = "ti,am654-ospi";
|
||||
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
||||
reg = <0x0 0x47040000 0x0 0x100>,
|
||||
<0x5 0x00000000 0x1 0x0000000>;
|
||||
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -197,7 +197,7 @@ ospi0: spi@47040000 {
|
|||
};
|
||||
|
||||
ospi1: spi@47050000 {
|
||||
compatible = "ti,am654-ospi";
|
||||
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
||||
reg = <0x0 0x47050000 0x0 0x100>,
|
||||
<0x7 0x00000000 0x1 0x00000000>;
|
||||
interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
|
|||
|
|
@ -174,9 +174,9 @@ &ospi0 {
|
|||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <40000000>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* This header provides constants for pinctrl bindings for TI's K3 SoC
|
||||
* family.
|
||||
*
|
||||
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H
|
||||
#define _DT_BINDINGS_PINCTRL_TI_K3_H
|
||||
|
|
@ -35,4 +35,7 @@
|
|||
#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue