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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-21 08:19:28 +00:00
Merge Realview GIC code
This commit is contained in:
commit
4ba9dcbeba
11 changed files with 168 additions and 26 deletions
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@ -14,7 +14,9 @@
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*
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* o There is one CPU Interface per CPU, which sends interrupts sent
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* by the Distributor, and interrupts generated locally, to the
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* associated CPU.
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* associated CPU. The base address of the CPU interface is usually
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* aliased so that the same address points to different chips depending
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* on the CPU it is accessed from.
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*
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* Note that IRQs 0-31 are special - they are local to each CPU.
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* As such, the enable set/clear, pending set/clear and active bit
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@ -31,10 +33,38 @@
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#include <asm/mach/irq.h>
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#include <asm/hardware/gic.h>
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static void __iomem *gic_dist_base;
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static void __iomem *gic_cpu_base;
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static DEFINE_SPINLOCK(irq_controller_lock);
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struct gic_chip_data {
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unsigned int irq_offset;
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void __iomem *dist_base;
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void __iomem *cpu_base;
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};
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#ifndef MAX_GIC_NR
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#define MAX_GIC_NR 1
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#endif
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static struct gic_chip_data gic_data[MAX_GIC_NR];
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static inline void __iomem *gic_dist_base(unsigned int irq)
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{
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struct gic_chip_data *gic_data = get_irq_chip_data(irq);
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return gic_data->dist_base;
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}
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static inline void __iomem *gic_cpu_base(unsigned int irq)
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{
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struct gic_chip_data *gic_data = get_irq_chip_data(irq);
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return gic_data->cpu_base;
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}
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static inline unsigned int gic_irq(unsigned int irq)
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{
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struct gic_chip_data *gic_data = get_irq_chip_data(irq);
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return irq - gic_data->irq_offset;
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}
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/*
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* Routines to acknowledge, disable and enable interrupts
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*
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@ -55,8 +85,8 @@ static void gic_ack_irq(unsigned int irq)
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u32 mask = 1 << (irq % 32);
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spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
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writel(irq, gic_cpu_base + GIC_CPU_EOI);
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writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
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writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
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spin_unlock(&irq_controller_lock);
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}
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@ -65,7 +95,7 @@ static void gic_mask_irq(unsigned int irq)
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u32 mask = 1 << (irq % 32);
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spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
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writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
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spin_unlock(&irq_controller_lock);
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}
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@ -74,14 +104,14 @@ static void gic_unmask_irq(unsigned int irq)
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u32 mask = 1 << (irq % 32);
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spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4);
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writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
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spin_unlock(&irq_controller_lock);
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}
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#ifdef CONFIG_SMP
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static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
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{
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void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3);
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void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
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unsigned int shift = (irq % 4) * 8;
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unsigned int cpu = first_cpu(mask_val);
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u32 val;
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@ -95,6 +125,37 @@ static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
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}
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#endif
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static void fastcall gic_handle_cascade_irq(unsigned int irq,
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struct irq_desc *desc)
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{
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struct gic_chip_data *chip_data = get_irq_data(irq);
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struct irq_chip *chip = get_irq_chip(irq);
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unsigned int cascade_irq;
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unsigned long status;
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/* primary controller ack'ing */
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chip->ack(irq);
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spin_lock(&irq_controller_lock);
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status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
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spin_unlock(&irq_controller_lock);
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cascade_irq = (status & 0x3ff);
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if (cascade_irq > 1020)
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goto out;
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if (cascade_irq < 32 || cascade_irq >= NR_IRQS) {
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do_bad_IRQ(cascade_irq, desc);
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goto out;
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}
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cascade_irq += chip_data->irq_offset;
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generic_handle_irq(cascade_irq);
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out:
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/* primary controller unmasking */
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chip->unmask(irq);
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}
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static struct irq_chip gic_chip = {
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.name = "GIC",
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.ack = gic_ack_irq,
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@ -105,15 +166,29 @@ static struct irq_chip gic_chip = {
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#endif
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};
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void __init gic_dist_init(void __iomem *base)
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void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
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{
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
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BUG();
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set_irq_chained_handler(irq, gic_handle_cascade_irq);
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}
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void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
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unsigned int irq_start)
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{
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unsigned int max_irq, i;
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u32 cpumask = 1 << smp_processor_id();
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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cpumask |= cpumask << 8;
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cpumask |= cpumask << 16;
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gic_dist_base = base;
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gic_data[gic_nr].dist_base = base;
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gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
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writel(0, base + GIC_DIST_CTRL);
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@ -158,8 +233,9 @@ void __init gic_dist_init(void __iomem *base)
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/*
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* Setup the Linux IRQ subsystem.
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*/
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for (i = 29; i < max_irq; i++) {
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for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
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set_irq_chip(i, &gic_chip);
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set_irq_chip_data(i, &gic_data[gic_nr]);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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@ -167,9 +243,13 @@ void __init gic_dist_init(void __iomem *base)
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writel(1, base + GIC_DIST_CTRL);
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}
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void __cpuinit gic_cpu_init(void __iomem *base)
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void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
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{
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gic_cpu_base = base;
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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gic_data[gic_nr].cpu_base = base;
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writel(0xf0, base + GIC_CPU_PRIMASK);
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writel(1, base + GIC_CPU_CTRL);
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}
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@ -179,6 +259,7 @@ void gic_raise_softirq(cpumask_t cpumask, unsigned int irq)
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{
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unsigned long map = *cpus_addr(cpumask);
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writel(map << 16 | irq, gic_dist_base + GIC_DIST_SOFTINT);
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/* this always happens on GIC0 */
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writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
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}
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#endif
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@ -16,4 +16,14 @@ config REALVIEW_MPCORE
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kernel built with this option enabled is not compatible with
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other tiles.
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config REALVIEW_MPCORE_REVB
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bool "Support MPcore RevB tile"
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depends on REALVIEW_MPCORE
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default n
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help
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Enable support for the MPCore RevB tile on the Realview platform.
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Since there are device address differences, a
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kernel built with this option enabled is not compatible with
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other tiles.
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endmenu
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@ -52,7 +52,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
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gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE));
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/*
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* let the primary processor know we're out of the
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@ -57,7 +57,21 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
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.pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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#ifdef CONFIG_REALVIEW_MPCORE
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{
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.virtual = IO_ADDRESS(REALVIEW_GIC1_CPU_BASE),
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.pfn = __phys_to_pfn(REALVIEW_GIC1_CPU_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_GIC1_DIST_BASE),
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.pfn = __phys_to_pfn(REALVIEW_GIC1_DIST_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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#endif
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{
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.virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
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.pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
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.length = SZ_4K,
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#ifdef CONFIG_REALVIEW_MPCORE
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unsigned int pldctrl;
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writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
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pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + 0xd8);
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pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
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pldctrl |= 0x00800000; /* New irq mode */
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writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8);
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writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
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writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
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#endif
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gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE));
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gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
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gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
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gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE));
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#ifdef CONFIG_REALVIEW_MPCORE
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gic_dist_init(1, __io_address(REALVIEW_GIC1_DIST_BASE), 64);
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gic_cpu_init(1, __io_address(REALVIEW_GIC1_CPU_BASE));
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gic_cascade_irq(1, IRQ_EB_IRQ1);
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#endif
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}
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static void __init realview_eb_init(void)
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@ -14,10 +14,13 @@
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/elf.h>
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#include <asm/hardware/arm_scu.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#ifdef CONFIG_SMP
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#include <asm/hardware/arm_scu.h>
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#endif
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#include "proc-macros.S"
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#define D_CACHE_LINE_SIZE 32
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@ -187,8 +190,7 @@ __v6_setup:
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/* Set up the SCU on core 0 only */
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mrc p15, 0, r0, c0, c0, 5 @ CPU core number
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ands r0, r0, #15
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moveq r0, #0x10000000 @ SCU_BASE
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orreq r0, r0, #0x00100000
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ldreq r0, =SCU_BASE
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ldreq r5, [r0, #SCU_CTRL]
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orreq r5, r5, #1
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streq r5, [r0, #SCU_CTRL]
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@ -26,7 +26,7 @@
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#include <asm/arch/platform.h>
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/* macro to get at IO space when running virtually */
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#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
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#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
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#define __io_address(n) __io(IO_ADDRESS(n))
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#endif
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@ -78,6 +78,9 @@
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#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6)
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#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7)
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#define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1)
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#define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2)
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#define IRQMASK_WDOGINT INTMASK_WDOGINT
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#define IRQMASK_SOFTINT INTMASK_SOFTINT
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#define IRQMASK_COMMRx INTMASK_COMMRx
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@ -115,4 +118,4 @@
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#define IRQMASK_ETH INTMASK_ETH
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#define IRQMASK_USB INTMASK_USB
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#define NR_IRQS (IRQ_GIC_START + 64)
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#define NR_IRQS (IRQ_GIC_START + 96)
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@ -207,11 +207,23 @@
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#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
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#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
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#else
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#ifdef CONFIG_REALVIEW_MPCORE_REVB
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#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
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#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_TWD_BASE 0x10100700
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#define REALVIEW_TWD_SIZE 0x00000100
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#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
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#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
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#else
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#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
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#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_TWD_BASE 0x1F000700
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#define REALVIEW_TWD_SIZE 0x00000100
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#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
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#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
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#endif
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#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
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#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
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#endif
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#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
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/* Reserved 0x10090000 - 0x100EFFFF */
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@ -306,7 +318,11 @@
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#define INT_USB 29 /* USB controller */
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#define INT_TSPENINT 30 /* Touchscreen pen */
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#define INT_TSKPADINT 31 /* Touchscreen keypad */
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#else
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#define MAX_GIC_NR 2
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#define INT_AACI 0
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#define INT_TIMERINT0_1 1
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#define INT_TIMERINT2_3 2
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8
include/asm-arm/arch-realview/scu.h
Normal file
8
include/asm-arm/arch-realview/scu.h
Normal file
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@ -0,0 +1,8 @@
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#ifndef __ASMARM_ARCH_SCU_H
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#define __ASMARM_ARCH_SCU_H
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#include <asm/arch/platform.h>
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#define SCU_BASE REALVIEW_MPCORE_SCU_BASE
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#endif
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@ -1,6 +1,8 @@
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#ifndef ASMARM_HARDWARE_ARM_SCU_H
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#define ASMARM_HARDWARE_ARM_SCU_H
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#include <asm/arch/scu.h>
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/*
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* SCU registers
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*/
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@ -33,8 +33,9 @@
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#define GIC_DIST_SOFTINT 0xf00
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#ifndef __ASSEMBLY__
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void gic_dist_init(void __iomem *base);
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void gic_cpu_init(void __iomem *base);
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void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start);
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void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
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void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
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void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
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#endif
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