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[MIPS] SMTC: Reformat to Linux style.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
783b09dc28
commit
4bf42d4272
1 changed files with 29 additions and 29 deletions
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@ -127,7 +127,7 @@ static int __init stlb_disable(char *s)
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static int __init asidmask_set(char *str)
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{
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get_option(&str, &asidmask);
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switch(asidmask) {
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switch (asidmask) {
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case 0x1:
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case 0x3:
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case 0x7:
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@ -249,7 +249,7 @@ void smtc_configure_tlb(void)
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/*
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* Only count if the MMU Type indicated is TLB
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*/
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if(((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) {
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if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) {
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config1val = read_vpe_c0_config1();
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tlbsiz += ((config1val >> 25) & 0x3f) + 1;
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}
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@ -500,7 +500,7 @@ void mipsmt_prepare_cpus(void)
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/* Set up coprocessor affinity CPU mask(s) */
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for (tc = 0; tc < ntc; tc++) {
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if(cpu_data[tc].options & MIPS_CPU_FPU)
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if (cpu_data[tc].options & MIPS_CPU_FPU)
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cpu_set(tc, mt_fpu_cpumask);
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}
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@ -582,8 +582,8 @@ void smtc_init_secondary(void)
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* SMTC init code assigns TCs consdecutively and in ascending order
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* to across available VPEs.
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*/
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if(((read_c0_tcbind() & TCBIND_CURTC) != 0)
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&& ((read_c0_tcbind() & TCBIND_CURVPE)
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if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
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((read_c0_tcbind() & TCBIND_CURVPE)
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!= cpu_data[smp_processor_id() - 1].vpe_id)){
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write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
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}
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@ -757,8 +757,8 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
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write_tc_c0_tchalt(0);
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UNLOCK_CORE_PRA();
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/* Try to reduce redundant timer interrupt messages */
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if(type == SMTC_CLOCK_TICK) {
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if(atomic_postincrement(&ipi_timer_latch[cpu])!=0) {
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if (type == SMTC_CLOCK_TICK) {
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if (atomic_postincrement(&ipi_timer_latch[cpu])!=0){
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smtc_ipi_nq(&freeIPIq, pipi);
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return;
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}
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@ -797,7 +797,7 @@ void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
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* CU bit of Status is indicator that TC was
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* already running on a kernel stack...
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*/
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if(tcstatus & ST0_CU0) {
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if (tcstatus & ST0_CU0) {
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/* Note that this "- 1" is pointer arithmetic */
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kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1;
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} else {
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@ -840,31 +840,31 @@ void ipi_decode(struct pt_regs *regs, struct smtc_ipi *pipi)
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smtc_ipi_nq(&freeIPIq, pipi);
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switch (type_copy) {
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case SMTC_CLOCK_TICK:
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/* Invoke Clock "Interrupt" */
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ipi_timer_latch[dest_copy] = 0;
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case SMTC_CLOCK_TICK:
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/* Invoke Clock "Interrupt" */
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ipi_timer_latch[dest_copy] = 0;
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#ifdef SMTC_IDLE_HOOK_DEBUG
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clock_hang_reported[dest_copy] = 0;
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clock_hang_reported[dest_copy] = 0;
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#endif /* SMTC_IDLE_HOOK_DEBUG */
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local_timer_interrupt(0, NULL, regs);
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local_timer_interrupt(0, NULL, regs);
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break;
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case LINUX_SMP_IPI:
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switch ((int)arg_copy) {
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case SMP_RESCHEDULE_YOURSELF:
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ipi_resched_interrupt(regs);
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break;
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case LINUX_SMP_IPI:
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switch ((int)arg_copy) {
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case SMP_RESCHEDULE_YOURSELF:
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ipi_resched_interrupt(regs);
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break;
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case SMP_CALL_FUNCTION:
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ipi_call_interrupt(regs);
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break;
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default:
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printk("Impossible SMTC IPI Argument 0x%x\n",
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(int)arg_copy);
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break;
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}
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case SMP_CALL_FUNCTION:
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ipi_call_interrupt(regs);
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break;
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default:
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printk("Impossible SMTC IPI Type 0x%x\n", type_copy);
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printk("Impossible SMTC IPI Argument 0x%x\n",
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(int)arg_copy);
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break;
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}
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break;
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default:
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printk("Impossible SMTC IPI Type 0x%x\n", type_copy);
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break;
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}
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}
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@ -879,7 +879,7 @@ void deferred_smtc_ipi(struct pt_regs *regs)
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* Test is not atomic, but much faster than a dequeue,
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* and the vast majority of invocations will have a null queue.
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*/
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if(IPIQ[q].head != NULL) {
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if (IPIQ[q].head != NULL) {
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while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) {
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/* ipi_decode() should be called with interrupts off */
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local_irq_save(flags);
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@ -1254,7 +1254,7 @@ void smtc_flush_tlb_asid(unsigned long asid)
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tlb_read();
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ehb();
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ehi = read_c0_entryhi();
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if((ehi & ASID_MASK) == asid) {
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if ((ehi & ASID_MASK) == asid) {
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/*
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* Invalidate only entries with specified ASID,
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* makiing sure all entries differ.
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