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arm64: dts: renesas: r8a779h0: Add CPU core clocks

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Describe the clocks for the four Cortex-A76 CPU cores.
CA76 CPU cores 0,1,2,3 are clocked by ZC0,ZC1,ZC2,ZC3.

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c64cf6ca1590fa1a36b90a18fd70c831d5b8318e.1706796979.git.geert+renesas@glider.be
This commit is contained in:
Duy Nguyen 2024-02-01 15:19:19 +01:00 committed by Geert Uytterhoeven
parent ad761924be
commit 4c1fd23a22
1 changed files with 4 additions and 0 deletions
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4
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
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@ -43,6 +43,7 @@ a76_0: cpu@0 {
next-level-cache = <&L3_CA76>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>;
};
a76_1: cpu@100 {
@ -53,6 +54,7 @@ a76_1: cpu@100 {
next-level-cache = <&L3_CA76>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>;
};
a76_2: cpu@200 {
@ -63,6 +65,7 @@ a76_2: cpu@200 {
next-level-cache = <&L3_CA76>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>;
};
a76_3: cpu@300 {
@ -73,6 +76,7 @@ a76_3: cpu@300 {
next-level-cache = <&L3_CA76>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>;
};
idle-states {