mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 03:10:12 +00:00
drm/nvc0: import initial vm backend
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
3ee0128140
commit
4c74eb7ff2
7 changed files with 169 additions and 7 deletions
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@ -28,7 +28,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nv10_gpio.o nv50_gpio.o \
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nv50_calc.o \
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nv04_pm.o nv50_pm.o nva3_pm.o \
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nv50_vram.o nv50_vm.o
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nv50_vram.o nv50_vm.o nvc0_vm.o
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nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o
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nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
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@ -909,8 +909,9 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
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break;
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}
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ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size, 12,
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NV_MEM_ACCESS_RW, &vram->bar_vma);
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ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
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vram->page_shift, NV_MEM_ACCESS_RW,
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&vram->bar_vma);
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if (ret)
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return ret;
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@ -69,6 +69,7 @@ struct nouveau_vram {
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struct drm_device *dev;
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struct nouveau_vma bar_vma;
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u8 page_shift;
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struct list_head regions;
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u32 memtype;
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@ -731,6 +731,10 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
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if (ret)
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return ret;
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node->page_shift = 12;
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if (nvbo->vma.node)
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node->page_shift = nvbo->vma.node->type;
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mem->mm_node = node;
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mem->start = node->offset >> PAGE_SHIFT;
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return 0;
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@ -295,7 +295,34 @@ nouveau_vm_new(struct drm_device *dev, u64 offset, u64 length, u64 mm_offset,
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vm->flush = nv50_vm_flush;
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vm->spg_shift = 12;
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vm->lpg_shift = 16;
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pgt_bits = 29;
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block = (1 << pgt_bits);
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if (length < block)
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block = length;
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} else
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if (dev_priv->card_type == NV_C0) {
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vm->map_pgt = nvc0_vm_map_pgt;
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vm->map = nvc0_vm_map;
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vm->map_sg = nvc0_vm_map_sg;
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vm->unmap = nvc0_vm_unmap;
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vm->flush = nvc0_vm_flush;
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vm->spg_shift = 12;
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vm->lpg_shift = 17;
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pgt_bits = 27;
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/* Should be 4096 everywhere, this is a hack that's
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* currently necessary to avoid an elusive bug that
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* causes corruption when mixing small/large pages
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*/
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if (length < (1ULL << 40))
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block = 4096;
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else {
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block = (1 << pgt_bits);
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if (length < block)
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block = length;
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}
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} else {
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kfree(vm);
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return -ENOSYS;
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@ -314,10 +341,6 @@ nouveau_vm_new(struct drm_device *dev, u64 offset, u64 length, u64 mm_offset,
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vm->refcount = 1;
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vm->pgt_bits = pgt_bits - 12;
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block = (1 << pgt_bits);
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if (length < block)
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block = length;
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ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12,
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block >> 12);
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if (ret) {
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@ -100,4 +100,14 @@ void nv50_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
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void nv50_vm_flush(struct nouveau_vm *);
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void nv50_vm_flush_engine(struct drm_device *, int engine);
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/* nvc0_vm.c */
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void nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
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struct nouveau_gpuobj *pgt[2]);
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void nvc0_vm_map(struct nouveau_vma *, struct nouveau_gpuobj *,
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struct nouveau_vram *, u32 pte, u32 cnt, u64 phys);
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void nvc0_vm_map_sg(struct nouveau_vma *, struct nouveau_gpuobj *,
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u32 pte, dma_addr_t *, u32 cnt);
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void nvc0_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
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void nvc0_vm_flush(struct nouveau_vm *);
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#endif
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123
drivers/gpu/drm/nouveau/nvc0_vm.c
Normal file
123
drivers/gpu/drm/nouveau/nvc0_vm.c
Normal file
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@ -0,0 +1,123 @@
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/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_vm.h"
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void
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nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
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struct nouveau_gpuobj *pgt[2])
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{
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u32 pde[2] = { 0, 0 };
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if (pgt[0])
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pde[1] = 0x00000001 | (pgt[0]->vinst >> 8);
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if (pgt[1])
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pde[0] = 0x00000001 | (pgt[1]->vinst >> 8);
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nv_wo32(pgd, (index * 8) + 0, pde[0]);
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nv_wo32(pgd, (index * 8) + 4, pde[1]);
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}
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static inline u64
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nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
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{
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phys >>= 8;
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phys |= 0x00000001; /* present */
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// if (vma->access & NV_MEM_ACCESS_SYS)
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// phys |= 0x00000002;
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phys |= ((u64)target << 32);
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phys |= ((u64)memtype << 36);
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return phys;
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}
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void
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nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
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struct nouveau_vram *mem, u32 pte, u32 cnt, u64 phys)
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{
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u32 next = 1 << (vma->node->type - 8);
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phys = nvc0_vm_addr(vma, phys, mem->memtype, 0);
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pte <<= 3;
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while (cnt--) {
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nv_wo32(pgt, pte + 0, lower_32_bits(phys));
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nv_wo32(pgt, pte + 4, upper_32_bits(phys));
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phys += next;
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pte += 8;
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}
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}
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void
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nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
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u32 pte, dma_addr_t *list, u32 cnt)
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{
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pte <<= 3;
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while (cnt--) {
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u64 phys = nvc0_vm_addr(vma, *list++, 0, 5);
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nv_wo32(pgt, pte + 0, lower_32_bits(phys));
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nv_wo32(pgt, pte + 4, upper_32_bits(phys));
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pte += 8;
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}
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}
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void
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nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
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{
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pte <<= 3;
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while (cnt--) {
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nv_wo32(pgt, pte + 0, 0x00000000);
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nv_wo32(pgt, pte + 4, 0x00000000);
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pte += 8;
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}
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}
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void
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nvc0_vm_flush(struct nouveau_vm *vm)
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{
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struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
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struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
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struct drm_device *dev = vm->dev;
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struct nouveau_vm_pgd *vpgd;
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u32 r100c80, engine;
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pinstmem->flush(vm->dev);
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if (vm == dev_priv->chan_vm)
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engine = 1;
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else
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engine = 5;
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list_for_each_entry(vpgd, &vm->pgd_list, head) {
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r100c80 = nv_rd32(dev, 0x100c80);
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nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8);
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nv_wr32(dev, 0x100cbc, 0x80000000 | engine);
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if (!nv_wait(dev, 0x100c80, 0xffffffff, r100c80))
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NV_ERROR(dev, "vm flush timeout eng %d\n", engine);
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}
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}
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