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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Merge branch 'net-stmmac-dwmac-qcom-ethqos-add-support-for-emac4'
Bartosz Golaszewski says: ==================== net: stmmac: dwmac-qcom-ethqos: add support for EMAC4 Extend the dwmac-qcom-ethqos driver to support EMAC4. While at it: rework the code somewhat. The bindings have been reviewed by DT maintainers. This is a sub-series of [1] with only the patches targetting the net subsystem as they can go in independently. [1] https://lore.kernel.org/lkml/20230617001644.4e093326@kernel.org/T/ ==================== Link: https://lore.kernel.org/r/20230619092402.195578-1-brgl@bgdev.pl Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
commit
4cb13ff143
5 changed files with 226 additions and 76 deletions
|
@ -20,6 +20,7 @@ properties:
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||||||
compatible:
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compatible:
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||||||
enum:
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enum:
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||||||
- qcom,qcs404-ethqos
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- qcom,qcs404-ethqos
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||||||
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- qcom,sa8775p-ethqos
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||||||
- qcom,sc8280xp-ethqos
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- qcom,sc8280xp-ethqos
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||||||
- qcom,sm8150-ethqos
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- qcom,sm8150-ethqos
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||||||
|
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||||||
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@ -32,11 +33,13 @@ properties:
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||||||
- const: rgmii
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- const: rgmii
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||||||
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||||||
interrupts:
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interrupts:
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||||||
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minItems: 1
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items:
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items:
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- description: Combined signal for various interrupt events
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- description: Combined signal for various interrupt events
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||||||
- description: The interrupt that occurs when Rx exits the LPI state
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- description: The interrupt that occurs when Rx exits the LPI state
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||||||
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interrupt-names:
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interrupt-names:
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||||||
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minItems: 1
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items:
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items:
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- const: macirq
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- const: macirq
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- const: eth_lpi
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- const: eth_lpi
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@ -49,11 +52,18 @@ properties:
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||||||
- const: stmmaceth
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- const: stmmaceth
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- const: pclk
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- const: pclk
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- const: ptp_ref
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- const: ptp_ref
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- const: rgmii
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- enum:
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- rgmii
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- phyaux
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iommus:
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iommus:
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||||||
maxItems: 1
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maxItems: 1
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||||||
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phys: true
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phy-names:
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const: serdes
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required:
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required:
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- compatible
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- compatible
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- clocks
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- clocks
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|
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@ -67,6 +67,7 @@ properties:
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||||||
- loongson,ls2k-dwmac
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- loongson,ls2k-dwmac
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||||||
- loongson,ls7a-dwmac
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- loongson,ls7a-dwmac
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||||||
- qcom,qcs404-ethqos
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- qcom,qcs404-ethqos
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||||||
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- qcom,sa8775p-ethqos
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||||||
- qcom,sc8280xp-ethqos
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- qcom,sc8280xp-ethqos
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||||||
- qcom,sm8150-ethqos
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- qcom,sm8150-ethqos
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- renesas,r9a06g032-gmac
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- renesas,r9a06g032-gmac
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@ -582,6 +583,7 @@ allOf:
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- ingenic,x1600-mac
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- ingenic,x1600-mac
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- ingenic,x1830-mac
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- ingenic,x1830-mac
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- ingenic,x2000-mac
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- ingenic,x2000-mac
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- qcom,sa8775p-ethqos
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- qcom,sc8280xp-ethqos
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- qcom,sc8280xp-ethqos
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- snps,dwmac-3.50a
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- snps,dwmac-3.50a
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- snps,dwmac-4.10a
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- snps,dwmac-4.10a
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||||||
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@ -638,6 +640,7 @@ allOf:
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||||||
- ingenic,x1830-mac
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- ingenic,x1830-mac
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||||||
- ingenic,x2000-mac
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- ingenic,x2000-mac
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||||||
- qcom,qcs404-ethqos
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- qcom,qcs404-ethqos
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||||||
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- qcom,sa8775p-ethqos
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||||||
- qcom,sc8280xp-ethqos
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- qcom,sc8280xp-ethqos
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||||||
- qcom,sm8150-ethqos
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- qcom,sm8150-ethqos
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||||||
- snps,dwmac-4.00
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- snps,dwmac-4.00
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||||||
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@ -6,6 +6,9 @@
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#include <linux/of_device.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <linux/phy.h>
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#include <linux/phy/phy.h>
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#include <linux/property.h>
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#include "stmmac.h"
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#include "stmmac.h"
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#include "stmmac_platform.h"
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#include "stmmac_platform.h"
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@ -72,6 +75,10 @@
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#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6)
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#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6)
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#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
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#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
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/* MAC_CTRL_REG bits */
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#define ETHQOS_MAC_CTRL_SPEED_MODE BIT(14)
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#define ETHQOS_MAC_CTRL_PORT_SEL BIT(15)
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struct ethqos_emac_por {
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struct ethqos_emac_por {
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unsigned int offset;
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unsigned int offset;
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unsigned int value;
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unsigned int value;
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@ -81,22 +88,28 @@ struct ethqos_emac_driver_data {
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const struct ethqos_emac_por *por;
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const struct ethqos_emac_por *por;
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unsigned int num_por;
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unsigned int num_por;
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bool rgmii_config_loopback_en;
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bool rgmii_config_loopback_en;
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bool has_emac3;
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bool has_emac_ge_3;
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const char *link_clk_name;
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bool has_integrated_pcs;
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struct dwmac4_addrs dwmac4_addrs;
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struct dwmac4_addrs dwmac4_addrs;
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};
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};
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struct qcom_ethqos {
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struct qcom_ethqos {
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struct platform_device *pdev;
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struct platform_device *pdev;
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void __iomem *rgmii_base;
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void __iomem *rgmii_base;
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void __iomem *mac_base;
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int (*configure_func)(struct qcom_ethqos *ethqos);
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unsigned int rgmii_clk_rate;
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unsigned int link_clk_rate;
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struct clk *rgmii_clk;
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struct clk *link_clk;
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struct phy *serdes_phy;
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unsigned int speed;
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unsigned int speed;
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int phy_mode;
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const struct ethqos_emac_por *por;
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const struct ethqos_emac_por *por;
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unsigned int num_por;
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unsigned int num_por;
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bool rgmii_config_loopback_en;
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bool rgmii_config_loopback_en;
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bool has_emac3;
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bool has_emac_ge_3;
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};
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};
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static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
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static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
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@ -115,7 +128,7 @@ static void rgmii_updatel(struct qcom_ethqos *ethqos,
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{
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{
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unsigned int temp;
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unsigned int temp;
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temp = rgmii_readl(ethqos, offset);
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temp = rgmii_readl(ethqos, offset);
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temp = (temp & ~(mask)) | val;
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temp = (temp & ~(mask)) | val;
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rgmii_writel(ethqos, temp, offset);
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rgmii_writel(ethqos, temp, offset);
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}
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}
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@ -123,25 +136,26 @@ static void rgmii_updatel(struct qcom_ethqos *ethqos,
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static void rgmii_dump(void *priv)
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static void rgmii_dump(void *priv)
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{
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{
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struct qcom_ethqos *ethqos = priv;
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struct qcom_ethqos *ethqos = priv;
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||||||
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struct device *dev = ðqos->pdev->dev;
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||||||
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dev_dbg(ðqos->pdev->dev, "Rgmii register dump\n");
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dev_dbg(dev, "Rgmii register dump\n");
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dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n",
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dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n",
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rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
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rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
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dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
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dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
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rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
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rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
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dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
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dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
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rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
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rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
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dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
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dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
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rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
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rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
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dev_dbg(ðqos->pdev->dev, "SDC4_STATUS: %x\n",
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dev_dbg(dev, "SDC4_STATUS: %x\n",
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rgmii_readl(ethqos, SDC4_STATUS));
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rgmii_readl(ethqos, SDC4_STATUS));
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dev_dbg(ðqos->pdev->dev, "SDCC_USR_CTL: %x\n",
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dev_dbg(dev, "SDCC_USR_CTL: %x\n",
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rgmii_readl(ethqos, SDCC_USR_CTL));
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rgmii_readl(ethqos, SDCC_USR_CTL));
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dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
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dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
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rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
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rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
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dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
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dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
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rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
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rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
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dev_dbg(ðqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
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dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
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rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
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rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
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}
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}
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@ -151,23 +165,23 @@ static void rgmii_dump(void *priv)
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#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL)
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#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL)
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static void
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static void
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ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed)
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ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed)
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{
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{
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switch (speed) {
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switch (speed) {
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case SPEED_1000:
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case SPEED_1000:
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ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ;
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ethqos->link_clk_rate = RGMII_1000_NOM_CLK_FREQ;
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break;
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break;
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case SPEED_100:
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case SPEED_100:
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ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
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ethqos->link_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
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break;
|
break;
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case SPEED_10:
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case SPEED_10:
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ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
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ethqos->link_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
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break;
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break;
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}
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}
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||||||
|
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||||||
clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate);
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clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
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||||||
}
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}
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||||||
|
|
||||||
static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
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static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
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||||||
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@ -189,7 +203,7 @@ static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
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||||||
.por = emac_v2_3_0_por,
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.por = emac_v2_3_0_por,
|
||||||
.num_por = ARRAY_SIZE(emac_v2_3_0_por),
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.num_por = ARRAY_SIZE(emac_v2_3_0_por),
|
||||||
.rgmii_config_loopback_en = true,
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.rgmii_config_loopback_en = true,
|
||||||
.has_emac3 = false,
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.has_emac_ge_3 = false,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct ethqos_emac_por emac_v2_1_0_por[] = {
|
static const struct ethqos_emac_por emac_v2_1_0_por[] = {
|
||||||
|
@ -205,7 +219,7 @@ static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
|
||||||
.por = emac_v2_1_0_por,
|
.por = emac_v2_1_0_por,
|
||||||
.num_por = ARRAY_SIZE(emac_v2_1_0_por),
|
.num_por = ARRAY_SIZE(emac_v2_1_0_por),
|
||||||
.rgmii_config_loopback_en = false,
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.rgmii_config_loopback_en = false,
|
||||||
.has_emac3 = false,
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.has_emac_ge_3 = false,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct ethqos_emac_por emac_v3_0_0_por[] = {
|
static const struct ethqos_emac_por emac_v3_0_0_por[] = {
|
||||||
|
@ -221,7 +235,41 @@ static const struct ethqos_emac_driver_data emac_v3_0_0_data = {
|
||||||
.por = emac_v3_0_0_por,
|
.por = emac_v3_0_0_por,
|
||||||
.num_por = ARRAY_SIZE(emac_v3_0_0_por),
|
.num_por = ARRAY_SIZE(emac_v3_0_0_por),
|
||||||
.rgmii_config_loopback_en = false,
|
.rgmii_config_loopback_en = false,
|
||||||
.has_emac3 = true,
|
.has_emac_ge_3 = true,
|
||||||
|
.dwmac4_addrs = {
|
||||||
|
.dma_chan = 0x00008100,
|
||||||
|
.dma_chan_offset = 0x1000,
|
||||||
|
.mtl_chan = 0x00008000,
|
||||||
|
.mtl_chan_offset = 0x1000,
|
||||||
|
.mtl_ets_ctrl = 0x00008010,
|
||||||
|
.mtl_ets_ctrl_offset = 0x1000,
|
||||||
|
.mtl_txq_weight = 0x00008018,
|
||||||
|
.mtl_txq_weight_offset = 0x1000,
|
||||||
|
.mtl_send_slp_cred = 0x0000801c,
|
||||||
|
.mtl_send_slp_cred_offset = 0x1000,
|
||||||
|
.mtl_high_cred = 0x00008020,
|
||||||
|
.mtl_high_cred_offset = 0x1000,
|
||||||
|
.mtl_low_cred = 0x00008024,
|
||||||
|
.mtl_low_cred_offset = 0x1000,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct ethqos_emac_por emac_v4_0_0_por[] = {
|
||||||
|
{ .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 },
|
||||||
|
{ .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c },
|
||||||
|
{ .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
|
||||||
|
{ .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
|
||||||
|
{ .offset = SDCC_USR_CTL, .value = 0x00010800 },
|
||||||
|
{ .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct ethqos_emac_driver_data emac_v4_0_0_data = {
|
||||||
|
.por = emac_v4_0_0_por,
|
||||||
|
.num_por = ARRAY_SIZE(emac_v3_0_0_por),
|
||||||
|
.rgmii_config_loopback_en = false,
|
||||||
|
.has_emac_ge_3 = true,
|
||||||
|
.link_clk_name = "phyaux",
|
||||||
|
.has_integrated_pcs = true,
|
||||||
.dwmac4_addrs = {
|
.dwmac4_addrs = {
|
||||||
.dma_chan = 0x00008100,
|
.dma_chan = 0x00008100,
|
||||||
.dma_chan_offset = 0x1000,
|
.dma_chan_offset = 0x1000,
|
||||||
|
@ -242,6 +290,7 @@ static const struct ethqos_emac_driver_data emac_v3_0_0_data = {
|
||||||
|
|
||||||
static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
|
static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
|
||||||
{
|
{
|
||||||
|
struct device *dev = ðqos->pdev->dev;
|
||||||
unsigned int val;
|
unsigned int val;
|
||||||
int retry = 1000;
|
int retry = 1000;
|
||||||
|
|
||||||
|
@ -261,7 +310,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
|
||||||
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
|
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
|
||||||
SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
|
SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
|
||||||
|
|
||||||
if (!ethqos->has_emac3) {
|
if (!ethqos->has_emac_ge_3) {
|
||||||
rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
|
rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
|
||||||
0, SDCC_HC_REG_DLL_CONFIG);
|
0, SDCC_HC_REG_DLL_CONFIG);
|
||||||
|
|
||||||
|
@ -279,7 +328,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
|
||||||
retry--;
|
retry--;
|
||||||
} while (retry > 0);
|
} while (retry > 0);
|
||||||
if (!retry)
|
if (!retry)
|
||||||
dev_err(ðqos->pdev->dev, "Clear CK_OUT_EN timedout\n");
|
dev_err(dev, "Clear CK_OUT_EN timedout\n");
|
||||||
|
|
||||||
/* Set CK_OUT_EN */
|
/* Set CK_OUT_EN */
|
||||||
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
|
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
|
||||||
|
@ -296,13 +345,13 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
|
||||||
retry--;
|
retry--;
|
||||||
} while (retry > 0);
|
} while (retry > 0);
|
||||||
if (!retry)
|
if (!retry)
|
||||||
dev_err(ðqos->pdev->dev, "Set CK_OUT_EN timedout\n");
|
dev_err(dev, "Set CK_OUT_EN timedout\n");
|
||||||
|
|
||||||
/* Set DDR_CAL_EN */
|
/* Set DDR_CAL_EN */
|
||||||
rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
|
rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
|
||||||
SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
|
SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
|
||||||
|
|
||||||
if (!ethqos->has_emac3) {
|
if (!ethqos->has_emac_ge_3) {
|
||||||
rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
|
rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
|
||||||
0, SDCC_HC_REG_DLL_CONFIG2);
|
0, SDCC_HC_REG_DLL_CONFIG2);
|
||||||
|
|
||||||
|
@ -322,14 +371,13 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
|
||||||
|
|
||||||
static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
|
static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
|
||||||
{
|
{
|
||||||
|
struct device *dev = ðqos->pdev->dev;
|
||||||
int phase_shift;
|
int phase_shift;
|
||||||
int phy_mode;
|
|
||||||
int loopback;
|
int loopback;
|
||||||
|
|
||||||
/* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */
|
/* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */
|
||||||
phy_mode = device_get_phy_mode(ðqos->pdev->dev);
|
if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
|
||||||
if (phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
|
ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
|
||||||
phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
|
|
||||||
phase_shift = 0;
|
phase_shift = 0;
|
||||||
else
|
else
|
||||||
phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN;
|
phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN;
|
||||||
|
@ -373,7 +421,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
|
||||||
/* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
|
/* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
|
||||||
* in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns
|
* in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns
|
||||||
*/
|
*/
|
||||||
if (ethqos->has_emac3) {
|
if (ethqos->has_emac_ge_3) {
|
||||||
/* 0.9 ns */
|
/* 0.9 ns */
|
||||||
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
|
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
|
||||||
115, SDCC_HC_REG_DDR_CONFIG);
|
115, SDCC_HC_REG_DDR_CONFIG);
|
||||||
|
@ -408,7 +456,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
|
||||||
rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
|
rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
|
||||||
0, RGMII_IO_MACRO_CONFIG2);
|
0, RGMII_IO_MACRO_CONFIG2);
|
||||||
|
|
||||||
if (ethqos->has_emac3)
|
if (ethqos->has_emac_ge_3)
|
||||||
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
|
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
|
||||||
RGMII_CONFIG2_RX_PROG_SWAP,
|
RGMII_CONFIG2_RX_PROG_SWAP,
|
||||||
RGMII_IO_MACRO_CONFIG2);
|
RGMII_IO_MACRO_CONFIG2);
|
||||||
|
@ -448,7 +496,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
|
||||||
RGMII_IO_MACRO_CONFIG);
|
RGMII_IO_MACRO_CONFIG);
|
||||||
rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
|
rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
|
||||||
0, RGMII_IO_MACRO_CONFIG2);
|
0, RGMII_IO_MACRO_CONFIG2);
|
||||||
if (ethqos->has_emac3)
|
if (ethqos->has_emac_ge_3)
|
||||||
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
|
rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
|
||||||
RGMII_CONFIG2_RX_PROG_SWAP,
|
RGMII_CONFIG2_RX_PROG_SWAP,
|
||||||
RGMII_IO_MACRO_CONFIG2);
|
RGMII_IO_MACRO_CONFIG2);
|
||||||
|
@ -468,16 +516,16 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
|
||||||
loopback, RGMII_IO_MACRO_CONFIG);
|
loopback, RGMII_IO_MACRO_CONFIG);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
dev_err(ðqos->pdev->dev,
|
dev_err(dev, "Invalid speed %d\n", ethqos->speed);
|
||||||
"Invalid speed %d\n", ethqos->speed);
|
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int ethqos_configure(struct qcom_ethqos *ethqos)
|
static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
|
||||||
{
|
{
|
||||||
|
struct device *dev = ðqos->pdev->dev;
|
||||||
volatile unsigned int dll_lock;
|
volatile unsigned int dll_lock;
|
||||||
unsigned int i, retry = 1000;
|
unsigned int i, retry = 1000;
|
||||||
|
|
||||||
|
@ -497,7 +545,7 @@ static int ethqos_configure(struct qcom_ethqos *ethqos)
|
||||||
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
|
rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
|
||||||
SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
|
SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
|
||||||
|
|
||||||
if (ethqos->has_emac3) {
|
if (ethqos->has_emac_ge_3) {
|
||||||
if (ethqos->speed == SPEED_1000) {
|
if (ethqos->speed == SPEED_1000) {
|
||||||
rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL);
|
rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL);
|
||||||
rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL);
|
rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL);
|
||||||
|
@ -527,7 +575,7 @@ static int ethqos_configure(struct qcom_ethqos *ethqos)
|
||||||
SDCC_HC_REG_DLL_CONFIG);
|
SDCC_HC_REG_DLL_CONFIG);
|
||||||
|
|
||||||
/* Set USR_CTL bit 26 with mask of 3 bits */
|
/* Set USR_CTL bit 26 with mask of 3 bits */
|
||||||
if (!ethqos->has_emac3)
|
if (!ethqos->has_emac_ge_3)
|
||||||
rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),
|
rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),
|
||||||
SDCC_USR_CTL);
|
SDCC_USR_CTL);
|
||||||
|
|
||||||
|
@ -540,8 +588,7 @@ static int ethqos_configure(struct qcom_ethqos *ethqos)
|
||||||
retry--;
|
retry--;
|
||||||
} while (retry > 0);
|
} while (retry > 0);
|
||||||
if (!retry)
|
if (!retry)
|
||||||
dev_err(ðqos->pdev->dev,
|
dev_err(dev, "Timeout while waiting for DLL lock\n");
|
||||||
"Timeout while waiting for DLL lock\n");
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (ethqos->speed == SPEED_1000)
|
if (ethqos->speed == SPEED_1000)
|
||||||
|
@ -552,24 +599,80 @@ static int ethqos_configure(struct qcom_ethqos *ethqos)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
|
||||||
|
{
|
||||||
|
int val;
|
||||||
|
|
||||||
|
val = readl(ethqos->mac_base + MAC_CTRL_REG);
|
||||||
|
|
||||||
|
switch (ethqos->speed) {
|
||||||
|
case SPEED_1000:
|
||||||
|
val &= ~ETHQOS_MAC_CTRL_PORT_SEL;
|
||||||
|
rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
|
||||||
|
RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
|
||||||
|
RGMII_IO_MACRO_CONFIG2);
|
||||||
|
break;
|
||||||
|
case SPEED_100:
|
||||||
|
val |= ETHQOS_MAC_CTRL_PORT_SEL | ETHQOS_MAC_CTRL_SPEED_MODE;
|
||||||
|
break;
|
||||||
|
case SPEED_10:
|
||||||
|
val |= ETHQOS_MAC_CTRL_PORT_SEL;
|
||||||
|
val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
writel(val, ethqos->mac_base + MAC_CTRL_REG);
|
||||||
|
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ethqos_configure(struct qcom_ethqos *ethqos)
|
||||||
|
{
|
||||||
|
return ethqos->configure_func(ethqos);
|
||||||
|
}
|
||||||
|
|
||||||
static void ethqos_fix_mac_speed(void *priv, unsigned int speed)
|
static void ethqos_fix_mac_speed(void *priv, unsigned int speed)
|
||||||
{
|
{
|
||||||
struct qcom_ethqos *ethqos = priv;
|
struct qcom_ethqos *ethqos = priv;
|
||||||
|
|
||||||
ethqos->speed = speed;
|
ethqos->speed = speed;
|
||||||
ethqos_update_rgmii_clk(ethqos, speed);
|
ethqos_update_link_clk(ethqos, speed);
|
||||||
ethqos_configure(ethqos);
|
ethqos_configure(ethqos);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv)
|
||||||
|
{
|
||||||
|
struct qcom_ethqos *ethqos = priv;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = phy_init(ethqos->serdes_phy);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = phy_power_on(ethqos->serdes_phy);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return phy_set_speed(ethqos->serdes_phy, ethqos->speed);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv)
|
||||||
|
{
|
||||||
|
struct qcom_ethqos *ethqos = priv;
|
||||||
|
|
||||||
|
phy_power_off(ethqos->serdes_phy);
|
||||||
|
phy_exit(ethqos->serdes_phy);
|
||||||
|
}
|
||||||
|
|
||||||
static int ethqos_clks_config(void *priv, bool enabled)
|
static int ethqos_clks_config(void *priv, bool enabled)
|
||||||
{
|
{
|
||||||
struct qcom_ethqos *ethqos = priv;
|
struct qcom_ethqos *ethqos = priv;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
||||||
if (enabled) {
|
if (enabled) {
|
||||||
ret = clk_prepare_enable(ethqos->rgmii_clk);
|
ret = clk_prepare_enable(ethqos->link_clk);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
dev_err(ðqos->pdev->dev, "rgmii_clk enable failed\n");
|
dev_err(ðqos->pdev->dev, "link_clk enable failed\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -580,18 +683,24 @@ static int ethqos_clks_config(void *priv, bool enabled)
|
||||||
*/
|
*/
|
||||||
ethqos_set_func_clk_en(ethqos);
|
ethqos_set_func_clk_en(ethqos);
|
||||||
} else {
|
} else {
|
||||||
clk_disable_unprepare(ethqos->rgmii_clk);
|
clk_disable_unprepare(ethqos->link_clk);
|
||||||
}
|
}
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void ethqos_clks_disable(void *data)
|
||||||
|
{
|
||||||
|
ethqos_clks_config(data, false);
|
||||||
|
}
|
||||||
|
|
||||||
static int qcom_ethqos_probe(struct platform_device *pdev)
|
static int qcom_ethqos_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct device_node *np = pdev->dev.of_node;
|
struct device_node *np = pdev->dev.of_node;
|
||||||
|
const struct ethqos_emac_driver_data *data;
|
||||||
struct plat_stmmacenet_data *plat_dat;
|
struct plat_stmmacenet_data *plat_dat;
|
||||||
struct stmmac_resources stmmac_res;
|
struct stmmac_resources stmmac_res;
|
||||||
const struct ethqos_emac_driver_data *data;
|
struct device *dev = &pdev->dev;
|
||||||
struct qcom_ethqos *ethqos;
|
struct qcom_ethqos *ethqos;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
|
@ -601,81 +710,108 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
|
||||||
|
|
||||||
plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
|
plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
|
||||||
if (IS_ERR(plat_dat)) {
|
if (IS_ERR(plat_dat)) {
|
||||||
dev_err(&pdev->dev, "dt configuration failed\n");
|
dev_err(dev, "dt configuration failed\n");
|
||||||
return PTR_ERR(plat_dat);
|
return PTR_ERR(plat_dat);
|
||||||
}
|
}
|
||||||
|
|
||||||
plat_dat->clks_config = ethqos_clks_config;
|
plat_dat->clks_config = ethqos_clks_config;
|
||||||
|
|
||||||
ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL);
|
ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL);
|
||||||
if (!ethqos) {
|
if (!ethqos) {
|
||||||
ret = -ENOMEM;
|
ret = -ENOMEM;
|
||||||
goto err_mem;
|
goto out_config_dt;
|
||||||
|
}
|
||||||
|
|
||||||
|
ethqos->phy_mode = device_get_phy_mode(dev);
|
||||||
|
switch (ethqos->phy_mode) {
|
||||||
|
case PHY_INTERFACE_MODE_RGMII:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||||
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||||
|
ethqos->configure_func = ethqos_configure_rgmii;
|
||||||
|
break;
|
||||||
|
case PHY_INTERFACE_MODE_SGMII:
|
||||||
|
ethqos->configure_func = ethqos_configure_sgmii;
|
||||||
|
break;
|
||||||
|
case -ENODEV:
|
||||||
|
ret = -ENODEV;
|
||||||
|
goto out_config_dt;
|
||||||
|
default:
|
||||||
|
ret = -EINVAL;
|
||||||
|
goto out_config_dt;
|
||||||
}
|
}
|
||||||
|
|
||||||
ethqos->pdev = pdev;
|
ethqos->pdev = pdev;
|
||||||
ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
|
ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
|
||||||
if (IS_ERR(ethqos->rgmii_base)) {
|
if (IS_ERR(ethqos->rgmii_base)) {
|
||||||
ret = PTR_ERR(ethqos->rgmii_base);
|
ret = PTR_ERR(ethqos->rgmii_base);
|
||||||
goto err_mem;
|
goto out_config_dt;
|
||||||
}
|
}
|
||||||
|
|
||||||
data = of_device_get_match_data(&pdev->dev);
|
ethqos->mac_base = stmmac_res.addr;
|
||||||
|
|
||||||
|
data = of_device_get_match_data(dev);
|
||||||
ethqos->por = data->por;
|
ethqos->por = data->por;
|
||||||
ethqos->num_por = data->num_por;
|
ethqos->num_por = data->num_por;
|
||||||
ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
|
ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
|
||||||
ethqos->has_emac3 = data->has_emac3;
|
ethqos->has_emac_ge_3 = data->has_emac_ge_3;
|
||||||
|
|
||||||
ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii");
|
ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");
|
||||||
if (IS_ERR(ethqos->rgmii_clk)) {
|
if (IS_ERR(ethqos->link_clk)) {
|
||||||
ret = PTR_ERR(ethqos->rgmii_clk);
|
ret = PTR_ERR(ethqos->link_clk);
|
||||||
goto err_mem;
|
goto out_config_dt;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = ethqos_clks_config(ethqos, true);
|
ret = ethqos_clks_config(ethqos, true);
|
||||||
if (ret)
|
if (ret)
|
||||||
goto err_mem;
|
goto out_config_dt;
|
||||||
|
|
||||||
|
ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos);
|
||||||
|
if (ret)
|
||||||
|
goto out_config_dt;
|
||||||
|
|
||||||
|
ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes");
|
||||||
|
if (IS_ERR(ethqos->serdes_phy)) {
|
||||||
|
ret = PTR_ERR(ethqos->serdes_phy);
|
||||||
|
goto out_config_dt;
|
||||||
|
}
|
||||||
|
|
||||||
ethqos->speed = SPEED_1000;
|
ethqos->speed = SPEED_1000;
|
||||||
ethqos_update_rgmii_clk(ethqos, SPEED_1000);
|
ethqos_update_link_clk(ethqos, SPEED_1000);
|
||||||
ethqos_set_func_clk_en(ethqos);
|
ethqos_set_func_clk_en(ethqos);
|
||||||
|
|
||||||
plat_dat->bsp_priv = ethqos;
|
plat_dat->bsp_priv = ethqos;
|
||||||
plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
|
plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
|
||||||
plat_dat->dump_debug_regs = rgmii_dump;
|
plat_dat->dump_debug_regs = rgmii_dump;
|
||||||
plat_dat->has_gmac4 = 1;
|
plat_dat->has_gmac4 = 1;
|
||||||
if (ethqos->has_emac3)
|
if (ethqos->has_emac_ge_3)
|
||||||
plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
|
plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
|
||||||
plat_dat->pmt = 1;
|
plat_dat->pmt = 1;
|
||||||
plat_dat->tso_en = of_property_read_bool(np, "snps,tso");
|
plat_dat->tso_en = of_property_read_bool(np, "snps,tso");
|
||||||
if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
|
if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
|
||||||
plat_dat->rx_clk_runs_in_lpi = 1;
|
plat_dat->rx_clk_runs_in_lpi = 1;
|
||||||
|
plat_dat->has_integrated_pcs = data->has_integrated_pcs;
|
||||||
|
|
||||||
ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
|
if (ethqos->serdes_phy) {
|
||||||
|
plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup;
|
||||||
|
plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = stmmac_dvr_probe(dev, plat_dat, &stmmac_res);
|
||||||
if (ret)
|
if (ret)
|
||||||
goto err_clk;
|
goto out_config_dt;
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
err_clk:
|
out_config_dt:
|
||||||
ethqos_clks_config(ethqos, false);
|
|
||||||
|
|
||||||
err_mem:
|
|
||||||
stmmac_remove_config_dt(pdev, plat_dat);
|
stmmac_remove_config_dt(pdev, plat_dat);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void qcom_ethqos_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct qcom_ethqos *ethqos = get_stmmac_bsp_priv(&pdev->dev);
|
|
||||||
|
|
||||||
stmmac_pltfr_remove(pdev);
|
|
||||||
ethqos_clks_config(ethqos, false);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct of_device_id qcom_ethqos_match[] = {
|
static const struct of_device_id qcom_ethqos_match[] = {
|
||||||
{ .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
|
{ .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
|
||||||
|
{ .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data},
|
||||||
{ .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data},
|
{ .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data},
|
||||||
{ .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
|
{ .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
|
||||||
{ }
|
{ }
|
||||||
|
@ -684,7 +820,7 @@ MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
|
||||||
|
|
||||||
static struct platform_driver qcom_ethqos_driver = {
|
static struct platform_driver qcom_ethqos_driver = {
|
||||||
.probe = qcom_ethqos_probe,
|
.probe = qcom_ethqos_probe,
|
||||||
.remove_new = qcom_ethqos_remove,
|
.remove_new = stmmac_pltfr_remove,
|
||||||
.driver = {
|
.driver = {
|
||||||
.name = "qcom-ethqos",
|
.name = "qcom-ethqos",
|
||||||
.pm = &stmmac_pltfr_pm_ops,
|
.pm = &stmmac_pltfr_pm_ops,
|
||||||
|
|
|
@ -5798,7 +5798,7 @@ static void stmmac_common_interrupt(struct stmmac_priv *priv)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* PCS link status */
|
/* PCS link status */
|
||||||
if (priv->hw->pcs) {
|
if (priv->hw->pcs && !priv->plat->has_integrated_pcs) {
|
||||||
if (priv->xstats.pcs_link)
|
if (priv->xstats.pcs_link)
|
||||||
netif_carrier_on(priv->dev);
|
netif_carrier_on(priv->dev);
|
||||||
else
|
else
|
||||||
|
|
|
@ -293,5 +293,6 @@ struct plat_stmmacenet_data {
|
||||||
bool sph_disable;
|
bool sph_disable;
|
||||||
bool serdes_up_after_phy_linkup;
|
bool serdes_up_after_phy_linkup;
|
||||||
const struct dwmac4_addrs *dwmac4_addrs;
|
const struct dwmac4_addrs *dwmac4_addrs;
|
||||||
|
bool has_integrated_pcs;
|
||||||
};
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in a new issue