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powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_SHIFT_BUG
This flag was used to support the PHB4 LSIs on P9 DD1 and we have stopped supporting this CPU when DD2 came out. See skiboot commit: https://github.com/open-power/skiboot/commit/0b0d15e3c170 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20201210171450.1933725-9-clg@kaod.org
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parent
7b3b3de3b0
commit
4cc0e36df2
6 changed files with 2 additions and 19 deletions
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@ -1091,7 +1091,7 @@ enum {
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OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001,
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OPAL_XIVE_IRQ_STORE_EOI = 0x00000002,
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OPAL_XIVE_IRQ_LSI = 0x00000004,
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OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008,
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OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, /* P9 DD1.0 workaround */
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OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010,
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OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
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};
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@ -60,7 +60,7 @@ struct xive_irq_data {
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};
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#define XIVE_IRQ_FLAG_STORE_EOI 0x01
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#define XIVE_IRQ_FLAG_LSI 0x02
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#define XIVE_IRQ_FLAG_SHIFT_BUG 0x04
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/* #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04 */ /* P9 DD1.0 workaround */
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#define XIVE_IRQ_FLAG_MASK_FW 0x08
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#define XIVE_IRQ_FLAG_EOI_FW 0x10
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#define XIVE_IRQ_FLAG_H_INT_ESB 0x20
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@ -37,9 +37,6 @@ static u8 xive_vm_esb_load(struct xive_irq_data *xd, u32 offset)
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* ordering.
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*/
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if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
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offset |= offset << 4;
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val = in_be64(xd->eoi_mmio + offset);
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return (u8)val;
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}
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@ -61,9 +61,6 @@ static u8 GLUE(X_PFX,esb_load)(struct xive_irq_data *xd, u32 offset)
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if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
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offset |= XIVE_ESB_LD_ST_MO;
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if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
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offset |= offset << 4;
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val =__x_readq(__x_eoi_page(xd) + offset);
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#ifdef __LITTLE_ENDIAN__
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val >>= 64-8;
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@ -200,10 +200,6 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
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if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
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offset |= XIVE_ESB_LD_ST_MO;
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/* Handle HW errata */
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if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
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offset |= offset << 4;
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if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
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val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
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else
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@ -214,10 +210,6 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
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static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
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{
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/* Handle HW errata */
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if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
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offset |= offset << 4;
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if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
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xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
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else
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@ -1312,7 +1304,6 @@ static const struct {
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} xive_irq_flags[] = {
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{ XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
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{ XIVE_IRQ_FLAG_LSI, "LSI" },
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{ XIVE_IRQ_FLAG_SHIFT_BUG, "SHIFT_BUG" },
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{ XIVE_IRQ_FLAG_MASK_FW, "MASK_FW" },
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{ XIVE_IRQ_FLAG_EOI_FW, "EOI_FW" },
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{ XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
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@ -64,8 +64,6 @@ int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
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data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
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if (opal_flags & OPAL_XIVE_IRQ_LSI)
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data->flags |= XIVE_IRQ_FLAG_LSI;
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if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
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data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
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if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
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data->flags |= XIVE_IRQ_FLAG_MASK_FW;
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if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
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