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Renesas driver updates for v5.5 

- Add support for the new RZ/G2N (r8a774b1) SoC,
   - Fix System Controller power request conflicts on recent R-Car Gen3
     and RZ/G2N SoC variants and revisions,
   - Minor cleanups.
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Merge tag 'renesas-drivers-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v5.5

  - Add support for the new RZ/G2N (r8a774b1) SoC,
  - Fix System Controller power request conflicts on recent R-Car Gen3
    and RZ/G2N SoC variants and revisions,
  - Minor cleanups.

* tag 'renesas-drivers-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rcar-sysc: Add r8a774b1 support
  soc: renesas: rcar-sysc: Remove unneeded inclusion of <linux/bug.h>
  soc: renesas: r8a774c0-sysc: Fix power request conflicts
  soc: renesas: rcar-rst: Add support for RZ/G2N
  soc: renesas: Identify RZ/G2N
  soc: renesas: Add Renesas R8A774B1 config option
  soc: renesas: r8a77990-sysc: Fix power request conflicts
  soc: renesas: r8a77980-sysc: Fix power request conflicts
  soc: renesas: r8a77970-sysc: Fix power request conflicts
  soc: renesas: r8a77965-sysc: Fix power request conflicts
  soc: renesas: r8a7796-sysc: Fix power request conflicts
  soc: renesas: r8a7795-sysc: Fix power request conflicts
  soc: renesas: rcar-sysc: Prepare for fixing power request conflicts
  dt-bindings: clk: Add r8a774b1 CPG Core Clock Definitions
  dt-bindings: power: Add r8a774b1 SYSC power domain definitions

Link: https://lore.kernel.org/r/20191018101136.26350-5-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-10-21 14:50:31 -07:00
parent da0c9ea146 6655c568ce
commit 4cc45d3892
26 changed files with 229 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/soc/renesas/Kconfig
View File

@ -178,6 +178,13 @@ config ARCH_R8A774A1
help
This enables support for the Renesas RZ/G2M SoC.
config ARCH_R8A774B1
bool "Renesas RZ/G2N SoC Platform"
select ARCH_RCAR_GEN3
select SYSC_R8A774B1
help
This enables support for the Renesas RZ/G2N SoC.
config ARCH_R8A774C0
bool "Renesas RZ/G2E SoC Platform"
select ARCH_RCAR_GEN3
@ -253,6 +260,10 @@ config SYSC_R8A774A1
bool "RZ/G2M System Controller support" if COMPILE_TEST
select SYSC_RCAR
config SYSC_R8A774B1
bool "RZ/G2N System Controller support" if COMPILE_TEST
select SYSC_RCAR
config SYSC_R8A774C0
bool "RZ/G2E System Controller support" if COMPILE_TEST
select SYSC_RCAR

1
drivers/soc/renesas/Makefile
View File

@ -7,6 +7,7 @@ obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o
obj-$(CONFIG_SYSC_R8A774A1) += r8a774a1-sysc.o
obj-$(CONFIG_SYSC_R8A774B1) += r8a774b1-sysc.o
obj-$(CONFIG_SYSC_R8A774C0) += r8a774c0-sysc.o
obj-$(CONFIG_SYSC_R8A7779) += r8a7779-sysc.o
obj-$(CONFIG_SYSC_R8A7790) += r8a7790-sysc.o

1
drivers/soc/renesas/r8a7743-sysc.c
View File

@ -5,7 +5,6 @@
* Copyright (C) 2016 Cogent Embedded Inc.
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a7743-sysc.h>

1
drivers/soc/renesas/r8a7745-sysc.c
View File

@ -5,7 +5,6 @@
* Copyright (C) 2016 Cogent Embedded Inc.
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a7745-sysc.h>

1
drivers/soc/renesas/r8a77470-sysc.c
View File

@ -5,7 +5,6 @@
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a77470-sysc.h>

1
drivers/soc/renesas/r8a774a1-sysc.c
View File

@ -7,7 +7,6 @@
* Copyright (C) 2016 Glider bvba
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a774a1-sysc.h>

37
drivers/soc/renesas/r8a774b1-sysc.c Normal file
View File

@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas RZ/G2N System Controller
* Copyright (C) 2019 Renesas Electronics Corp.
*
* Based on Renesas R-Car M3-W System Controller
* Copyright (C) 2016 Glider bvba
*/
#include <linux/bits.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a774b1-sysc.h>
#include "rcar-sysc.h"
static const struct rcar_sysc_area r8a774b1_areas[] __initconst = {
{ "always-on", 0, 0, R8A774B1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
{ "ca57-scu", 0x1c0, 0, R8A774B1_PD_CA57_SCU, R8A774B1_PD_ALWAYS_ON,
PD_SCU },
{ "ca57-cpu0", 0x80, 0, R8A774B1_PD_CA57_CPU0, R8A774B1_PD_CA57_SCU,
PD_CPU_NOCR },
{ "ca57-cpu1", 0x80, 1, R8A774B1_PD_CA57_CPU1, R8A774B1_PD_CA57_SCU,
PD_CPU_NOCR },
{ "a3vc", 0x380, 0, R8A774B1_PD_A3VC, R8A774B1_PD_ALWAYS_ON },
{ "a3vp", 0x340, 0, R8A774B1_PD_A3VP, R8A774B1_PD_ALWAYS_ON },
{ "a2vc1", 0x3c0, 1, R8A774B1_PD_A2VC1, R8A774B1_PD_A3VC },
{ "3dg-a", 0x100, 0, R8A774B1_PD_3DG_A, R8A774B1_PD_ALWAYS_ON },
{ "3dg-b", 0x100, 1, R8A774B1_PD_3DG_B, R8A774B1_PD_3DG_A },
};
const struct rcar_sysc_info r8a774b1_sysc_info __initconst = {
.areas = r8a774b1_areas,
.num_areas = ARRAY_SIZE(r8a774b1_areas),
.extmask_offs = 0x2f8,
.extmask_val = BIT(0),
};

4
drivers/soc/renesas/r8a774c0-sysc.c
View File

@ -6,7 +6,7 @@
* Based on Renesas R-Car E3 System Controller
*/
#include <linux/bug.h>
#include <linux/bits.h>
#include <linux/kernel.h>
#include <linux/sys_soc.h>
@ -50,4 +50,6 @@ const struct rcar_sysc_info r8a774c0_sysc_info __initconst = {
.init = r8a774c0_sysc_init,
.areas = r8a774c0_areas,
.num_areas = ARRAY_SIZE(r8a774c0_areas),
.extmask_offs = 0x2f8,
.extmask_val = BIT(0),
};

1
drivers/soc/renesas/r8a7779-sysc.c
View File

@ -5,7 +5,6 @@
* Copyright (C) 2016 Glider bvba
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a7779-sysc.h>

1
drivers/soc/renesas/r8a7790-sysc.c
View File

@ -5,7 +5,6 @@
* Copyright (C) 2016 Glider bvba
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a7790-sysc.h>

1
drivers/soc/renesas/r8a7791-sysc.c
View File

@ -5,7 +5,6 @@
* Copyright (C) 2016 Glider bvba
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a7791-sysc.h>

1
drivers/soc/renesas/r8a7792-sysc.c
View File

@ -5,7 +5,6 @@
* Copyright (C) 2016 Cogent Embedded Inc.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>

1
drivers/soc/renesas/r8a7794-sysc.c
View File

@ -5,7 +5,6 @@
* Copyright (C) 2016 Glider bvba
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a7794-sysc.h>

33
drivers/soc/renesas/r8a7795-sysc.c
View File

@ -5,7 +5,7 @@
* Copyright (C) 2016-2017 Glider bvba
*/
#include <linux/bug.h>
#include <linux/bits.h>
#include <linux/kernel.h>
#include <linux/sys_soc.h>
@ -51,25 +51,46 @@ static struct rcar_sysc_area r8a7795_areas[] __initdata = {
/*
* Fixups for R-Car H3 revisions after ES1.x
* Fixups for R-Car H3 revisions
*/
static const struct soc_device_attribute r8a7795es1[] __initconst = {
{ .soc_id = "r8a7795", .revision = "ES1.*" },
#define HAS_A2VC0 BIT(0) /* Power domain A2VC0 is present */
#define NO_EXTMASK BIT(1) /* Missing SYSCEXTMASK register */
static const struct soc_device_attribute r8a7795_quirks_match[] __initconst = {
{
.soc_id = "r8a7795", .revision = "ES1.*",
.data = (void *)(HAS_A2VC0 | NO_EXTMASK),
}, {
.soc_id = "r8a7795", .revision = "ES2.*",
.data = (void *)(NO_EXTMASK),
},
{ /* sentinel */ }
};
static int __init r8a7795_sysc_init(void)
{
if (!soc_device_match(r8a7795es1))
const struct soc_device_attribute *attr;
u32 quirks = 0;
attr = soc_device_match(r8a7795_quirks_match);
if (attr)
quirks = (uintptr_t)attr->data;
if (!(quirks & HAS_A2VC0))
rcar_sysc_nullify(r8a7795_areas, ARRAY_SIZE(r8a7795_areas),
R8A7795_PD_A2VC0);
if (quirks & NO_EXTMASK)
r8a7795_sysc_info.extmask_val = 0;
return 0;
}
const struct rcar_sysc_info r8a7795_sysc_info __initconst = {
struct rcar_sysc_info r8a7795_sysc_info __initdata = {
.init = r8a7795_sysc_init,
.areas = r8a7795_areas,
.num_areas = ARRAY_SIZE(r8a7795_areas),
.extmask_offs = 0x2f8,
.extmask_val = BIT(0),
};

23
drivers/soc/renesas/r8a7796-sysc.c
View File

@ -5,8 +5,9 @@
* Copyright (C) 2016 Glider bvba
*/
#include <linux/bug.h>
#include <linux/bits.h>
#include <linux/kernel.h>
#include <linux/sys_soc.h>
#include <dt-bindings/power/r8a7796-sysc.h>
@ -39,7 +40,25 @@ static const struct rcar_sysc_area r8a7796_areas[] __initconst = {
{ "a3ir", 0x180, 0, R8A7796_PD_A3IR, R8A7796_PD_ALWAYS_ON },
};
const struct rcar_sysc_info r8a7796_sysc_info __initconst = {
/* Fixups for R-Car M3-W ES1.x revision */
static const struct soc_device_attribute r8a7796es1[] __initconst = {
{ .soc_id = "r8a7796", .revision = "ES1.*" },
{ /* sentinel */ }
};
static int __init r8a7796_sysc_init(void)
{
if (soc_device_match(r8a7796es1))
r8a7796_sysc_info.extmask_val = 0;
return 0;
}
struct rcar_sysc_info r8a7796_sysc_info __initdata = {
.init = r8a7796_sysc_init,
.areas = r8a7796_areas,
.num_areas = ARRAY_SIZE(r8a7796_areas),
.extmask_offs = 0x2f8,
.extmask_val = BIT(0),
};

4
drivers/soc/renesas/r8a77965-sysc.c
View File

@ -7,7 +7,7 @@
* Copyright (C) 2016 Glider bvba
*/
#include <linux/bug.h>
#include <linux/bits.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a77965-sysc.h>
@ -33,4 +33,6 @@ static const struct rcar_sysc_area r8a77965_areas[] __initconst = {
const struct rcar_sysc_info r8a77965_sysc_info __initconst = {
.areas = r8a77965_areas,
.num_areas = ARRAY_SIZE(r8a77965_areas),
.extmask_offs = 0x2f8,
.extmask_val = BIT(0),
};

4
drivers/soc/renesas/r8a77970-sysc.c
View File

@ -5,7 +5,7 @@
* Copyright (C) 2017 Cogent Embedded Inc.
*/
#include <linux/bug.h>
#include <linux/bits.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a77970-sysc.h>
@ -32,4 +32,6 @@ static const struct rcar_sysc_area r8a77970_areas[] __initconst = {
const struct rcar_sysc_info r8a77970_sysc_info __initconst = {
.areas = r8a77970_areas,
.num_areas = ARRAY_SIZE(r8a77970_areas),
.extmask_offs = 0x1b0,
.extmask_val = BIT(0),
};

4
drivers/soc/renesas/r8a77980-sysc.c
View File

@ -6,7 +6,7 @@
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
#include <linux/bug.h>
#include <linux/bits.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a77980-sysc.h>
@ -49,4 +49,6 @@ static const struct rcar_sysc_area r8a77980_areas[] __initconst = {
const struct rcar_sysc_info r8a77980_sysc_info __initconst = {
.areas = r8a77980_areas,
.num_areas = ARRAY_SIZE(r8a77980_areas),
.extmask_offs = 0x138,
.extmask_val = BIT(0),
};

4
drivers/soc/renesas/r8a77990-sysc.c
View File

@ -5,7 +5,7 @@
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <linux/bug.h>
#include <linux/bits.h>
#include <linux/kernel.h>
#include <linux/sys_soc.h>
@ -50,4 +50,6 @@ const struct rcar_sysc_info r8a77990_sysc_info __initconst = {
.init = r8a77990_sysc_init,
.areas = r8a77990_areas,
.num_areas = ARRAY_SIZE(r8a77990_areas),
.extmask_offs = 0x2f8,
.extmask_val = BIT(0),
};

1
drivers/soc/renesas/r8a77995-sysc.c
View File

@ -5,7 +5,6 @@
* Copyright (C) 2017 Glider bvba
*/
#include <linux/bug.h>
#include <linux/kernel.h>
#include <dt-bindings/power/r8a77995-sysc.h>

1
drivers/soc/renesas/rcar-rst.c
View File

@ -45,6 +45,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
/* RZ/G2 is handled like R-Car Gen3 */
{ .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a774b1-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },
/* R-Car Gen1 */
{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },

19
drivers/soc/renesas/rcar-sysc.c
View File

@ -63,6 +63,7 @@ struct rcar_sysc_ch {
static void __iomem *rcar_sysc_base;
static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
static u32 rcar_sysc_extmask_offs, rcar_sysc_extmask_val;
static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
{
@ -105,6 +106,14 @@ static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
spin_lock_irqsave(&rcar_sysc_lock, flags);
/*
* Mask external power requests for CPU or 3DG domains
*/
if (rcar_sysc_extmask_val) {
iowrite32(rcar_sysc_extmask_val,
rcar_sysc_base + rcar_sysc_extmask_offs);
}
/*
* The interrupt source needs to be enabled, but masked, to prevent the
* CPU from receiving it.
@ -148,6 +157,9 @@ static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
out:
if (rcar_sysc_extmask_val)
iowrite32(0, rcar_sysc_base + rcar_sysc_extmask_offs);
spin_unlock_irqrestore(&rcar_sysc_lock, flags);
pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
@ -275,6 +287,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
#ifdef CONFIG_SYSC_R8A774A1
{ .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
#endif
#ifdef CONFIG_SYSC_R8A774B1
{ .compatible = "renesas,r8a774b1-sysc", .data = &r8a774b1_sysc_info },
#endif
#ifdef CONFIG_SYSC_R8A774C0
{ .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
#endif
@ -360,6 +375,10 @@ static int __init rcar_sysc_pd_init(void)
rcar_sysc_base = base;
/* Optional External Request Mask Register */
rcar_sysc_extmask_offs = info->extmask_offs;
rcar_sysc_extmask_val = info->extmask_val;
domains = kzalloc(sizeof(*domains), GFP_KERNEL);
if (!domains) {
error = -ENOMEM;

8
drivers/soc/renesas/rcar-sysc.h
View File

@ -44,20 +44,24 @@ struct rcar_sysc_info {
int (*init)(void); /* Optional */
const struct rcar_sysc_area *areas;
unsigned int num_areas;
/* Optional External Request Mask Register */
u32 extmask_offs; /* SYSCEXTMASK register offset */
u32 extmask_val; /* SYSCEXTMASK register mask value */
};
extern const struct rcar_sysc_info r8a7743_sysc_info;
extern const struct rcar_sysc_info r8a7745_sysc_info;
extern const struct rcar_sysc_info r8a77470_sysc_info;
extern const struct rcar_sysc_info r8a774a1_sysc_info;
extern const struct rcar_sysc_info r8a774b1_sysc_info;
extern const struct rcar_sysc_info r8a774c0_sysc_info;
extern const struct rcar_sysc_info r8a7779_sysc_info;
extern const struct rcar_sysc_info r8a7790_sysc_info;
extern const struct rcar_sysc_info r8a7791_sysc_info;
extern const struct rcar_sysc_info r8a7792_sysc_info;
extern const struct rcar_sysc_info r8a7794_sysc_info;
extern const struct rcar_sysc_info r8a7795_sysc_info;
extern const struct rcar_sysc_info r8a7796_sysc_info;
extern struct rcar_sysc_info r8a7795_sysc_info;
extern struct rcar_sysc_info r8a7796_sysc_info;
extern const struct rcar_sysc_info r8a77965_sysc_info;
extern const struct rcar_sysc_info r8a77970_sysc_info;
extern const struct rcar_sysc_info r8a77980_sysc_info;

8
drivers/soc/renesas/renesas-soc.c
View File

@ -116,6 +116,11 @@ static const struct renesas_soc soc_rz_g2m __initconst __maybe_unused = {
.id = 0x52,
};
static const struct renesas_soc soc_rz_g2n __initconst __maybe_unused = {
.family = &fam_rzg2,
.id = 0x55,
};
static const struct renesas_soc soc_rz_g2e __initconst __maybe_unused = {
.family = &fam_rzg2,
.id = 0x57,
@ -227,6 +232,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A774A1
{ .compatible = "renesas,r8a774a1", .data = &soc_rz_g2m },
#endif
#ifdef CONFIG_ARCH_R8A774B1
{ .compatible = "renesas,r8a774b1", .data = &soc_rz_g2n },
#endif
#ifdef CONFIG_ARCH_R8A774C0
{ .compatible = "renesas,r8a774c0", .data = &soc_rz_g2e },
#endif

57
include/dt-bindings/clock/r8a774b1-cpg-mssr.h Normal file
View File

@ -0,0 +1,57 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a774b1 CPG Core Clocks */
#define R8A774B1_CLK_Z 0
#define R8A774B1_CLK_ZG 1
#define R8A774B1_CLK_ZTR 2
#define R8A774B1_CLK_ZTRD2 3
#define R8A774B1_CLK_ZT 4
#define R8A774B1_CLK_ZX 5
#define R8A774B1_CLK_S0D1 6
#define R8A774B1_CLK_S0D2 7
#define R8A774B1_CLK_S0D3 8
#define R8A774B1_CLK_S0D4 9
#define R8A774B1_CLK_S0D6 10
#define R8A774B1_CLK_S0D8 11
#define R8A774B1_CLK_S0D12 12
#define R8A774B1_CLK_S1D2 13
#define R8A774B1_CLK_S1D4 14
#define R8A774B1_CLK_S2D1 15
#define R8A774B1_CLK_S2D2 16
#define R8A774B1_CLK_S2D4 17
#define R8A774B1_CLK_S3D1 18
#define R8A774B1_CLK_S3D2 19
#define R8A774B1_CLK_S3D4 20
#define R8A774B1_CLK_LB 21
#define R8A774B1_CLK_CL 22
#define R8A774B1_CLK_ZB3 23
#define R8A774B1_CLK_ZB3D2 24
#define R8A774B1_CLK_CR 25
#define R8A774B1_CLK_DDR 26
#define R8A774B1_CLK_SD0H 27
#define R8A774B1_CLK_SD0 28
#define R8A774B1_CLK_SD1H 29
#define R8A774B1_CLK_SD1 30
#define R8A774B1_CLK_SD2H 31
#define R8A774B1_CLK_SD2 32
#define R8A774B1_CLK_SD3H 33
#define R8A774B1_CLK_SD3 34
#define R8A774B1_CLK_RPC 35
#define R8A774B1_CLK_RPCD2 36
#define R8A774B1_CLK_MSO 37
#define R8A774B1_CLK_HDMI 38
#define R8A774B1_CLK_CSI0 39
#define R8A774B1_CLK_CP 40
#define R8A774B1_CLK_CPEX 41
#define R8A774B1_CLK_R 42
#define R8A774B1_CLK_OSC 43
#define R8A774B1_CLK_CANFD 44
#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */

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include/dt-bindings/power/r8a774b1-sysc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774B1_PD_CA57_CPU0 0
#define R8A774B1_PD_CA57_CPU1 1
#define R8A774B1_PD_A3VP 9
#define R8A774B1_PD_CA57_SCU 12
#define R8A774B1_PD_A3VC 14
#define R8A774B1_PD_3DG_A 17
#define R8A774B1_PD_3DG_B 18
#define R8A774B1_PD_A2VC1 26
/* Always-on power area */
#define R8A774B1_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */