[IA64] remove duplicate code for register access
We have duplicate code to access registers (access_uarea and regset way). They just have different layout, so remove duplicate code. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Shaohua Li
Tony Luck
parent
6cb53d7a6f
commit
4cd8dc8358
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@ -745,25 +745,6 @@ ia64_sync_fph (struct task_struct *task)
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psr->dfh = 1;
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}
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static int
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access_fr (struct unw_frame_info *info, int regnum, int hi,
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unsigned long *data, int write_access)
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{
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struct ia64_fpreg fpval;
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int ret;
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ret = unw_get_fr(info, regnum, &fpval);
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if (ret < 0)
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return ret;
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if (write_access) {
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fpval.u.bits[hi] = *data;
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ret = unw_set_fr(info, regnum, fpval);
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} else
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*data = fpval.u.bits[hi];
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return ret;
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}
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/*
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* Change the machine-state of CHILD such that it will return via the normal
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* kernel exit-path, rather than the syscall-exit path.
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@ -865,309 +846,7 @@ access_nat_bits (struct task_struct *child, struct pt_regs *pt,
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static int
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access_uarea (struct task_struct *child, unsigned long addr,
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unsigned long *data, int write_access)
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{
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unsigned long *ptr, regnum, urbs_end, cfm;
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struct switch_stack *sw;
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struct pt_regs *pt;
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# define pt_reg_addr(pt, reg) ((void *) \
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((unsigned long) (pt) \
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+ offsetof(struct pt_regs, reg)))
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pt = task_pt_regs(child);
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sw = (struct switch_stack *) (child->thread.ksp + 16);
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if ((addr & 0x7) != 0) {
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dprintk("ptrace: unaligned register address 0x%lx\n", addr);
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return -1;
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}
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if (addr < PT_F127 + 16) {
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/* accessing fph */
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if (write_access)
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ia64_sync_fph(child);
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else
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ia64_flush_fph(child);
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ptr = (unsigned long *)
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((unsigned long) &child->thread.fph + addr);
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} else if ((addr >= PT_F10) && (addr < PT_F11 + 16)) {
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/* scratch registers untouched by kernel (saved in pt_regs) */
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ptr = pt_reg_addr(pt, f10) + (addr - PT_F10);
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} else if (addr >= PT_F12 && addr < PT_F15 + 16) {
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/*
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* Scratch registers untouched by kernel (saved in
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* switch_stack).
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*/
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ptr = (unsigned long *) ((long) sw
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+ (addr - PT_NAT_BITS - 32));
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} else if (addr < PT_AR_LC + 8) {
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/* preserved state: */
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struct unw_frame_info info;
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char nat = 0;
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int ret;
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unw_init_from_blocked_task(&info, child);
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if (unw_unwind_to_user(&info) < 0)
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return -1;
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switch (addr) {
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case PT_NAT_BITS:
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return access_nat_bits(child, pt, &info,
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data, write_access);
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case PT_R4: case PT_R5: case PT_R6: case PT_R7:
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if (write_access) {
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/* read NaT bit first: */
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unsigned long dummy;
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ret = unw_get_gr(&info, (addr - PT_R4)/8 + 4,
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&dummy, &nat);
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if (ret < 0)
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return ret;
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}
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return unw_access_gr(&info, (addr - PT_R4)/8 + 4, data,
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&nat, write_access);
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case PT_B1: case PT_B2: case PT_B3:
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case PT_B4: case PT_B5:
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return unw_access_br(&info, (addr - PT_B1)/8 + 1, data,
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write_access);
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case PT_AR_EC:
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return unw_access_ar(&info, UNW_AR_EC, data,
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write_access);
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case PT_AR_LC:
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return unw_access_ar(&info, UNW_AR_LC, data,
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write_access);
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default:
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if (addr >= PT_F2 && addr < PT_F5 + 16)
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return access_fr(&info, (addr - PT_F2)/16 + 2,
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(addr & 8) != 0, data,
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write_access);
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else if (addr >= PT_F16 && addr < PT_F31 + 16)
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return access_fr(&info,
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(addr - PT_F16)/16 + 16,
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(addr & 8) != 0,
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data, write_access);
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else {
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dprintk("ptrace: rejecting access to register "
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"address 0x%lx\n", addr);
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return -1;
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}
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}
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} else if (addr < PT_F9+16) {
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/* scratch state */
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switch (addr) {
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case PT_AR_BSP:
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/*
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* By convention, we use PT_AR_BSP to refer to
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* the end of the user-level backing store.
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* Use ia64_rse_skip_regs(PT_AR_BSP, -CFM.sof)
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* to get the real value of ar.bsp at the time
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* the kernel was entered.
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*
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* Furthermore, when changing the contents of
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* PT_AR_BSP (or PT_CFM) while the task is
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* blocked in a system call, convert the state
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* so that the non-system-call exit
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* path is used. This ensures that the proper
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* state will be picked up when resuming
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* execution. However, it *also* means that
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* once we write PT_AR_BSP/PT_CFM, it won't be
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* possible to modify the syscall arguments of
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* the pending system call any longer. This
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* shouldn't be an issue because modifying
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* PT_AR_BSP/PT_CFM generally implies that
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* we're either abandoning the pending system
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* call or that we defer it's re-execution
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* (e.g., due to GDB doing an inferior
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* function call).
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*/
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urbs_end = ia64_get_user_rbs_end(child, pt, &cfm);
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if (write_access) {
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if (*data != urbs_end) {
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if (in_syscall(pt))
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convert_to_non_syscall(child,
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pt,
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cfm);
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/*
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* Simulate user-level write
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* of ar.bsp:
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*/
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pt->loadrs = 0;
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pt->ar_bspstore = *data;
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}
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} else
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*data = urbs_end;
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return 0;
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case PT_CFM:
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urbs_end = ia64_get_user_rbs_end(child, pt, &cfm);
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if (write_access) {
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if (((cfm ^ *data) & PFM_MASK) != 0) {
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if (in_syscall(pt))
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convert_to_non_syscall(child,
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pt,
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cfm);
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pt->cr_ifs = ((pt->cr_ifs & ~PFM_MASK)
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| (*data & PFM_MASK));
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}
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} else
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*data = cfm;
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return 0;
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case PT_CR_IPSR:
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if (write_access) {
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unsigned long tmp = *data;
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/* psr.ri==3 is a reserved value: SDM 2:25 */
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if ((tmp & IA64_PSR_RI) == IA64_PSR_RI)
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tmp &= ~IA64_PSR_RI;
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pt->cr_ipsr = ((tmp & IPSR_MASK)
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| (pt->cr_ipsr & ~IPSR_MASK));
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} else
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*data = (pt->cr_ipsr & IPSR_MASK);
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return 0;
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case PT_AR_RSC:
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if (write_access)
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pt->ar_rsc = *data | (3 << 2); /* force PL3 */
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else
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*data = pt->ar_rsc;
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return 0;
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case PT_AR_RNAT:
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ptr = pt_reg_addr(pt, ar_rnat);
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break;
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case PT_R1:
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ptr = pt_reg_addr(pt, r1);
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break;
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case PT_R2: case PT_R3:
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ptr = pt_reg_addr(pt, r2) + (addr - PT_R2);
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break;
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case PT_R8: case PT_R9: case PT_R10: case PT_R11:
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ptr = pt_reg_addr(pt, r8) + (addr - PT_R8);
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break;
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case PT_R12: case PT_R13:
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ptr = pt_reg_addr(pt, r12) + (addr - PT_R12);
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break;
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case PT_R14:
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ptr = pt_reg_addr(pt, r14);
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break;
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case PT_R15:
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ptr = pt_reg_addr(pt, r15);
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break;
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case PT_R16: case PT_R17: case PT_R18: case PT_R19:
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case PT_R20: case PT_R21: case PT_R22: case PT_R23:
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case PT_R24: case PT_R25: case PT_R26: case PT_R27:
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case PT_R28: case PT_R29: case PT_R30: case PT_R31:
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ptr = pt_reg_addr(pt, r16) + (addr - PT_R16);
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break;
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case PT_B0:
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ptr = pt_reg_addr(pt, b0);
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break;
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case PT_B6:
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ptr = pt_reg_addr(pt, b6);
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break;
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case PT_B7:
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ptr = pt_reg_addr(pt, b7);
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break;
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case PT_F6: case PT_F6+8: case PT_F7: case PT_F7+8:
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case PT_F8: case PT_F8+8: case PT_F9: case PT_F9+8:
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ptr = pt_reg_addr(pt, f6) + (addr - PT_F6);
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break;
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case PT_AR_BSPSTORE:
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ptr = pt_reg_addr(pt, ar_bspstore);
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break;
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case PT_AR_UNAT:
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ptr = pt_reg_addr(pt, ar_unat);
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break;
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case PT_AR_PFS:
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ptr = pt_reg_addr(pt, ar_pfs);
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break;
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case PT_AR_CCV:
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ptr = pt_reg_addr(pt, ar_ccv);
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break;
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case PT_AR_FPSR:
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ptr = pt_reg_addr(pt, ar_fpsr);
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break;
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case PT_CR_IIP:
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ptr = pt_reg_addr(pt, cr_iip);
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break;
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case PT_PR:
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ptr = pt_reg_addr(pt, pr);
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break;
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/* scratch register */
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default:
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/* disallow accessing anything else... */
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dprintk("ptrace: rejecting access to register "
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"address 0x%lx\n", addr);
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return -1;
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}
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} else if (addr <= PT_AR_SSD) {
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ptr = pt_reg_addr(pt, ar_csd) + (addr - PT_AR_CSD);
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} else {
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/* access debug registers */
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if (addr >= PT_IBR) {
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regnum = (addr - PT_IBR) >> 3;
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ptr = &child->thread.ibr[0];
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} else {
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regnum = (addr - PT_DBR) >> 3;
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ptr = &child->thread.dbr[0];
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}
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if (regnum >= 8) {
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dprintk("ptrace: rejecting access to register "
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"address 0x%lx\n", addr);
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return -1;
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}
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#ifdef CONFIG_PERFMON
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/*
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* Check if debug registers are used by perfmon. This
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* test must be done once we know that we can do the
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* operation, i.e. the arguments are all valid, but
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* before we start modifying the state.
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*
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* Perfmon needs to keep a count of how many processes
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* are trying to modify the debug registers for system
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* wide monitoring sessions.
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*
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* We also include read access here, because they may
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* cause the PMU-installed debug register state
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* (dbr[], ibr[]) to be reset. The two arrays are also
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* used by perfmon, but we do not use
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* IA64_THREAD_DBG_VALID. The registers are restored
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* by the PMU context switch code.
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*/
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if (pfm_use_debug_registers(child)) return -1;
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#endif
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if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
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child->thread.flags |= IA64_THREAD_DBG_VALID;
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memset(child->thread.dbr, 0,
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sizeof(child->thread.dbr));
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memset(child->thread.ibr, 0,
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sizeof(child->thread.ibr));
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}
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ptr += regnum;
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if ((regnum & 1) && write_access) {
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/* don't let the user set kernel-level breakpoints: */
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*ptr = *data & ~(7UL << 56);
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return 0;
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}
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}
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if (write_access)
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*ptr = *data;
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else
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*data = *ptr;
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return 0;
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}
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unsigned long *data, int write_access);
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static long
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ptrace_getregs (struct task_struct *child, struct pt_all_user_regs __user *ppr)
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@ -2290,6 +1969,205 @@ static int fpregs_set(struct task_struct *target,
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kbuf, ubuf);
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}
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static int
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access_uarea(struct task_struct *child, unsigned long addr,
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unsigned long *data, int write_access)
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{
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unsigned int pos = -1; /* an invalid value */
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int ret;
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unsigned long *ptr, regnum;
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if ((addr & 0x7) != 0) {
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dprintk("ptrace: unaligned register address 0x%lx\n", addr);
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return -1;
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}
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if ((addr >= PT_NAT_BITS + 8 && addr < PT_F2) ||
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(addr >= PT_R7 + 8 && addr < PT_B1) ||
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(addr >= PT_AR_LC + 8 && addr < PT_CR_IPSR) ||
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(addr >= PT_AR_SSD + 8 && addr < PT_DBR)) {
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dprintk("ptrace: rejecting access to register "
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"address 0x%lx\n", addr);
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return -1;
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}
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switch (addr) {
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case PT_F32 ... (PT_F127 + 15):
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pos = addr - PT_F32 + ELF_FP_OFFSET(32);
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break;
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case PT_F2 ... (PT_F5 + 15):
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pos = addr - PT_F2 + ELF_FP_OFFSET(2);
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break;
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case PT_F10 ... (PT_F31 + 15):
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pos = addr - PT_F10 + ELF_FP_OFFSET(10);
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break;
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case PT_F6 ... (PT_F9 + 15):
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pos = addr - PT_F6 + ELF_FP_OFFSET(6);
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break;
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}
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if (pos != -1) {
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if (write_access)
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ret = fpregs_set(child, NULL, pos,
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sizeof(unsigned long), data, NULL);
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else
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ret = fpregs_get(child, NULL, pos,
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sizeof(unsigned long), data, NULL);
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if (ret != 0)
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return -1;
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return 0;
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}
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switch (addr) {
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case PT_NAT_BITS:
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pos = ELF_NAT_OFFSET;
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break;
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case PT_R4 ... PT_R7:
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pos = addr - PT_R4 + ELF_GR_OFFSET(4);
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break;
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case PT_B1 ... PT_B5:
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pos = addr - PT_B1 + ELF_BR_OFFSET(1);
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break;
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case PT_AR_EC:
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pos = ELF_AR_EC_OFFSET;
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break;
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case PT_AR_LC:
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pos = ELF_AR_LC_OFFSET;
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break;
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case PT_CR_IPSR:
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pos = ELF_CR_IPSR_OFFSET;
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break;
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case PT_CR_IIP:
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pos = ELF_CR_IIP_OFFSET;
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break;
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case PT_CFM:
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pos = ELF_CFM_OFFSET;
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break;
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case PT_AR_UNAT:
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pos = ELF_AR_UNAT_OFFSET;
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break;
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case PT_AR_PFS:
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pos = ELF_AR_PFS_OFFSET;
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break;
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case PT_AR_RSC:
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pos = ELF_AR_RSC_OFFSET;
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break;
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case PT_AR_RNAT:
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pos = ELF_AR_RNAT_OFFSET;
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break;
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case PT_AR_BSPSTORE:
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pos = ELF_AR_BSPSTORE_OFFSET;
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break;
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case PT_PR:
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pos = ELF_PR_OFFSET;
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break;
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case PT_B6:
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pos = ELF_BR_OFFSET(6);
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break;
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case PT_AR_BSP:
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pos = ELF_AR_BSP_OFFSET;
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break;
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case PT_R1 ... PT_R3:
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pos = addr - PT_R1 + ELF_GR_OFFSET(1);
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break;
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case PT_R12 ... PT_R15:
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pos = addr - PT_R12 + ELF_GR_OFFSET(12);
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break;
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case PT_R8 ... PT_R11:
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pos = addr - PT_R8 + ELF_GR_OFFSET(8);
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break;
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case PT_R16 ... PT_R31:
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pos = addr - PT_R16 + ELF_GR_OFFSET(16);
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break;
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case PT_AR_CCV:
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pos = ELF_AR_CCV_OFFSET;
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break;
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case PT_AR_FPSR:
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pos = ELF_AR_FPSR_OFFSET;
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break;
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case PT_B0:
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pos = ELF_BR_OFFSET(0);
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break;
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case PT_B7:
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pos = ELF_BR_OFFSET(7);
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break;
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case PT_AR_CSD:
|
||||
pos = ELF_AR_CSD_OFFSET;
|
||||
break;
|
||||
case PT_AR_SSD:
|
||||
pos = ELF_AR_SSD_OFFSET;
|
||||
break;
|
||||
}
|
||||
|
||||
if (pos != -1) {
|
||||
if (write_access)
|
||||
ret = gpregs_set(child, NULL, pos,
|
||||
sizeof(unsigned long), data, NULL);
|
||||
else
|
||||
ret = gpregs_get(child, NULL, pos,
|
||||
sizeof(unsigned long), data, NULL);
|
||||
if (ret != 0)
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* access debug registers */
|
||||
if (addr >= PT_IBR) {
|
||||
regnum = (addr - PT_IBR) >> 3;
|
||||
ptr = &child->thread.ibr[0];
|
||||
} else {
|
||||
regnum = (addr - PT_DBR) >> 3;
|
||||
ptr = &child->thread.dbr[0];
|
||||
}
|
||||
|
||||
if (regnum >= 8) {
|
||||
dprintk("ptrace: rejecting access to register "
|
||||
"address 0x%lx\n", addr);
|
||||
return -1;
|
||||
}
|
||||
#ifdef CONFIG_PERFMON
|
||||
/*
|
||||
* Check if debug registers are used by perfmon. This
|
||||
* test must be done once we know that we can do the
|
||||
* operation, i.e. the arguments are all valid, but
|
||||
* before we start modifying the state.
|
||||
*
|
||||
* Perfmon needs to keep a count of how many processes
|
||||
* are trying to modify the debug registers for system
|
||||
* wide monitoring sessions.
|
||||
*
|
||||
* We also include read access here, because they may
|
||||
* cause the PMU-installed debug register state
|
||||
* (dbr[], ibr[]) to be reset. The two arrays are also
|
||||
* used by perfmon, but we do not use
|
||||
* IA64_THREAD_DBG_VALID. The registers are restored
|
||||
* by the PMU context switch code.
|
||||
*/
|
||||
if (pfm_use_debug_registers(child))
|
||||
return -1;
|
||||
#endif
|
||||
|
||||
if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
|
||||
child->thread.flags |= IA64_THREAD_DBG_VALID;
|
||||
memset(child->thread.dbr, 0,
|
||||
sizeof(child->thread.dbr));
|
||||
memset(child->thread.ibr, 0,
|
||||
sizeof(child->thread.ibr));
|
||||
}
|
||||
|
||||
ptr += regnum;
|
||||
|
||||
if ((regnum & 1) && write_access) {
|
||||
/* don't let the user set kernel-level breakpoints: */
|
||||
*ptr = *data & ~(7UL << 56);
|
||||
return 0;
|
||||
}
|
||||
if (write_access)
|
||||
*ptr = *data;
|
||||
else
|
||||
*data = *ptr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct user_regset native_regsets[] = {
|
||||
{
|
||||
.core_note_type = NT_PRSTATUS,
|
||||
|
|
|
|||
Loading…
Reference in New Issue