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drm/i915/mtl: Introduce FBC B
MTL introduces a second FBC engine. The two FBC engines can operate entirely independently, FBC A serving pipe A and FBC B serving pipe B. The one place where things might go a bit wrong is the CFB allocation from stolen. We might have to consider some change to the allocation strategy to have a better chance of both engines being able to allocate its CFB. Maybe FBC A should allocate bottom up and FBC B top down, or something? For the moment the allocation strategy is DRM_MM_INSERT_BEST for both. Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220817122624.213889-1-jani.nikula@intel.com
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2 changed files with 3 additions and 1 deletions
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@ -19,6 +19,7 @@ struct intel_plane_state;
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enum intel_fbc_id {
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INTEL_FBC_A,
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INTEL_FBC_B,
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I915_MAX_FBCS,
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};
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@ -1111,7 +1111,8 @@ static const struct intel_device_info pvc_info = {
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#define XE_LPDP_FEATURES \
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XE_LPD_FEATURES, \
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.display.ver = 14, \
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.display.has_cdclk_crawl = 1
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.display.has_cdclk_crawl = 1, \
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.display.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
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__maybe_unused
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static const struct intel_device_info mtl_info = {
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