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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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scsi: be2iscsi: Fix POST check and reset sequence
SLIPORT FUNCTION_RESET does not reset the chip. So POST status needs to be checked before issuing FUNCTION_RESET. The completion of FUNCTION_RESET is indicated in BMBX Rdy bit. be_cmd_fw_initialize too needs to be done before issuing any cmd to FW. be_cmd_fw_initialize is renamed as beiscsi_cmd_special_wrb. Rearrange and rename few functions in init and cleanup path. Signed-off-by: Jitendra Bhivare <jitendra.bhivare@broadcom.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Jitendra Bhivare
Martin K. Petersen
parent
480195c267
commit
4d2ee1e688
4 changed files with 165 additions and 197 deletions
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@ -21,35 +21,6 @@
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#include "be.h"
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#include "be_mgmt.h"
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int be_chk_reset_complete(struct beiscsi_hba *phba)
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{
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unsigned int num_loop;
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u8 *mpu_sem = 0;
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u32 status;
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num_loop = 1000;
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mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
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msleep(5000);
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while (num_loop) {
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status = readl((void *)mpu_sem);
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if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000)
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break;
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msleep(60);
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num_loop--;
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}
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if ((status & 0x80000000) || (!num_loop)) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BC_%d : Failed in be_chk_reset_complete"
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"status = 0x%x\n", status);
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return -EIO;
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}
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return 0;
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}
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struct be_mcc_wrb *alloc_mcc_wrb(struct beiscsi_hba *phba,
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unsigned int *ref_tag)
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{
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@ -769,87 +740,6 @@ int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
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return status;
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}
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/**
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* be_cmd_fw_initialize()- Initialize FW
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* @ctrl: Pointer to function control structure
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*
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* Send FW initialize pattern for the function.
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*
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* return
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* Success: 0
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* Failure: Non-Zero value
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**/
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int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
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int status;
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u8 *endian_check;
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mutex_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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endian_check = (u8 *) wrb;
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*endian_check++ = 0xFF;
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*endian_check++ = 0x12;
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*endian_check++ = 0x34;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xFF;
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*endian_check++ = 0x56;
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*endian_check++ = 0x78;
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*endian_check++ = 0xFF;
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be_dws_cpu_to_le(wrb, sizeof(*wrb));
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status = be_mbox_notify(ctrl);
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if (status)
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BC_%d : be_cmd_fw_initialize Failed\n");
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mutex_unlock(&ctrl->mbox_lock);
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return status;
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}
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/**
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* be_cmd_fw_uninit()- Uinitialize FW
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* @ctrl: Pointer to function control structure
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*
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* Send FW uninitialize pattern for the function
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*
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* return
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* Success: 0
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* Failure: Non-Zero value
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**/
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int be_cmd_fw_uninit(struct be_ctrl_info *ctrl)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
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int status;
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u8 *endian_check;
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mutex_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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endian_check = (u8 *) wrb;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xAA;
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*endian_check++ = 0xBB;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xCC;
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*endian_check++ = 0xDD;
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*endian_check = 0xFF;
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be_dws_cpu_to_le(wrb, sizeof(*wrb));
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status = be_mbox_notify(ctrl);
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if (status)
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BC_%d : be_cmd_fw_uninit Failed\n");
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mutex_unlock(&ctrl->mbox_lock);
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return status;
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}
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int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
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struct be_queue_info *cq, struct be_queue_info *eq,
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bool sol_evts, bool no_delay, int coalesce_wm)
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@ -1293,25 +1183,6 @@ int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
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return status;
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}
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int beiscsi_cmd_reset_function(struct beiscsi_hba *phba)
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{
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struct be_ctrl_info *ctrl = &phba->ctrl;
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct be_post_sgl_pages_req *req = embedded_payload(wrb);
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int status;
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mutex_lock(&ctrl->mbox_lock);
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req = embedded_payload(wrb);
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be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
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be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
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OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
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status = be_mbox_notify(ctrl);
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mutex_unlock(&ctrl->mbox_lock);
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return status;
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}
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/**
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* be_cmd_set_vlan()- Configure VLAN paramters on the adapter
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* @phba: device priv structure instance
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@ -1653,3 +1524,124 @@ int beiscsi_set_uer_feature(struct beiscsi_hba *phba)
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mutex_unlock(&ctrl->mbox_lock);
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return ret;
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}
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static u32 beiscsi_get_post_stage(struct beiscsi_hba *phba)
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{
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u32 sem;
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if (is_chip_be2_be3r(phba))
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sem = ioread32(phba->csr_va + SLIPORT_SEMAPHORE_OFFSET_BEx);
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else
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pci_read_config_dword(phba->pcidev,
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SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
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return sem;
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}
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int beiscsi_check_fw_rdy(struct beiscsi_hba *phba)
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{
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u32 loop, post, rdy = 0;
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loop = 1000;
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while (loop--) {
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post = beiscsi_get_post_stage(phba);
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if (post & POST_ERROR_BIT)
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break;
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if ((post & POST_STAGE_MASK) == POST_STAGE_ARMFW_RDY) {
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rdy = 1;
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break;
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}
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msleep(60);
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}
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if (!rdy) {
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__beiscsi_log(phba, KERN_ERR,
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"BC_%d : FW not ready 0x%x\n", post);
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}
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return rdy;
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}
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static int beiscsi_cmd_function_reset(struct beiscsi_hba *phba)
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{
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struct be_ctrl_info *ctrl = &phba->ctrl;
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct be_post_sgl_pages_req *req = embedded_payload(wrb);
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int status;
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mutex_lock(&ctrl->mbox_lock);
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req = embedded_payload(wrb);
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be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
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be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
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OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
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status = be_mbox_notify(ctrl);
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mutex_unlock(&ctrl->mbox_lock);
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return status;
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}
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int beiscsi_cmd_special_wrb(struct be_ctrl_info *ctrl, u32 load)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
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u8 *endian_check;
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int status;
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mutex_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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endian_check = (u8 *) wrb;
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if (load) {
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/* to start communicating */
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*endian_check++ = 0xFF;
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*endian_check++ = 0x12;
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*endian_check++ = 0x34;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xFF;
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*endian_check++ = 0x56;
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*endian_check++ = 0x78;
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*endian_check++ = 0xFF;
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} else {
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/* to stop communicating */
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*endian_check++ = 0xFF;
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*endian_check++ = 0xAA;
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*endian_check++ = 0xBB;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xCC;
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*endian_check++ = 0xDD;
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*endian_check = 0xFF;
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}
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be_dws_cpu_to_le(wrb, sizeof(*wrb));
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status = be_mbox_notify(ctrl);
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if (status)
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beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
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"BC_%d : special WRB message failed\n");
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mutex_unlock(&ctrl->mbox_lock);
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return status;
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}
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int beiscsi_init_sliport(struct beiscsi_hba *phba)
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{
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int status;
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/* check POST stage before talking to FW */
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status = beiscsi_check_fw_rdy(phba);
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if (!status)
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return -EIO;
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/*
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* SLI COMMON_FUNCTION_RESET completion is indicated by BMBX RDY bit.
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* It should clean up any stale info in FW for this fn.
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*/
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status = beiscsi_cmd_function_reset(phba);
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if (status) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BC_%d : SLI Function Reset failed\n");
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return status;
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}
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/* indicate driver is loading */
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return beiscsi_cmd_special_wrb(&phba->ctrl, 1);
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}
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@ -98,11 +98,23 @@ struct be_mcc_compl {
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#define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
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#define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
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/********** MPU semphore ******************/
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#define MPU_EP_SEMAPHORE_OFFSET 0xac
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#define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
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#define EP_SEMAPHORE_POST_ERR_MASK 0x1
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#define EP_SEMAPHORE_POST_ERR_SHIFT 31
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/********** MPU semphore: used for SH & BE ******************/
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#define SLIPORT_SOFTRESET_OFFSET 0x5c /* CSR BAR offset */
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#define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */
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#define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
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#define POST_STAGE_MASK 0x0000FFFF
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#define POST_ERROR_BIT 0x80000000
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#define POST_ERR_RECOVERY_CODE_MASK 0xF000
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/* Soft Reset register masks */
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#define SLIPORT_SOFTRESET_SR_MASK 0x00000080 /* SR bit */
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/* MPU semphore POST stage values */
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#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
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#define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
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#define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
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#define POST_STAGE_ARMFW_RDY 0xC000 /* FW is done with POST */
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#define POST_STAGE_RECOVERABLE_ERR 0xE000 /* Recoverable err detected */
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/********** MCC door bell ************/
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#define DB_MCCQ_OFFSET 0x140
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@ -110,9 +122,6 @@ struct be_mcc_compl {
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/* Number of entries posted */
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#define DB_MCCQ_NUM_POSTED_SHIFT 16 /* bits 16 - 29 */
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/* MPU semphore POST stage values */
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#define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
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/**
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* When the async bit of mcc_compl is set, the last 4 bytes of
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* mcc_compl is interpreted as follows:
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@ -753,6 +762,12 @@ struct be_cmd_set_features {
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} param;
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} __packed;
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int beiscsi_cmd_special_wrb(struct be_ctrl_info *ctrl, u32 load);
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int beiscsi_check_fw_rdy(struct beiscsi_hba *phba);
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int beiscsi_init_sliport(struct beiscsi_hba *phba);
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int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
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struct be_queue_info *eq, int eq_delay);
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@ -784,9 +799,6 @@ int __beiscsi_mcc_compl_status(struct beiscsi_hba *phba,
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struct be_mcc_wrb **wrb,
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struct be_dma_mem *mbx_cmd_mem);
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/*ISCSI Functuions */
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int be_cmd_fw_initialize(struct be_ctrl_info *ctrl);
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int be_cmd_fw_uninit(struct be_ctrl_info *ctrl);
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struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem);
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int be_mcc_compl_poll(struct beiscsi_hba *phba, unsigned int tag);
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void be_mcc_notify(struct beiscsi_hba *phba, unsigned int tag);
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@ -812,8 +824,6 @@ int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
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struct be_dma_mem *q_mem, u32 page_offset,
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u32 num_pages);
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int beiscsi_cmd_reset_function(struct beiscsi_hba *phba);
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int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, struct be_dma_mem *q_mem,
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struct be_queue_info *wrbq,
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struct hwi_wrb_context *pwrb_context,
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@ -1422,8 +1432,6 @@ struct be_cmd_get_port_name {
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* the cxn
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*/
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int be_chk_reset_complete(struct beiscsi_hba *phba);
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void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
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bool embedded, u8 sge_cnt);
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@ -3544,7 +3544,7 @@ static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
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}
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}
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static void hwi_cleanup(struct beiscsi_hba *phba)
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static void hwi_cleanup_port(struct beiscsi_hba *phba)
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{
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struct be_queue_info *q;
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struct be_ctrl_info *ctrl = &phba->ctrl;
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@ -3603,7 +3603,8 @@ static void hwi_cleanup(struct beiscsi_hba *phba)
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beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
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}
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}
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be_cmd_fw_uninit(ctrl);
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/* last communication, indicate driver is unloading */
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beiscsi_cmd_special_wrb(&phba->ctrl, 0);
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}
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static int be_mcc_queues_create(struct beiscsi_hba *phba,
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@ -3700,8 +3701,7 @@ static int hwi_init_port(struct beiscsi_hba *phba)
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phwi_context->max_eqd = 128;
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phwi_context->min_eqd = 0;
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phwi_context->cur_eqd = 0;
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be_cmd_fw_initialize(&phba->ctrl);
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/* set optic state to unknown */
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/* set port optic state to unknown */
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phba->optic_state = 0xff;
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status = beiscsi_create_eqs(phba, phwi_context);
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@ -3807,7 +3807,7 @@ static int hwi_init_port(struct beiscsi_hba *phba)
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error:
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BM_%d : hwi_init_port failed");
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hwi_cleanup(phba);
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hwi_cleanup_port(phba);
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return status;
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}
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@ -4196,7 +4196,7 @@ static int beiscsi_init_port(struct beiscsi_hba *phba)
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return ret;
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do_cleanup_ctrlr:
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hwi_cleanup(phba);
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hwi_cleanup_port(phba);
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return ret;
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}
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@ -4233,7 +4233,7 @@ static void hwi_purge_eq(struct beiscsi_hba *phba)
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}
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}
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static void beiscsi_clean_port(struct beiscsi_hba *phba)
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static void beiscsi_cleanup_port(struct beiscsi_hba *phba)
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{
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int mgmt_status, ulp_num;
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struct ulp_cid_info *ptr_cid_info = NULL;
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@ -4250,7 +4250,7 @@ static void beiscsi_clean_port(struct beiscsi_hba *phba)
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}
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hwi_purge_eq(phba);
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hwi_cleanup(phba);
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hwi_cleanup_port(phba);
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kfree(phba->io_sgl_hndl_base);
|
||||
kfree(phba->eh_sgl_hndl_base);
|
||||
kfree(phba->ep_array);
|
||||
|
|
@ -5011,12 +5011,12 @@ static void beiscsi_quiesce(struct beiscsi_hba *phba)
|
|||
/* PCI_ERR is set then check if driver is not unloading */
|
||||
if (test_bit(BEISCSI_HBA_RUNNING, &phba->state) &&
|
||||
test_bit(BEISCSI_HBA_PCI_ERR, &phba->state)) {
|
||||
hwi_cleanup(phba);
|
||||
hwi_cleanup_port(phba);
|
||||
return;
|
||||
}
|
||||
|
||||
destroy_workqueue(phba->wq);
|
||||
beiscsi_clean_port(phba);
|
||||
beiscsi_cleanup_port(phba);
|
||||
beiscsi_free_mem(phba);
|
||||
|
||||
beiscsi_unmap_pci_function(phba);
|
||||
|
|
@ -5461,9 +5461,8 @@ static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev)
|
|||
pci_set_power_state(pdev, PCI_D0);
|
||||
pci_restore_state(pdev);
|
||||
|
||||
/* Wait for the CHIP Reset to complete */
|
||||
status = be_chk_reset_complete(phba);
|
||||
if (!status) {
|
||||
status = beiscsi_check_fw_rdy(phba);
|
||||
if (status) {
|
||||
beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
|
||||
"BM_%d : EEH Reset Completed\n");
|
||||
} else {
|
||||
|
|
@ -5478,7 +5477,7 @@ static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev)
|
|||
|
||||
static void beiscsi_eeh_resume(struct pci_dev *pdev)
|
||||
{
|
||||
int ret = 0, i;
|
||||
int ret, i;
|
||||
struct be_eq_obj *pbe_eq;
|
||||
struct beiscsi_hba *phba = NULL;
|
||||
struct hwi_controller *phwi_ctrlr;
|
||||
|
|
@ -5498,19 +5497,9 @@ static void beiscsi_eeh_resume(struct pci_dev *pdev)
|
|||
phba->num_cpus = 1;
|
||||
}
|
||||
|
||||
ret = beiscsi_cmd_reset_function(phba);
|
||||
if (ret) {
|
||||
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
||||
"BM_%d : Reset Failed\n");
|
||||
ret = beiscsi_init_sliport(phba);
|
||||
if (ret)
|
||||
goto ret_err;
|
||||
}
|
||||
|
||||
ret = be_chk_reset_complete(phba);
|
||||
if (ret) {
|
||||
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
||||
"BM_%d : Failed to get out of reset.\n");
|
||||
goto ret_err;
|
||||
}
|
||||
|
||||
beiscsi_get_params(phba);
|
||||
phba->shost->max_id = phba->params.cxns_per_ctrl;
|
||||
|
|
@ -5627,28 +5616,15 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev,
|
|||
ret = be_ctrl_init(phba, pcidev);
|
||||
if (ret) {
|
||||
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
||||
"BM_%d : beiscsi_dev_probe-"
|
||||
"Failed in be_ctrl_init\n");
|
||||
"BM_%d : be_ctrl_init failed\n");
|
||||
goto hba_free;
|
||||
}
|
||||
|
||||
ret = beiscsi_init_sliport(phba);
|
||||
if (ret)
|
||||
goto hba_free;
|
||||
|
||||
set_bit(BEISCSI_HBA_RUNNING, &phba->state);
|
||||
/*
|
||||
* FUNCTION_RESET should clean up any stale info in FW for this fn
|
||||
*/
|
||||
ret = beiscsi_cmd_reset_function(phba);
|
||||
if (ret) {
|
||||
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
||||
"BM_%d : Reset Failed\n");
|
||||
goto hba_free;
|
||||
}
|
||||
ret = be_chk_reset_complete(phba);
|
||||
if (ret) {
|
||||
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
||||
"BM_%d : Failed to get out of reset.\n");
|
||||
goto hba_free;
|
||||
}
|
||||
|
||||
spin_lock_init(&phba->io_sgl_lock);
|
||||
spin_lock_init(&phba->mgmt_sgl_lock);
|
||||
spin_lock_init(&phba->async_pdu_lock);
|
||||
|
|
@ -5772,7 +5748,7 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev,
|
|||
irq_poll_disable(&pbe_eq->iopoll);
|
||||
}
|
||||
free_twq:
|
||||
beiscsi_clean_port(phba);
|
||||
beiscsi_cleanup_port(phba);
|
||||
beiscsi_free_mem(phba);
|
||||
free_port:
|
||||
pci_free_consistent(phba->pcidev,
|
||||
|
|
|
|||
|
|
@ -82,14 +82,6 @@
|
|||
#define BEISCSI_MAX_FRAGS_INIT 192
|
||||
#define BE_NUM_MSIX_ENTRIES 1
|
||||
|
||||
#define MPU_EP_CONTROL 0
|
||||
#define MPU_EP_SEMAPHORE 0xac
|
||||
#define BE2_SOFT_RESET 0x5c
|
||||
#define BE2_PCI_ONLINE0 0xb0
|
||||
#define BE2_PCI_ONLINE1 0xb4
|
||||
#define BE2_SET_RESET 0x80
|
||||
#define BE2_MPU_IRAM_ONLINE 0x00000080
|
||||
|
||||
#define BE_SENSE_INFO_SIZE 258
|
||||
#define BE_ISCSI_PDU_HEADER_SIZE 64
|
||||
#define BE_MIN_MEM_SIZE 16384
|
||||
|
|
|
|||
Loading…
Reference in a new issue