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PCI: imx6: Implement reset sequence for i.MX6+
I.MX6+ has a dedicated bit for resetting PCIe core, which should be used instead of a regular reset sequence since using the latter will hang the SoC. This commit is based on c34068d48273e24d392d9a49a38be807954420ed from http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git Tested-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
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parent
e6f1fef04c
commit
4d31c6109a
3 changed files with 23 additions and 3 deletions
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@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
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- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie"
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- reg: base address and length of the PCIe controller
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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@ -34,7 +34,8 @@
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enum imx6_pcie_variants {
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IMX6Q,
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IMX6SX
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IMX6SX,
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IMX6QP,
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};
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struct imx6_pcie {
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@ -256,6 +257,11 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
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IMX6SX_GPR5_PCIE_BTNRST_RESET,
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IMX6SX_GPR5_PCIE_BTNRST_RESET);
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break;
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case IMX6QP:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_SW_RST,
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IMX6Q_GPR1_PCIE_SW_RST);
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break;
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case IMX6Q:
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/*
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* If the bootloader already enabled the link we need some
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@ -310,6 +316,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
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break;
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case IMX6QP: /* FALLTHROUGH */
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case IMX6Q:
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/* power up core phy and enable ref clock */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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@ -370,9 +377,20 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
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!imx6_pcie->gpio_active_high);
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}
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if (imx6_pcie->variant == IMX6SX)
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switch (imx6_pcie->variant) {
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case IMX6SX:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
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IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
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break;
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case IMX6QP:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_SW_RST, 0);
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usleep_range(200, 500);
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break;
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case IMX6Q: /* Nothing to do */
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break;
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}
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return 0;
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@ -718,6 +736,7 @@ static void imx6_pcie_shutdown(struct platform_device *pdev)
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static const struct of_device_id imx6_pcie_of_match[] = {
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{ .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
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{ .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
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{ .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
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{},
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};
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MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
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@ -95,6 +95,7 @@
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#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX BIT(0)
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#define IMX6Q_GPR1_PCIE_REQ_MASK (0x3 << 30)
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#define IMX6Q_GPR1_PCIE_SW_RST BIT(29)
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#define IMX6Q_GPR1_PCIE_EXIT_L1 BIT(28)
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#define IMX6Q_GPR1_PCIE_RDY_L23 BIT(27)
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#define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26)
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