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drm/i915: Only set gem object L3 cache level for IVB devices
Do some further clean up based on the initial review of drm/i915: Separate cherryview from valleyview. In this case, in i915_gem_alloc_context_obj() only call i915_gem_object_set_cache_level() for Ivy Bridge devices since later platforms don't have L3 control bits in the PTE. v2: Expand comment to mention snooping requirement. (Ville, Imre) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Wayne Boyer <wayne.boyer@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1449596332-23470-1-git-send-email-wayne.boyer@intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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1 changed files with 8 additions and 1 deletions
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@ -189,8 +189,15 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
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* shouldn't touch the cache level, especially as that
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* would make the object snooped which might have a
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* negative performance impact.
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*
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* Snooping is required on non-llc platforms in execlist
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* mode, but since all GGTT accesses use PAT entry 0 we
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* get snooping anyway regardless of cache_level.
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*
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* This is only applicable for Ivy Bridge devices since
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* later platforms don't have L3 control bits in the PTE.
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*/
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if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
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if (IS_IVYBRIDGE(dev)) {
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ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
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/* Failure shouldn't ever happen this early */
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if (WARN_ON(ret)) {
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