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[Blackfin] arch: Update anomaly list.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Sonic Zhang
Bryan Wu
parent
18628e4375
commit
4d55563070
5 changed files with 97 additions and 19 deletions
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@ -2,12 +2,12 @@
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* File: include/asm-blackfin/mach-bf527/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2007 Analog Devices Inc.
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* Copyright (C) 2004-2008 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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* - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List
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* - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -15,35 +15,85 @@
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
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#define ANOMALY_05000301 (1)
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/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (1)
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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#define ANOMALY_05000328 (1)
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/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
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#define ANOMALY_05000337 (1)
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/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */
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/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
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#define ANOMALY_05000341 (1)
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/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
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#define ANOMALY_05000342 (1)
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/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
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/* USB Calibration Value Is Not Initialized */
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#define ANOMALY_05000346 (1)
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/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
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#define ANOMALY_05000347 (1)
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/* Security Features Are Not Functional */
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#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (1)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* Incorrect Revision Number in DSPID Register */
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#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* New Feature: Higher Default CCLK Rate */
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#define ANOMALY_05000368 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* Authentication Fails To Initiate */
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#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
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/* Data Read From L3 Memory by USB DMA May be Corrupted */
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#define ANOMALY_05000380 (1)
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/* USB Full-speed Mode not Fully Tested */
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#define ANOMALY_05000381 (1)
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/* New Feature: Boot from OTP Memory */
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#define ANOMALY_05000385 (1)
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/* New Feature: bfrom_SysControl() Routine */
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#define ANOMALY_05000386 (1)
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/* New Feature: Programmable Preboot Settings */
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#define ANOMALY_05000387 (1)
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/* Reset Vector Must Not Be in SDRAM Memory Space */
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#define ANOMALY_05000389 (1)
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/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
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#define ANOMALY_05000392 (1)
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/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000393 (1)
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/* New Feature: Log Buffer Functionality */
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#define ANOMALY_05000394 (1)
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/* New Feature: Hook Routine Functionality */
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#define ANOMALY_05000395 (1)
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/* New Feature: Header Indirect Bit */
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#define ANOMALY_05000396 (1)
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/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
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#define ANOMALY_05000397 (1)
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/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
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#define ANOMALY_05000398 (1)
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/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
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#define ANOMALY_05000399 (1)
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/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
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#define ANOMALY_05000401 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000244 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000244 (0)
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#define ANOMALY_05000261 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000312 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000363 (0)
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#endif
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@ -7,7 +7,7 @@
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*/
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/* This file shoule be up to date with:
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* - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
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* - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -251,10 +251,18 @@
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#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* UART Break Signal Issues */
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#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* PPI Does Not Start Properly In Specific Mode */
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#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000266 (0)
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@ -7,7 +7,7 @@
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*/
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/* This file shoule be up to date with:
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* - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
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* - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -132,10 +132,24 @@
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#define ANOMALY_05000322 (1)
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/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
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#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
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/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */
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#define ANOMALY_05000350 (__SILICON_REVISION__ < 3)
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (1)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
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#define ANOMALY_05000359 (1)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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@ -146,5 +160,6 @@
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000363 (0)
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#endif
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@ -93,5 +93,6 @@
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000363 (0)
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#endif
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@ -7,7 +7,7 @@
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*/
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/* This file shoule be up to date with:
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* - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
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* - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -256,10 +256,14 @@
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#define ANOMALY_05000357 (1)
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/* Conflicting Column Address Widths Causes SDRAM Errors */
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#define ANOMALY_05000362 (1)
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/* UART Break Signal Issues */
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#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000158 (0)
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