Merge branches 'pci/host-exynos', 'pci/host-iproc', 'pci/host-keystone', 'pci/host-layerscape', 'pci/host-mvebu', 'pci/host-rcar' and 'pci/host-versatile' into next
* pci/host-exynos: PCI: exynos: Fix INTx enablement statement termination error * pci/host-iproc: PCI: iproc: Add Broadcom iProc PCIe support PCI: iproc: Add DT docs for Broadcom iProc PCIe driver PCI: Export symbols required for loadable host driver modules * pci/host-keystone: PCI: keystone: Don't dereference possible NULL pointer * pci/host-layerscape: PCI: layerscape: Simplify platform_get_resource_byname() failure checking * pci/host-mvebu: PCI: mvebu: Add suspend/resume support * pci/host-rcar: PCI: rcar: Verify that mem_res is 64K-aligned PCI: rcar: Change PCIEPARL and PCIEPARH to PCIEPALR and PCIEPAUR PCI: rcar: Write zeroes to reserved PCIEPARL bits PCI: rcar: Fix position of MSI enable bit * pci/host-versatile: PCI: versatile: Check for devm_ioremap_resource() failures
This commit is contained in:
Bjorn Helgaas
commit
4dd1f57956
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@ -0,0 +1,63 @@
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* Broadcom iProc PCIe controller with the platform bus interface
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Required properties:
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- compatible: Must be "brcm,iproc-pcie"
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- reg: base address and length of the PCIe controller I/O register space
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map, standard PCI properties to define the
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mapping of the PCIe interface to interrupt numbers
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- linux,pci-domain: PCI domain ID. Should be unique for each host controller
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- bus-range: PCI bus numbers covered
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions
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Optional properties:
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- phys: phandle of the PCIe PHY device
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- phy-names: must be "pcie-phy"
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Example:
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pcie0: pcie@18012000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18012000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x28000000 0 0x00010000
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0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
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phys = <&phy 0 5>;
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phy-names = "pcie-phy";
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};
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pcie1: pcie@18013000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18013000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x48000000 0 0x00010000
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0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
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phys = <&phy 1 6>;
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phy-names = "pcie-phy";
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};
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@ -106,4 +106,23 @@ config PCI_VERSATILE
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bool "ARM Versatile PB PCI controller"
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depends on ARCH_VERSATILE
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config PCIE_IPROC
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tristate "Broadcom iProc PCIe controller"
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depends on OF && ARM
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default n
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help
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This enables the iProc PCIe core controller support for Broadcom's
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iProc family of SoCs. An appropriate bus interface driver also needs
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to be enabled
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config PCIE_IPROC_PLATFORM
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tristate "Broadcom iProc PCIe platform bus driver"
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depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)
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depends on OF
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select PCIE_IPROC
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default ARCH_BCM_IPROC
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help
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Say Y here if you want to use the Broadcom iProc PCIe controller
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through the generic platform bus interface
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endmenu
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@ -13,3 +13,5 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
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obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
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obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
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obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
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@ -396,7 +396,7 @@ static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
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/* enable INTX interrupt */
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val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
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IRQ_INTC_ASSERT | IRQ_INTD_ASSERT,
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IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
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exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
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}
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@ -496,11 +496,12 @@ int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
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/* Index 1 is the application reg. space address */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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ks_pcie->app = *res;
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ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);
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if (IS_ERR(ks_pcie->va_app_base))
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return PTR_ERR(ks_pcie->va_app_base);
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ks_pcie->app = *res;
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/* Create legacy IRQ domain */
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ks_pcie->legacy_irq_domain =
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irq_domain_add_linear(ks_pcie->legacy_intc_np,
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@ -127,14 +127,11 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
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pcie->dev = &pdev->dev;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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if (!dbi_base) {
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dev_err(&pdev->dev, "missing *regs* space\n");
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return -ENODEV;
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}
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pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
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if (IS_ERR(pcie->dbi))
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if (IS_ERR(pcie->dbi)) {
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dev_err(&pdev->dev, "missing *regs* space\n");
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return PTR_ERR(pcie->dbi);
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}
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pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"fsl,pcie-scfg");
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@ -129,6 +129,7 @@ struct mvebu_pcie_port {
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size_t memwin_size;
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phys_addr_t iowin_base;
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size_t iowin_size;
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u32 saved_pcie_stat;
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};
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static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
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@ -899,6 +900,35 @@ static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
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pcie->msi->dev = &pcie->pdev->dev;
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}
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static int mvebu_pcie_suspend(struct device *dev)
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{
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struct mvebu_pcie *pcie;
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int i;
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pcie = dev_get_drvdata(dev);
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for (i = 0; i < pcie->nports; i++) {
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struct mvebu_pcie_port *port = pcie->ports + i;
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port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
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}
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return 0;
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}
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static int mvebu_pcie_resume(struct device *dev)
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{
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struct mvebu_pcie *pcie;
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int i;
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pcie = dev_get_drvdata(dev);
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for (i = 0; i < pcie->nports; i++) {
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struct mvebu_pcie_port *port = pcie->ports + i;
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mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
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mvebu_pcie_setup_hw(port);
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}
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return 0;
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}
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static int mvebu_pcie_probe(struct platform_device *pdev)
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{
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struct mvebu_pcie *pcie;
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@ -1056,6 +1086,8 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
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mvebu_pcie_msi_enable(pcie);
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mvebu_pcie_enable(pcie);
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platform_set_drvdata(pdev, pcie);
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return 0;
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}
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@ -1068,12 +1100,18 @@ static const struct of_device_id mvebu_pcie_of_match_table[] = {
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};
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MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
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static struct dev_pm_ops mvebu_pcie_pm_ops = {
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.suspend_noirq = mvebu_pcie_suspend,
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.resume_noirq = mvebu_pcie_resume,
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};
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static struct platform_driver mvebu_pcie_driver = {
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.driver = {
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.name = "mvebu-pcie",
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.of_match_table = mvebu_pcie_of_match_table,
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/* driver unloading/unbinding currently not supported */
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.suppress_bind_attrs = true,
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.pm = &mvebu_pcie_pm_ops,
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},
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.probe = mvebu_pcie_probe,
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};
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@ -301,6 +301,9 @@ static int rcar_pci_probe(struct platform_device *pdev)
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if (!mem_res || !mem_res->start)
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return -ENODEV;
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if (mem_res->start & 0xFFFF)
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return -EINVAL;
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priv = devm_kzalloc(&pdev->dev,
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sizeof(struct rcar_pci_priv), GFP_KERNEL);
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if (!priv)
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|
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@ -138,19 +138,19 @@ static int versatile_pci_probe(struct platform_device *pdev)
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LIST_HEAD(pci_res);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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versatile_pci_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(versatile_pci_base))
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return PTR_ERR(versatile_pci_base);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res)
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return -ENODEV;
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versatile_cfg_base[0] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(versatile_cfg_base[0]))
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return PTR_ERR(versatile_cfg_base[0]);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
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if (!res)
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return -ENODEV;
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versatile_cfg_base[1] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(versatile_cfg_base[1]))
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return PTR_ERR(versatile_cfg_base[1]);
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ret = versatile_pci_parse_request_of_pci_ranges(&pdev->dev, &pci_res);
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if (ret)
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|
|
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@ -0,0 +1,108 @@
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/clk.h>
|
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#include <linux/module.h>
|
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#include <linux/slab.h>
|
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#include <linux/interrupt.h>
|
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#include <linux/platform_device.h>
|
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#include <linux/of_address.h>
|
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#include <linux/of_pci.h>
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#include <linux/of_irq.h>
|
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#include <linux/of_platform.h>
|
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#include <linux/phy/phy.h>
|
||||
|
||||
#include "pcie-iproc.h"
|
||||
|
||||
static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
|
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{
|
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struct iproc_pcie *pcie;
|
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struct device_node *np = pdev->dev.of_node;
|
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struct resource reg;
|
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resource_size_t iobase = 0;
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LIST_HEAD(res);
|
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int ret;
|
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|
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pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL);
|
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if (!pcie)
|
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return -ENOMEM;
|
||||
|
||||
pcie->dev = &pdev->dev;
|
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platform_set_drvdata(pdev, pcie);
|
||||
|
||||
ret = of_address_to_resource(np, 0, ®);
|
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if (ret < 0) {
|
||||
dev_err(pcie->dev, "unable to obtain controller resources\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pcie->base = devm_ioremap(pcie->dev, reg.start, resource_size(®));
|
||||
if (!pcie->base) {
|
||||
dev_err(pcie->dev, "unable to map controller registers\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* PHY use is optional */
|
||||
pcie->phy = devm_phy_get(&pdev->dev, "pcie-phy");
|
||||
if (IS_ERR(pcie->phy)) {
|
||||
if (PTR_ERR(pcie->phy) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
pcie->phy = NULL;
|
||||
}
|
||||
|
||||
ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &iobase);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev,
|
||||
"unable to get PCI host bridge resources\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pcie->resources = &res;
|
||||
|
||||
ret = iproc_pcie_setup(pcie);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "PCIe controller setup failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int iproc_pcie_pltfm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct iproc_pcie *pcie = platform_get_drvdata(pdev);
|
||||
|
||||
return iproc_pcie_remove(pcie);
|
||||
}
|
||||
|
||||
static const struct of_device_id iproc_pcie_of_match_table[] = {
|
||||
{ .compatible = "brcm,iproc-pcie", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
|
||||
|
||||
static struct platform_driver iproc_pcie_pltfm_driver = {
|
||||
.driver = {
|
||||
.name = "iproc-pcie",
|
||||
.of_match_table = of_match_ptr(iproc_pcie_of_match_table),
|
||||
},
|
||||
.probe = iproc_pcie_pltfm_probe,
|
||||
.remove = iproc_pcie_pltfm_remove,
|
||||
};
|
||||
module_platform_driver(iproc_pcie_pltfm_driver);
|
||||
|
||||
MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
|
||||
MODULE_DESCRIPTION("Broadcom iPROC PCIe platform driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,268 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
* Copyright (C) 2015 Broadcom Corporatcommon ion
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/msi.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/phy/phy.h>
|
||||
|
||||
#include "pcie-iproc.h"
|
||||
|
||||
#define CLK_CONTROL_OFFSET 0x000
|
||||
#define EP_MODE_SURVIVE_PERST_SHIFT 1
|
||||
#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
|
||||
#define RC_PCIE_RST_OUTPUT_SHIFT 0
|
||||
#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
|
||||
|
||||
#define CFG_IND_ADDR_OFFSET 0x120
|
||||
#define CFG_IND_ADDR_MASK 0x00001ffc
|
||||
|
||||
#define CFG_IND_DATA_OFFSET 0x124
|
||||
|
||||
#define CFG_ADDR_OFFSET 0x1f8
|
||||
#define CFG_ADDR_BUS_NUM_SHIFT 20
|
||||
#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
|
||||
#define CFG_ADDR_DEV_NUM_SHIFT 15
|
||||
#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
|
||||
#define CFG_ADDR_FUNC_NUM_SHIFT 12
|
||||
#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
|
||||
#define CFG_ADDR_REG_NUM_SHIFT 2
|
||||
#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
|
||||
#define CFG_ADDR_CFG_TYPE_SHIFT 0
|
||||
#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
|
||||
|
||||
#define CFG_DATA_OFFSET 0x1fc
|
||||
|
||||
#define SYS_RC_INTX_EN 0x330
|
||||
#define SYS_RC_INTX_MASK 0xf
|
||||
|
||||
static inline struct iproc_pcie *sys_to_pcie(struct pci_sys_data *sys)
|
||||
{
|
||||
return sys->private_data;
|
||||
}
|
||||
|
||||
/**
|
||||
* Note access to the configuration registers are protected at the higher layer
|
||||
* by 'pci_lock' in drivers/pci/access.c
|
||||
*/
|
||||
static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
|
||||
unsigned int devfn,
|
||||
int where)
|
||||
{
|
||||
struct pci_sys_data *sys = bus->sysdata;
|
||||
struct iproc_pcie *pcie = sys_to_pcie(sys);
|
||||
unsigned slot = PCI_SLOT(devfn);
|
||||
unsigned fn = PCI_FUNC(devfn);
|
||||
unsigned busno = bus->number;
|
||||
u32 val;
|
||||
|
||||
/* root complex access */
|
||||
if (busno == 0) {
|
||||
if (slot >= 1)
|
||||
return NULL;
|
||||
writel(where & CFG_IND_ADDR_MASK,
|
||||
pcie->base + CFG_IND_ADDR_OFFSET);
|
||||
return (pcie->base + CFG_IND_DATA_OFFSET);
|
||||
}
|
||||
|
||||
if (fn > 1)
|
||||
return NULL;
|
||||
|
||||
/* EP device access */
|
||||
val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
|
||||
(slot << CFG_ADDR_DEV_NUM_SHIFT) |
|
||||
(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
|
||||
(where & CFG_ADDR_REG_NUM_MASK) |
|
||||
(1 & CFG_ADDR_CFG_TYPE_MASK);
|
||||
writel(val, pcie->base + CFG_ADDR_OFFSET);
|
||||
|
||||
return (pcie->base + CFG_DATA_OFFSET);
|
||||
}
|
||||
|
||||
static struct pci_ops iproc_pcie_ops = {
|
||||
.map_bus = iproc_pcie_map_cfg_bus,
|
||||
.read = pci_generic_config_read32,
|
||||
.write = pci_generic_config_write32,
|
||||
};
|
||||
|
||||
static void iproc_pcie_reset(struct iproc_pcie *pcie)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* Configure the PCIe controller as root complex and send a downstream
|
||||
* reset
|
||||
*/
|
||||
val = EP_MODE_SURVIVE_PERST | RC_PCIE_RST_OUTPUT;
|
||||
writel(val, pcie->base + CLK_CONTROL_OFFSET);
|
||||
udelay(250);
|
||||
val &= ~EP_MODE_SURVIVE_PERST;
|
||||
writel(val, pcie->base + CLK_CONTROL_OFFSET);
|
||||
msleep(250);
|
||||
}
|
||||
|
||||
static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
|
||||
{
|
||||
u8 hdr_type;
|
||||
u32 link_ctrl;
|
||||
u16 pos, link_status;
|
||||
int link_is_active = 0;
|
||||
|
||||
/* make sure we are not in EP mode */
|
||||
pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
|
||||
if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
|
||||
dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
|
||||
pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
|
||||
PCI_CLASS_BRIDGE_PCI);
|
||||
|
||||
/* check link status to see if link is active */
|
||||
pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
|
||||
pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
|
||||
if (link_status & PCI_EXP_LNKSTA_NLW)
|
||||
link_is_active = 1;
|
||||
|
||||
if (!link_is_active) {
|
||||
/* try GEN 1 link speed */
|
||||
#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
|
||||
#define PCI_TARGET_LINK_SPEED_MASK 0xf
|
||||
#define PCI_TARGET_LINK_SPEED_GEN2 0x2
|
||||
#define PCI_TARGET_LINK_SPEED_GEN1 0x1
|
||||
pci_bus_read_config_dword(bus, 0,
|
||||
PCI_LINK_STATUS_CTRL_2_OFFSET,
|
||||
&link_ctrl);
|
||||
if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
|
||||
PCI_TARGET_LINK_SPEED_GEN2) {
|
||||
link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
|
||||
link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
|
||||
pci_bus_write_config_dword(bus, 0,
|
||||
PCI_LINK_STATUS_CTRL_2_OFFSET,
|
||||
link_ctrl);
|
||||
msleep(100);
|
||||
|
||||
pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
|
||||
pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
|
||||
&link_status);
|
||||
if (link_status & PCI_EXP_LNKSTA_NLW)
|
||||
link_is_active = 1;
|
||||
}
|
||||
}
|
||||
|
||||
dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
|
||||
|
||||
return link_is_active ? 0 : -ENODEV;
|
||||
}
|
||||
|
||||
static void iproc_pcie_enable(struct iproc_pcie *pcie)
|
||||
{
|
||||
writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
|
||||
}
|
||||
|
||||
int iproc_pcie_setup(struct iproc_pcie *pcie)
|
||||
{
|
||||
int ret;
|
||||
struct pci_bus *bus;
|
||||
|
||||
if (!pcie || !pcie->dev || !pcie->base)
|
||||
return -EINVAL;
|
||||
|
||||
if (pcie->phy) {
|
||||
ret = phy_init(pcie->phy);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = phy_power_on(pcie->phy);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "unable to power on PCIe PHY\n");
|
||||
goto err_exit_phy;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
iproc_pcie_reset(pcie);
|
||||
|
||||
pcie->sysdata.private_data = pcie;
|
||||
|
||||
bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops,
|
||||
&pcie->sysdata, pcie->resources);
|
||||
if (!bus) {
|
||||
dev_err(pcie->dev, "unable to create PCI root bus\n");
|
||||
ret = -ENOMEM;
|
||||
goto err_power_off_phy;
|
||||
}
|
||||
pcie->root_bus = bus;
|
||||
|
||||
ret = iproc_pcie_check_link(pcie, bus);
|
||||
if (ret) {
|
||||
dev_err(pcie->dev, "no PCIe EP device detected\n");
|
||||
goto err_rm_root_bus;
|
||||
}
|
||||
|
||||
iproc_pcie_enable(pcie);
|
||||
|
||||
pci_scan_child_bus(bus);
|
||||
pci_assign_unassigned_bus_resources(bus);
|
||||
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
|
||||
pci_bus_add_devices(bus);
|
||||
|
||||
return 0;
|
||||
|
||||
err_rm_root_bus:
|
||||
pci_stop_root_bus(bus);
|
||||
pci_remove_root_bus(bus);
|
||||
|
||||
err_power_off_phy:
|
||||
if (pcie->phy)
|
||||
phy_power_off(pcie->phy);
|
||||
err_exit_phy:
|
||||
if (pcie->phy)
|
||||
phy_exit(pcie->phy);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(iproc_pcie_setup);
|
||||
|
||||
int iproc_pcie_remove(struct iproc_pcie *pcie)
|
||||
{
|
||||
pci_stop_root_bus(pcie->root_bus);
|
||||
pci_remove_root_bus(pcie->root_bus);
|
||||
|
||||
if (pcie->phy) {
|
||||
phy_power_off(pcie->phy);
|
||||
phy_exit(pcie->phy);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(iproc_pcie_remove);
|
||||
|
||||
MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
|
||||
MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2015 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _PCIE_IPROC_H
|
||||
#define _PCIE_IPROC_H
|
||||
|
||||
#define IPROC_PCIE_MAX_NUM_IRQS 6
|
||||
|
||||
/**
|
||||
* iProc PCIe device
|
||||
* @dev: pointer to device data structure
|
||||
* @base: PCIe host controller I/O register base
|
||||
* @resources: linked list of all PCI resources
|
||||
* @sysdata: Per PCI controller data
|
||||
* @root_bus: pointer to root bus
|
||||
* @phy: optional PHY device that controls the Serdes
|
||||
* @irqs: interrupt IDs
|
||||
*/
|
||||
struct iproc_pcie {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
struct list_head *resources;
|
||||
struct pci_sys_data sysdata;
|
||||
struct pci_bus *root_bus;
|
||||
struct phy *phy;
|
||||
int irqs[IPROC_PCIE_MAX_NUM_IRQS];
|
||||
};
|
||||
|
||||
int iproc_pcie_setup(struct iproc_pcie *pcie);
|
||||
int iproc_pcie_remove(struct iproc_pcie *pcie);
|
||||
|
||||
#endif /* _PCIE_IPROC_H */
|
||||
|
|
@ -64,8 +64,8 @@
|
|||
#define LAR_ENABLE (1 << 1)
|
||||
|
||||
/* PCIe address reg & mask */
|
||||
#define PCIEPARL(x) (0x03400 + ((x) * 0x20))
|
||||
#define PCIEPARH(x) (0x03404 + ((x) * 0x20))
|
||||
#define PCIEPALR(x) (0x03400 + ((x) * 0x20))
|
||||
#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
|
||||
#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
|
||||
#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
|
||||
#define PAR_ENABLE (1 << 31)
|
||||
|
|
@ -341,8 +341,9 @@ static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
|
|||
else
|
||||
res_start = res->start;
|
||||
|
||||
rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPARH(win));
|
||||
rcar_pci_write_reg(pcie, lower_32_bits(res_start), PCIEPARL(win));
|
||||
rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
|
||||
rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
|
||||
PCIEPALR(win));
|
||||
|
||||
/* First resource is for IO */
|
||||
mask = PAR_ENABLE;
|
||||
|
|
@ -501,7 +502,7 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
|
|||
|
||||
/* Enable MSI */
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI))
|
||||
rcar_pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
|
||||
rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
|
||||
|
||||
/* Finish initialization - establish a PCI Express link */
|
||||
rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
|
||||
|
|
|
|||
|
|
@ -2493,6 +2493,7 @@ u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
|
|||
*pinp = pin;
|
||||
return PCI_SLOT(dev->devfn);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_common_swizzle);
|
||||
|
||||
/**
|
||||
* pci_release_region - Release a PCI bar
|
||||
|
|
|
|||
|
|
@ -1995,6 +1995,7 @@ err_out:
|
|||
kfree(b);
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_create_root_bus);
|
||||
|
||||
int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -139,6 +139,7 @@ void pci_stop_root_bus(struct pci_bus *bus)
|
|||
/* stop the host bridge */
|
||||
device_release_driver(&host_bridge->dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_stop_root_bus);
|
||||
|
||||
void pci_remove_root_bus(struct pci_bus *bus)
|
||||
{
|
||||
|
|
@ -158,3 +159,4 @@ void pci_remove_root_bus(struct pci_bus *bus)
|
|||
/* remove the host bridge */
|
||||
device_unregister(&host_bridge->dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_remove_root_bus);
|
||||
|
|
|
|||
|
|
@ -1750,3 +1750,4 @@ void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
|
|||
__pci_bus_assign_resources(bus, &add_list, NULL);
|
||||
BUG_ON(!list_empty(&add_list));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);
|
||||
|
|
|
|||
|
|
@ -65,3 +65,4 @@ void pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
|
|||
for_each_pci_dev(dev)
|
||||
pdev_fixup_irq(dev, swizzle, map_irq);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_fixup_irqs);
|
||||
|
|
|
|||
Loading…
Reference in New Issue